Renesas M16C/29 Hardware Manual

8/17/2019 Renesas M16C/29 Hardware Manual

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RENESAS MCU

M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group

16

Rev. 1.11Revision Date: Dec.11, 2006

Hardware Manual

www.renesas.com

All information contained in these materials, including products and product specifications,represents information on the product at the time of publication and is subject to change byRenesas Technology Corp. without notice. Please review the latest information published

by Renesas Technology Corp. through various means, including the Renesas TechnologyCorp. website (http://www.renesas.com).

REJ09B0101-0111


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1. This document is provided for reference purposes only so that Renesas customers may select the appropriateRenesas products for their use. Renesas neither makes warranties or representations with respect to theaccuracy or completeness of the information contained in this document nor grants any license to anyintellectual property rights or any other rights of Renesas or any third party with respect to the information in

this document.2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arisingout of the use of any information in this document, including, but not limited to, product data, diagrams, charts,programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of militaryapplications such as the development of weapons of mass destruction or for the purpose of any other militaryuse. When exporting the products or technology described herein, you should follow the applicable exportcontrol laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, andapplication circuit examples, is current as of the date this document is issued. Such information, however, issubject to change without any prior notice. Before purchasing or using any Renesas products listed in thisdocument, please confirm the latest product information with a Renesas sales office. Also, please pay regularand careful attention to additional and different information to be disclosed by Renesas such as that disclosedthrough our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas

assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the informationincluded in this document.6. When using or otherwise relying on the information in this document, you should evaluate the information in

light of the total system before deciding about the applicability of such information to the intended application.Renesas makes no representations, warranties or guaranties regarding the suitability of its products for anyparticular application and specifically disclaims any liability arising out of the application and use of theinformation in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesasproducts are not designed, manufactured or tested for applications or otherwise in systems the failure ormalfunction of which may cause a direct threat to human life or create a risk of human injury or which requireespecially high quality and reliability such as safety systems, or equipment or systems for transportation andtraffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communicationtransmission. If you are considering the use of our products for such purposes, please contact a Renesassales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who

elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless RenesasTechnology Corp., its affiliated companies and their officers, directors, and employees against any and alldamages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respectto the maximum rating, operating supply voltage range, movement power voltage range, heat radiationcharacteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions ordamages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specificcharacteristics such as the occurrence of failure at a certain rate and malfunctions under certain useconditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and

injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design forhardware and software including but not limited to redundancy, fire control and malfunction prevention,appropriate treatment for aging degradation or any other applicable measures. Among others, since theevaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products orsystem manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesasproducts are attached or affixed, the risk of accident such as swallowing by infants and small children is veryhigh. You should implement safety measures so that Renesas products may not be easily detached from yourproducts. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior writtenapproval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in thisdocument, Renesas semiconductor products, or if you have any other inquiries.

Notes regarding these materials


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General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the

products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General

Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description

in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.

The input pins of CMOS products are generally in the high-impedance state. In operation with an

unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an

associated shoot-through current flows internally, and malfunctions occur due to the false

recognition of the pin state as an input signal become possible. Unused pins should be handled as

described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins

are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are

not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function

are not guaranteed from the moment when power is supplied until the power reaches the level at

which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

The reserved addresses are provided for the possible future expansion of functions. Do not access

these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become stable.

When switching the clock signal during program execution, wait until the target clock signal has

stabilized.

When the clock signal is generated with an external resonator (or from an external oscillator) during

a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,

when switching to a clock signal produced with an external resonator (or by an external oscillator)

while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different type number, confirm that thechange will not lead to problems.

The characteristics of MPU/MCU in the same group but having different type numbers may differ

because of the differences in internal memory capacity and layout pattern. When changing to

products of different type numbers, implement a system-evaluation test for each of the products.


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How to Use This Manual

1. Purpose and Target Readers

This manual is designed to provide the user with an understanding of the hardware functions and electrical

characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic

knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.

The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral

functions, and electrical characteristics; and usage notes.

Particular attention should be paid to the precautionary notes when using the manual. These notes occur

within the body of the text, at the end of each section, and in the Usage Notes section.

The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer

to the text of the manual for details.

The following documents apply to the M16C/29 Group. Make sure to refer to the latest versions of these documents.

The newest versions of the documents listed may be obtained from the Renesas Technology Web site.

Document Type Description Document Title Document No.

Datasheet Hardware overview and electrical characteristics M16C/29 Group

Datasheet

REJ09B0101

Hardware manual Hardware specifications (pin assignments,

memory maps, peripheral function

specifications, electrical characteristics, timing

charts) and operation description

Note: Refer to the application notes for details on

using peripheral functions.

M16C/29 Group

Hardware Manual

This hardware

manual

Software manual Description of CPU instruction set M16C/60,

M16C/20,

M16C/Tiny Series

Software Manual

REJ09B0137

Application note Information on using peripheral functions and

application examples

Sample programs

Information on writing programs in assembly

language and C

Available from Renesas

Technology Web site.

Renesas

technical update

Product specifications, updates on documents,

etc.


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2. Notation of Numbers and Symbols

The notation conventions for register names, bit names, numbers, and symbols used in this manual are described

below.

(1) Register Names, Bit Names, and Pin NamesRegisters, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word

“register,” “bit,” or “pin” to distinguish the three categories.

Examples the PM03 bit in the PM0 register

P35 pin, VCC pin

(2) Notation of Numbers

The indication “2” is appended to numeric values given in binary format. However, nothing is appended to the

values of single bits. The indication “16” is appended to numeric values given in hexadecimal format. Nothing

is appended to numeric values given in decimal format.

Examples Binary: 112

Hexadecimal: EFA016

Decimal: 1234


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3. Register Notation

The symbols and terms used in register diagrams are described below.

*1

Blank: Set to 0 or 1 according to the application.

0: Set to 0.

1: Set to 1.

X: Nothing is assigned.

*2

RW: Read and write.

RO: Read only.

WO: Write only.

−: Nothing is assigned.

*3

• Reserved bit

Reserved bit. Set to specified value.

*4

• Nothing is assigned

Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.

• Do not set to a value

Operation is not guaranteed when a value is set.

• Function varies according to the operating mode.

The function of the bit varies with the peripheral function mode. Refer to the register diagram for information

on the individual modes.

XXX Register

Symbol Address After Reset XXX XXX 0016

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

XXX bits 1 0: XXX

0 1: XXX

1 0: Do not set.

1 1: XXX

b1 b0

XXX1

XXX0

XXX4

Reserved bits

XXX5

XXX7

XXX6

Function

Nothing is assigned. If necessary, set to 0.When read, the content is undefined.

XXX bit

Function varies according to the operatingmode.

Set to 0.

0

(b3)

(b2)

RW

RW

RW

RW

WO

RW

RO

XXX bits

0: XXX1: XXX

*1

*2

*3

*4


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4. List of Abbreviations and Acronyms

Abbreviation Full Form

ACIA Asynchronous Communication Interface Adapter bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant BitNC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SFR Special Function Registers

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator


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A-1

Table of Contents

Quick Reference to Pages Classified by Address______________________B-1

1. Overview ____________________________________________________ 1

1.1 Features ........................................................................................................................... 1

1.1.1 Applications ................................................................................................................ 1

1.1.2 Specifications ............................................................................................................. 2

1.2 Block Diagram .................................................................................................................. 4

1.3 Product List ....................................................................................................................... 6

1.4 Pin Assignments ............................................................................................................. 12

1.5 Pin Description ............................................................................................................... 18

2. Central Processing Unit (CPU) __________________________________ 21

2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 21

2.2 Address Registers (A0 and A1) ...................................................................................... 21

2.3 Frame Base Register (FB) .............................................................................................. 22

2.4 Interrupt Table Register (INTB) ....................................................................................... 22

2.5 Program Counter (PC) .................................................................................................... 22

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).......................................... 22

2.7 Static Base Register (SB) ............................................................................................... 22

2.8 Flag Register (FLG) ........................................................................................................ 22

2.8.1 Carry Flag (C Flag) .................................................................................................. 22

2.8.2 Debug Flag (D Flag)................................................................................................. 22

2.8.3 Zero Flag (Z Flag) ................................................................................................... 22

2.8.4 Sign Flag (S Flag) .................................................................................................... 22

2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 22

2.8.6 Overflow Flag (O Flag) ............................................................................................. 22

2.8.7 Interrupt Enable Flag (I Flag) ................................................................................... 222.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 22

2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 22

2.8.10 Reserved Area ....................................................................................................... 22

3. Memory ____________________________________________________ 23

4. Special Function Registers (SFRs) _______________________________ 24


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5. Resets _____________________________________________________ 35

5.1 Hardware Reset.............................................................................................................. 35

5.1.1 Hardware Reset 1 .................................................................................................... 35

5.1.2 Brown-Out Detection Reset (Hardware Reset 2) ..................................................... 35

5.2 Software Reset ............................................................................................................... 36

5.3 Watchdog Timer Reset ................................................................................................... 36

5.4 Oscillation Stop Detection Reset .................................................................................... 36

5.5 Voltage Detection Circuit ................................................................................................ 38

5.5.1 Low Voltage Detection Interrupt ............................................................................... 41

5.5.2. Limitations on Stop Mode........................................................................................ 43

5.5.3. Limitations on WAIT Instruction............................................................................... 43

6. Processor Mode _____________________________________________ 447. Clock Generation Circuit _______________________________________ 47

7.1 Main Clock ...................................................................................................................... 54

7.2 Sub Clock ....................................................................................................................... 55

7.3 On-chip Oscillator Clock ................................................................................................. 56

7.4 PLL Clock ....................................................................................................................... 56

7.5 CPU Clock and Peripheral Function Clock ..................................................................... 58

7.5.1 CPU Clock................................................................................................................ 58

7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32, fCAN0) . 587.5.3 ClockOutput Function............................................................................................... 58

7.6 Power Control ................................................................................................................. 59

7.6.1 Normal Operation Mode ........................................................................................... 59

7.6.2 Wait Mode ................................................................................................................ 60

7.6.3 Stop Mode ............................................................................................................... 62

7.7 System Clock Protective Function .................................................................................. 66

7.8 Oscillation Stop and Re-oscillation Detect Function ....................................................... 66

7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)........................... 677.8.2 Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect Interrupt) ... 67

7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function ............................. 68

8. Protection __________________________________________________ 69


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9. Interrupts ___________________________________________________ 70

9.1 Type of Interrupts ............................................................................................................ 70

9.1.1 Software Interrupts ................................................................................................... 71

9.1.2 Hardware Interrupts ................................................................................................. 72

9.2 Interrupts and Interrupt Vector ........................................................................................ 73

9.2.1 Fixed Vector Tables .................................................................................................. 73

9.2.2 Relocatable Vector Tables ........................................................................................ 74

9.3 Interrupt Control .............................................................................................................. 75

9.3.1 I Flag ........................................................................................................................ 78

9.3.2 IR Bit ........................................................................................................................ 78

9.3.3 ILVL2 to ILVL0 Bits and IPL...................................................................................... 78

9.4 Interrupt Sequence ......................................................................................................... 79

9.4.1 Interrupt Response Time .......................................................................................... 809.4.2 Variation of IPL when Interrupt Request is Accepted ............................................... 80

9.4.3 Saving Registers ...................................................................................................... 81

9.4.4 Returning from an Interrupt Routine......................................................................... 83

9.5 Interrupt Priority .............................................................................................................. 83

9.5.1 Interrupt Priority Resolution Circuit .......................................................................... 83 ______

9.6 INT Interrupt ................................................................................................................... 85 ______

9.7 NMI Interrupt ................................................................................................................... 86

9.8 Key Input Interrupt .......................................................................................................... 869.9 CAN0 Wake-up Interrupt ................................................................................................ 87

9.10 Address Match Interrupt ............................................................................................... 87

10. Watchdog Timer ____________________________________________ 89

10.1 Count Source Protective Mode..................................................................................... 90

11. DMAC ____________________________________________________ 91

11.1 Transfer Cycles ............................................................................................................ 96

11.1.1 Effect of Source and Destination Addresses ......................................................... 9611.1.2 Effect of Software Wait .......................................................................................... 96

11.2. DMA Transfer Cycles ................................................................................................... 98

11.3 DMA Enable .................................................................................................................. 99

11.4 DMA Request................................................................................................................ 99

11.5 Channel Priority and DMA Transfer Timing................................................................ 100


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12. Timers ___________________________________________________ 101

12.1 Timer A ...................................................................................................................... 103

12.1.1 Timer Mode .......................................................................................................... 106

12.1.2 Event Counter Mode ............................................................................................ 107

12.1.3 One-shot Timer Mode .......................................................................................... 112

12.1.4 Pulse Width Modulation (PWM) Mode ................................................................. 114

12.2 Timer B ...................................................................................................................... 117

12.2.1 Timer Mode ......................................................................................................... 119

12.2.2 Event Counter Mode ............................................................................................ 120

12.2.3 Pulse Period and Pulse Width Measurement Mode............................................ 121

12.2.4 A/D Trigger Mode ................................................................................................ 123

12.3 Three-phase Motor Control Timer Function................................................................ 125

12.3.1 Position-Data-Retain Function ............................................................................. 13612.3.2 Three-phase/Port Output Switch Function ........................................................... 138

13. Timer S __________________________________________________ 140

13.1 Base Timer ................................................................................................................. 151

13.1.1 Base Timer Reset Register(G1BTRR) ................................................................. 155

13.2 Interrupt Operation ..................................................................................................... 156

13.3 DMA Support .............................................................................................................. 156

13.4 Time Measurement Function ...................................................................................... 157

13.5 Waveform Generating Function .................................................................................. 161

13.5.1 Single-Phase Waveform Output Mode ................................................................. 162

13.5.2 Phase-Delayed Waveform Output Mode.............................................................. 164

13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode ................................. 166

13.6 I/O Port Function Select ............................................................................................. 168

13.6.1 INPC17 Alternate Input Pin Selection .................................................................. 169 ________

13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17 .......................................... 169

14. Serial I/O _________________________________________________ 17014.1 UARTi (i=0 to 2) .......................................................................................................... 170

14.1.1 Clock Synchronous serial I/O Mode ..................................................................... 180

14.1.2 Clock Asynchronous Serial I/O (UART) Mode ..................................................... 188

14.1.3 Special Mode 1 (I2C bus mode)(UART2) ............................................................. 196

14.1.4 Special Mode 2 (UART2) ..................................................................................... 206

14.1.5 Special Mode 3 (IEBus mode)(UART2) .............................................................. 210

14.1.6 Special Mode 4 (SIM Mode) (UART2)................................................................. 212


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14.2 SI/O3 and SI/O4 ........................................................................................................ 217

14.2.2 CLK Polarity Selection ........................................................................................ 220

14.2.1 SI/Oi Operation Timing ........................................................................................ 220

14.2.3 Functions for Setting an SOUTi Initial Value ....................................................... 221

15. A/D Converter _____________________________________________ 222

15.1 Operating Modes ........................................................................................................ 228

15.1.1 One-Shot Mode .................................................................................................... 228

15.1.2 Repeat mode........................................................................................................ 230

15.1.3 Single Sweep Mode ............................................................................................ 232

15.1.4 Repeat Sweep Mode 0......................................................................................... 234

15.1.5 Repeat Sweep Mode 1......................................................................................... 236

15.1.6 Simultaneous Sample Sweep Mode .................................................................... 238

15.1.7 Delayed Trigger Mode 0 ....................................................................................... 241

15.1.8 Delayed Trigger Mode 1 ....................................................................................... 247

15.2 Resolution Select Function ......................................................................................... 253

15.3 Sample and Hold ........................................................................................................ 253

15.4 Power Consumption Reducing Function .................................................................... 253

15.5 Output Impedance of Sensor under A/D Conversion ................................................. 254

16. Multi-master I2C bus Interface _________________________________ 255

16.1 I2

C0 Data Shift Register (S00 register) ....................................................................... 26416.2 I2C0 Address Register (S0D0 register) ....................................................................... 264

16.3 I2C0 Clock Control Register (S20 register) ................................................................ 265

16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) ..................................... 265

16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) .............................................. 265

16.3.3 Bit 6: ACK Bit (ACKBIT) ...................................................................................... 265

16.3.4 Bit 7: ACK Clock Bit (ACK-CLK).......................................................................... 265

16.4 I2C0 Control Register 0 (S1D0) ................................................................................. 267

16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) ..................................................................... 26716.4.2 Bit 3: I2C Interface Enable Bit (ES0).................................................................... 267

16.4.3 Bit 4: Data Format Select Bit (ALS)..................................................................... 267

16.4.4 Bit 6: I2C bus Interface Reset Bit (IHR) ............................................................... 267

16.4.5 Bit 7: I2C bus Interface Pin Input Level Select Bit (TISS) .................................... 268

16.5 I2C0 Status Register (S10 register) ........................................................................... 269

16.5.1 Bit 0: Last Receive Bit (LRB)............................................................................... 269

16.5.2 Bit 1: General Call Detection Flag (ADR0) .......................................................... 269


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16.5.3 Bit 2: Slave Address Comparison Flag (AAS) ..................................................... 269

16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ........................................................... 269

16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN) ............................................. 270

16.5.6 Bit 5: Bus Busy Flag (BB) .................................................................................... 270

16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX)....... 271

16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ................ 271

16.6 I2C0 Control Register 1 (S3D0 register) .................................................................... 272

16.6.1 Bit 0: Interrupt Enable Bit by STOP Condition (SIM ) .......................................... 272

16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT) .................. 272

16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC .................................................... 273

16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM .................... 274

16.6.5 Bits 6,7 : I2C System Clock Select Bits ICK0, ICK1 ............................................ 274

16.6.6 Address Receive in STOP/WAIT Mode ............................................................... 27416.7 I2C0 Control Register 2 (S4D0 Register) ................................................................... 275

16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) .......................................... 276

16.7.2 Bit1: Time-Out Detection Flag (TOF ).................................................................. 276

16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL) .......................................... 276

16.7.4 Bits 3,4,5: I2C System Clock Select Bits (ICK2-4) ............................................... 276

16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN).......................... 276

16.8 I2C0 START/STOP Condition Control Register (S2D0 Register) ............................... 277

16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) ............................ 277

16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP) .......................................... 277

16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS) ...................................................... 277

16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL) ....................... 277

16.9 START Condition Generation Method ....................................................................... 278

16.10 START Condition Duplicate Protect Function ........................................................... 279

16.11 STOP Condition Generation Method ........................................................................ 279

16.12 START/STOP Condition Detect Operation ............................................................... 281

16.13 Address Data Communication ................................................................................. 282

16.13.1 Example of Master Transmit ............................................................................. 282

16.13.2 Example of Slave Receive ................................................................................ 283

16.14 Precautions............................................................................................................... 284

17. CAN Module ______________________________________________ 287

17.1 CAN Module-Related Registers ................................................................................. 288

17.1.1 CAN0 Message Box ............................................................................................. 289

17.1.2 Acceptance Mask Registers ................................................................................. 291

17.1.3 CAN SFR Registers ............................................................................................. 292


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17.2 Operating Modes ........................................................................................................ 300

17.2.1 CAN Reset/Initialization Mode ............................................................................. 300

17.2.2 CAN Operating Mode ........................................................................................... 301

17.2.3 CAN Sleep Mode ................................................................................................. 301

17.2.4 CAN Interface Sleep Mode .................................................................................. 302

17.2.5 Bus Off State ........................................................................................................ 302

17.3 Configuration of the CAN Module System Clock ........................................................ 303

17.3.1 Bit Timing Configuration ....................................................................................... 303

17.3.2 Bit-rate .................................................................................................................. 304

17.4 Acceptance Filtering Function and Masking Function ................................................ 305

17.5 Acceptance Filter Support Unit (ASU) ........................................................................ 306

17.6 BasicCAN Mode ......................................................................................................... 307

17.7 Return from Bus off Function...................................................................................... 30817.8 Time Stamp Counter and Time Stamp Function......................................................... 308

17.9 Listen-Only Mode ....................................................................................................... 308

17.10 Reception and Transmission .................................................................................... 309

17.10.1 Reception ........................................................................................................... 310

17.10.2 Transmission ...................................................................................................... 311

17.11 CAN Interrupts .......................................................................................................... 312

18. CRC Calculation Circuit _____________________________________ 313

18.1 CRC Snoop ................................................................................................................ 313

19. Programmable I/O Ports _____________________________________ 316

19.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10) ....................................... 316

19.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) ......................................................... 316

19.3 Pull-up Control Register 0 to 2 (PUR0 to PUR2 Registers)........................................ 316

19.4 Port Control Register (PCR Register) ......................................................................... 316

19.5 Pin Assignment Control Register (PACR)................................................................... 317

19.6 Digital Debounce Function ......................................................................................... 317

20. Flash Memory Version ______________________________________ 330

20.1 Flash Memory Performance ....................................................................................... 330

20.1.1 Boot Mode ........................................................................................................... 331

20.2 Memory Map............................................................................................................... 332

20.3 Functions To Prevent Flash Memory from Rewriting .................................................. 335

20.3.1 ROM Code Protect Function ................................................................................ 335

20.3.2 ID Code Check Function ...................................................................................... 335


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20.4 CPU Rewrite Mode ..................................................................................................... 337

20.4.1 EW Mode 0 .......................................................................................................... 338

20.4.2 EW Mode 1 .......................................................................................................... 338

20.5 Register Description ................................................................................................... 339

20.5.1 Flash Memory Control Register 0 (FMR0) ........................................................... 339



20.6 Precautions in CPU Rewrite Mode ............................................................................. 345

20.6.1 Operation Speed .................................................................................................. 345

20.6.2 Prohibited Instructions.......................................................................................... 345

20.6.3 Interrupts .............................................................................................................. 345

20.6.4 How to Access...................................................................................................... 345

20.6.5 Writing in the User ROM Area .............................................................................. 34520.6.6 DMA Transfer ....................................................................................................... 346

20.6.7 Writing Command and Data ................................................................................. 346

20.6.8 Wait Mode ............................................................................................................ 346

20.6.9 Stop Mode ............................................................................................................ 346

20.6.10 Low Power Consumption Mode and On-Chip Oscillator-Low Power Consumption Mode ... 346

20.7 Software Commands .................................................................................................. 347

20.7.1 Read Array Command (FF16)............................................................................... 347

20.7.2 Read Status Register Command (7016) ............................................................... 347

20.7.3 Clear Status Register Command (5016) ............................................................... 347

20.7.4 Program Command (4016) ................................................................................... 348

20.7.5 Block Erase .......................................................................................................... 349

20.8 Status Register ........................................................................................................... 351

20.8.1 Sequence Status (SR7 and FMR00 Bits )............................................................ 351

20.8.2 Erase Status (SR5 and FMR07 Bits) ................................................................... 351

20.8.3 Program Status (SR4 and FMR06 Bits) ............................................................... 351

20.8.4 Full Status Check ................................................................................................. 352

20.9 Standard Serial I/O Mode ........................................................................................... 354

20.9.1 ID Code Check Function ...................................................................................... 354

20.9.2 Example of Circuit Application in Standard Serial I/O Mode ................................ 358

20.10 Parallel I/O Mode ...................................................................................................... 360

20.10.1 ROM Code Protect Function .............................................................................. 360

20.11 CAN I/O Mode .......................................................................................................... 361

20.11.1 ID code check function ....................................................................................... 361

20.11.2 Example of Circuit Application in CAN I/O Mode................................................ 365


16/496

A-9

21. Electrical Characteristics _____________________________________ 366

21.1 Normal version ........................................................................................................... 366

21.2 T version ..................................................................................................................... 387

21.3 V Version .................................................................................................................... 408

22. Usage Notes ______________________________________________ 421

22.1 SFRs........................................................................................................................... 421

22.1.1 For 80-Pin Package ............................................................................................. 421

22.1.2 For 64-Pin Package ............................................................................................. 421

22.1.3 Register Setting.................................................................................................... 421

22.2 Clock Generation Circuit ............................................................................................. 422

22.2.1 PLL Frequency Synthesizer ................................................................................. 422

22.2.2 Power Control ...................................................................................................... 42322.3 Protection ................................................................................................................... 425

22.4 Interrupts .................................................................................................................... 426

22.4.1 Reading Address 0000016 .....................................................................................................426

22.4.2 Setting the SP ...................................................................................................... 426 _______

22.4.3 NMI Interrupt ....................................................................................................... 426

22.4.4 Changing the Interrupt Generate Factor .............................................................. 426 ______

22.4.5 INT Interrupt ......................................................................................................... 427

22.4.6 Rewrite the Interrupt Control Register .................................................................. 428

22.4.7 Watchdog Timer Interrupt ..................................................................................... 428

22.5 DMAC ......................................................................................................................... 429

22.5.1 Write to DMAE Bit in DMiCON Register ............................................................... 429

22.6 Timers ......................................................................................................................... 430

22.6.1 Timer A ................................................................................................................. 430

22.6.2 Timer B ................................................................................................................. 433

22.6.3 Three-phase Motor Control Timer Function ......................................................... 434

22.7 Timer S ....................................................................................................................... 435

22.7.1 Rewrite the G1IR Register .................................................................................. 435

22.7.2 Rewrite the ICOCiIC Register ............................................................................. 436

22.7.3 Waveform Generating Function .......................................................................... 436

22.7.4 IC/OC Base Timer Interrupt .................................................................................. 436

22.8 Serial I/O..................................................................................................................... 437

22.8.1 Clock-Synchronous Serial I/O .............................................................................. 437

22.8.2 UART Mode.......................................................................................................... 438

22.8.3 SI/O3, SI/O4 ......................................................................................................... 438


17/496

A-10

22.9 A/D Converter ............................................................................................................. 439

22.10 Multi-Master I2C bus Interface ................................................................................. 441

22.10.1 Writing to the S00 Register ................................................................................ 441

22.10.2 AL Flag ............................................................................................................... 441

22.11 CAN Module ............................................................................................................. 442

22.11.1 Reading C0STR Register ................................................................................... 442

22.11.2 CAN Transceiver in Boot Mode .......................................................................... 444

22.12 Programmable I/O Ports ........................................................................................... 445

22.13 Electric Characteristic Differences Between Mask ROM.......................................... 446

22.14 Mask ROM Version................................................................................................... 447

22.14.1 Internal ROM Area ............................................................................................. 447

22.14.2 Reserved Bit ....................................................................................................... 447

22.15 Flash Memory Version .............................................................................................. 44822.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ........................................ 448

22.15.2 Stop Mode .......................................................................................................... 448

22.15.3 Wait Mode .......................................................................................................... 448

22.15.4 Low PowerDissipation Mode, On-Chip Oscillator Low Power Dissipation Mode .. 448

22.15.5 Writing Command and Data ............................................................................... 448

22.15.6 Program Command ............................................................................................ 448

22.15.7 Operation Speed ................................................................................................ 448

22.15.8 Instructions Inhibited Against Use ...................................................................... 448

22.15.9 Interrupts ............................................................................................................ 449

22.15.10 How to Access.................................................................................................. 449

22.15.11 Writing in the User ROM Area .......................................................................... 449

22.15.12 DMA Transfer ................................................................................................... 449

22.15.13 Regarding Programming/Erasure Times and Execution Time ......................... 449

22.15.14 Definition of Programming/Erasure Times ....................................................... 450

22.15.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle products

( Normal: U7, U9; T-ver./V-ver.: U7) .............................................................. 450

22.15.16 Boot Mode ........................................................................................................ 450

22.16 Noise ........................................................................................................................ 451

22.17 Instruction for a Device Use ..................................................................................... 452


18/496

A-11

Appendix 1. Package Dimensions ________________________________ 453

Appendix 2. Functional Comparison _______________________________ 454

Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) .... 454

Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) ............... 455

Register Index ________________________________________________ 456


19/496

B-1

Quick Reference to Pages Classified by Address

CAN0 wakeup interrupt control register C01WKIC 76

CAN0 successful reception interrupt control register C0RECIC 76

CAN0 successful transmission interrupt control regiser C0TRMIC 76INT3 interrupt control register INT3IC 76

IC/OC 0 interrupt control register ICOC0IC 76

IC/OC 1 interrupt control register, ICOC1IC 76

I2C bus interface interrupt control register IICIC 76

IC/OC base timer interrupt control register, BTIC 76

SCLSDA interrupt control register SCLDAIC 76

SI/O4 interrupt control register, S4IC 76

INT5 interrupt control register INT5IC 76

SI/O3 interrupt control register, S3IC 76


UART2 Bus collision detection interrupt control register BCNIC 76

DMA0 interrupt control register DM0IC 76

DMA1 interrupt control register DM1IC 76

CAN0 error interrupt control register C01ERRIC 76

A/D conversion interrupt control register ADIC 76

Key input interrupt control register KUPIC 76UART2 transmit interrupt control register S2TIC 76

UART2 receive interrupt control register S2RIC 76

UART0 transmit interrupt control register S0TIC 76


UART1 transmit interrupt control register S1TIC 76


Timer A0 interrupt control register TA0IC 76





Timer B0 interrupt control register TB0IC 76






CAN0 message box 0: Identifier/DLC 289

CAN 0 message box 0: Data field 289

CAN0 message box 0: Time stamp 289


CAN 0 message box 1: Data field 289

CAN0 message box 1: Time stamp 289

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Address

Note: The blank areas are reserved and cannot be accessed by users.

Register Symbol Page

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

004C16

004D16

004E16

004F16

005016

005116

005216

005316

005416

005516

005616

005716

005816

005916

005A16

005B16

005C16

005D16

005E16

005F16

006016

006116

006216

006316

006416

006516

006616

006716

006816

006916

006A16

006B16

006C16

006D16

006E16

006F16

007016

007116

007216

007316

007416

007516

007616

007716

007816

007916

007A16

007B16

007C16

007D16

007E16

007F16

Processor mode register 0 PM0 44


System clock control register 0 CM0 49

System clock control register 1 CM1 50

Address match interrupt enable register AIER 88

Protect register PRCR 69

Oscillation stop detection register CM2 51

Watchdog timer start register WDTS 90

Watchdog timer control register WDC 90

Address match interrupt register 0 RMAD0 88

Address match interrupt register 1 RMAD1 88

Voltage detection register 1 VCR1 41

Voltage detection register 2 VCR2 41

PLL control register 0 PLC0 53


Low voltage detection interrupt register D4INT 42

DMA0 source pointer SAR0 95

DMA0 destination pointer DAR0 95

DMA0 transfer counter TCR0 95

DMA0 control register DM0CON 94

DMA1 source pointer SAR1 95

DMA1 destination pointer DAR1 95

DMA1 transfer counter TCR1 95

DMA1 control register DM1CON 94

Address Register Symbol Page


20/496

B-2


008016

008116

008216

008316

008416

008516

008616

008716

008816

008916

008A16

008B16

008C16

008D16

008E16

008F16

009016

009116

009216

009316

009416

009516

009616

009716

009816

009916

009A16

009B16

009C16

009D16

009E16

009F16

00A016

00A116

00A216

00A316

00A416

00A516

00A616

00A716

00A816

00A916

00AA16

00AB16

00AC16

00AD16

00AE16

00AF16

00B016

00B116

00B216

00B316

00B416

00B516

00B616

00B716

00B816

00B916

00BA16

00BB16

00BC16

00BD16

00BE16

00BF16

Address



00C016

00C116

00C216

00C316

00C416

00C516

00C616

00C716

00C816

00C916

00CA16

00CB16

00CC16

00CD16

00CE16

00CF16

00D016

00D116

00D216

00D316

00D416

00D516

00D616

00D716

00D816

00D916

00DA16

00DB16

00DC16

00DD16

00DE16

00DF16

00E016

00E116

00E216

00E316

00E416

00E516

00E616

00E716

00E816

00E916

00EA16

00EB16

00EC16

00ED16

00EE16

00EF16

00F016

00F116

00F216

00F316

00F416

00F516

00F616

00F716

00F816

00F916

00FA16

00FB16

00FC16

00FD16

00FE16

00FF16


CAN0 message box 2: Data field 289

CAN0 message box 2: time stamp 289
























21/496

B-3


010016

010116

010216

010316

010416

010516

010616

010716

010816

010916

010A16

010B16

010C16

010D16

010E16

010F16

011016

011116

011216

011316

011416

011516

011616

011716

011816

011916

011A16

011B16

011C16

011D16

011E16

011F16

012016

012116

012216

012316

012416

012516

012616

012716

012816

012916

012A16

012B16

012C16

012D16

012E16

012F16

013016

013116

013216

013316

013416

013516

013616

013716

013816

013916

013A16

013B16

013C16

013D16

013E16

013F16

Address



014016

014116

014216

014316

014416

014516

014616

014716

014816

014916

014A16

014B16

014C16

014D16

014E16

014F16

015016

015116

015216

015316

015416

015516

015616

015716

015816

015916

015A16

015B16

015C16

015D16

015E16

015F16

016016

016116

016216

016316

016416

016516

016616

016716

016816

016916

016A16

016B16

016C16

016D16

016E16

016F16

017016

017116

017216

017316

017416

017516

017616

017716

017816

017916

017A16

017B16

017C16

017D16

017E16

017F16

CAN0 message box 10: Identifer/DLC 289



















CAN0 global mask register C0GMR 291

CAN0 local mask A register C0LMAR 291

CAN0 local mask B register C0LMBR 291


22/496

B-4


Note 1: The blank areas are reserved and cannot be accessed by users.Note 2: This register is included in the flash memory version.

018016

018116

018216

018316

018416

018516

018616

01B016

01B116

01B216

01B316

01B416

01B516

01B616

01B716

01B816

01B916

01BA16

01BB16

01BC16

020016

020116

020216

020316

020416

020516

020616

020716

020816

020916

020A16

020B16

020C16

020D16

020E16

020F16

021016

021116

021216

021316

021416

021516

021616

021716

021816

021916

021A16

021B16

021C16

021D16

021E16

021F16

021016

02FE16

02FF16


Flash memory control register 4 (Note 2) FMR4 342



CAN0 message control register 0 C0MCTL0 292










CAN0 message control register 10 C0MCTL10 292CAN0 message control register 11 C0MCTL11 292





CAN0 control register C0CTLR 293

CAN0 status register C0STR 294

CAN0 slot status register C0SSTR 295

CAN 0 interrupt control register C0ICR 296

CAN0 extended ID register C0IDR 296

CAN0 configuration register C0CONR 297

CAN0 receive error count register C0RECR 298

CAN0 transmit error count register C0TECR 298

CAN0 time stamp register C0TSR 299

024016

024116

024216

024316

024416

024516

024616

024716

024816

024916

024A16

024C16

024D16

024E16

024F16

025016

025116

025216

025316

025416

025516

025616

025716

025816

025916

025A16

025B16

025C16

025D16

025E16

025F16

02E016

02E116

02E216

02E316

02E416

02E516

02E616

02E716

02E816

02E916

02EA16

02FE16

02FF16


CAN0 acceptance f il ter support register C0AFS 299

Three-phase protect control register TPRC 139

0n-chip oscillator control register ROCR 50

Pin assignment control register PACR 177, 326

Peripheral clock select register PCLKR 52

CAN0 clock select register CCLKR 53

I2C0 data shift register S00 258

I2C0 address register S0D0 257

I2C0 control register 0 S1D0 259

I2

C0 clock control register S20 258I2C0 start/stop condition control register S2D0 263



I2C0 status register S10 260


23/496

B-5


Note : The blank areas are reserved and cannot be accessed by users.

034016

034116

034216

034316

034416

034516

034616

034716

034816

034916

034A16

034B16

034C16

034D16

034E16

034F16

035016

035116

035216

035316

035416

035516

035616

035716

035816

035916

035A16

035B16

035C16

035D16

035E16

035F16

036016

036116

036216

036316

036416

036516

036616

036716

036816

036916

036A16

036B16

036C16

036D16

036E16

036F16

037016

037116

037216

037316

037416

037516

037616

037716

037816

037916

037A16

037B16

037C16

037D16

037E16

037F16

Timer A1-1 register TA11 130



Three-phase PWM control register 0 INVC0 127

Three-phase PWM control register 1 INVC1 128

Three-phase output buffer register 0 IDB0 129

Three-phase output buffer register 1 IDB1 129

Dead time timer DTT 129

Timer B2 interrupt occurrence frequency set counter ICTB2 129

Position-data-retain function contol register PDRF 137

Port function control register PFCR 139

Interrupt request cause select register 2 IFSR2A 77

Interrupt request cause select register IFSR 77, 85

SI/O3 transmit/receive register S3TRR 218

SI/O3 control register S3C 218

SI/O3 bit rate generator S3BRG 218

SI/O4 transmit/receive register S4TRR 218

SI/O4 control register S4C 218

SI/O4 bit rate generator S4BRG 218

UART2 special mode register 4 U2SMR4 179UART2 special mode register 3 U2SMR3 179

UART2 special mode register 2 U2SMR2 178

UART2 special mode register U2SMR 178

UART2 transmit/receive mode register U2MR 175

UART2 bit rate generator U2BRG 174

UART2 transmit buffer register U2TB 174

UART2 transmit/receive control register 0 U2C0 176


UART2 receive buffer register U2RB 174


030016

030116

030216

030316

030416

030516

030616

030716

030816

030916

030A16

030B16

030C16

030D16

030E16

030F16

031016

031116

031216

031316

031416

031516

031616

031716

031816

031916

031A16

031B16

031C16

031D16

031E16

031F16

032016

032116

032216

032316

032416

032516

032616

032716

032816

032916

032A16

032B16

032C16

032D16

032E16

032F16

033016

033116

033216

033316

033416

033516

033616

033716

033816

033916

033A16

033B16

033C16

033D16

033E16

033F16


TM, WG register 0 G1TM0, G1PO0 146,147








WG control register 0 G1POCR0 146








TM control register 0 G1TMCR0 145








Base timer register G1BT 142

Base timer control register 0 G1BCR0 142

Base timer control register 1 G1BCR1 143

TM prescale register 6 G1TPR6 145TM prescale register 7 G1TPR7 145

Function enable register G1FE 148

Function select register G1FS 148

Base timer reset register G1BTRR 144

Divider register G1DV 143

Interrupt request register G1IR 149

Interrupt enable register 0 G1IE0 150

Interrupt enable register 1 G1IE1 150

NMI digital debounce register NDDR 327

P17 digital debounce register P17DDR 327


24/496

B-6

Note : The blank areas are reserved and cannot be accessed by users.

03C016

03C116

03C216

03C316

03C416

03C516

03C616

03C716

03C816

03C916

03CA16

03CB16

03CC16

03CD16

03CE16

03CF16

03D016

03D116

03D216

03D316

03D416

03D516

03D616

03D716

03D816

03D916

03DA16

03DB16

03DC16

03DD16

03DE16

03DF16

03E016

03E116

03E216

03E316

03E416

03E516

03E616

03E716

03E816

03E916

03EA16

03EB16

03EC16

03ED16

03EE16

03EF16

03F016

03F116

03F216

03F316

03F416

03F516

03F616

03F716

03F816

03F916

03FA16

03FB16

03FC16

03FD16

03FE16

03FF16

A/D register 0 AD0 226








A/D trigger control register ADTRGCON 225

A/D convert status register 0 ADSTAT0 226A/D control register 2 ADCON2 224

A/D control register 0 ADCON0 224

A/D control register 1 ADCON1 224

Port P0 register P0 324


Port P0 direction register PD0 323


Port P2 register P2 324Port P3 register P3 324













Pull-up control register 0 PUR0 325



Port control register PCR 326


038016

038116

038216

038316

038416

038516

038616

038716

038816

038916

038A16

038B16

038C16

038D16

038E16

038F16

039016

039116

039216

039316

039416

039516

039616

039716

039816

039916

039A16

039B16

039C16

039D16

039E16

039F16

03A016

03A116

03A216

03A316

03A416

03A516

03A616

03A716

03A816

03A916

03AA16

03AB16

03AC16

03AD16

03AE16

03AF16

03B016

03B116

03B216

03B316

03B416

03B516

03B616

03B716

03B816

03B916

03BA16

03BB16

03BC16

03BD16

03BE16

03BF16

Count start flag TABSR

Clock prescaler reset flag CPSRF 105,118

One-shot start flag ONSF 105Trigger select register TRGSR 105,132

Up-down flag UDF 104

Timer A0 register TA0 104





Timer B0 register TB0 118



Timer A0 mode register TA0MR 103





Timer B0 mode register TB0MR 117



Timer B2 special mode register TB2SC 131



UART0 transmit buffer register U0TB 174UART0 transmit/receive control register 0 U0C0 176





UART1 transmit buffer register U1TB 174




UART transmit/receive control register 2 UCON 176

CRC snoop address register CRCSAR 314

CRC mode register CRCMR 314

DMA0 request cause select register DM0SL 93

DMA1 request cause select register DM1SL 94

CRC data register CRCD 314

CRC input register CRCIN 314

104, 118, 132




25/496

M16C/29 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

page 1 854fo6002,11.ceD11.1.veR1110-1010B90JER

1. Overview

1.1 FeaturesThe M16C/29 Group of single-chip MCUs is built using the high-performance silicon gate CMOS process

using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded LQFP. These

single-chip MCUs operate using sophisticated instructions featuring a high level of instruction efficiency.

With 1M bytes of address space, they are capable of executing instructions at high speed. They also

contain one CAN module, makes it suitable for control of cars and LAN system of FA. In addition, they

contain a multiplier and a DMAC, also making it suitable for control of various OA, communication, and

industrial equipment which requires high-speed arithmetic/logic operations.

1.1.1 Applications

Automotive body, car audio, LAN system of FA, etc.


26/496

1. Overview

page 2

puorG92 / C61M

854fo6002,11.ceD11.1.veR1110-1010B90JER

Item Performance

CPU Number of basic instructions 91 instructions

Shortest instruction 50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V) (Normal-ver./T-ver.)

excution time 100 ns(f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V) (Normal-ver.)

50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V, -40 to 105°C) (V-ver.)

62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V, -40 to 125°C) (V-ver.)

Operation mode Single chip mode

Address space 1 Mbyte

Memory capacity ROM/RAM: See Tables 1.3 to 1.5

Peripheral Port Input/Output: 71 lines

Function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels

Three-phase Motor Control Timer

TimerS (Input Capture/Output Compare): 16 bit base timer x 1 channel (Input/Output x 8 channels )

Serial I/O 2 channels (UART, clock synchronous serial I/O)

1 channel (UART, clock synchronous serial I/O, I2C bus(1), or IEbus(2))2 channels (Clock synchronous serial I/O)

1 channel (Multi- master I2C bus(1))

A/D converter 10 bits x 27 channels

DMAC 2 channels

CRC calculation circuit 2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable

CAN module 1 channel, supporting CAN 2.0B specification

Watchdog timer 15 bits x 1 channel (with prescaler)

Interrupt 29 internal and 8 external sources, 4 software sources,

interrupt priority level: 7

Clock generation circuit 4 circuits

• Main clock• Sub-clock• On-chip oscillator(main-clock oscillation stop detect function)• PLL frequency synthesizer

Oscillation stop detect Function Main clock oscillation stop, re-oscillation detect function

Voltage detection circuit Available (Normal-ver.) / Not available (T-ver., V-ver.)

Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHz) (Normal-ver.)

Charact- VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHz)eristics VCC = 3.0 to 5.5 V (T-ver.)

VCC = 4.2 to 5.5 V (V-ver.)Power consumption 18 mA (VCC = 5 V, f(BCLK) = 20 MHz)25 µA (f(XCIN) = 32 kHz on RAM)3 µA (VCC = 5 V, f(XCIN) = 32 kHz, in wait mode)0.8 µA (VCC = 5 V, in stop mode)

Flash Program/erase supply voltage 2.7 to 5.5 V (Normal-ver.), 3.0 to 5.5V (T-ver.), 4.2 to 5.5 V (V-ver.)

memory Program and erase endurance 100 times (all space) or 1,000 times (blocks 0 to 5)/

10,000 times (blocks A and B(3))

Operating ambient temperature -20 to 85°C/-40 to 85°C(3) (Normal-ver.)-40 to 85°C (T-ver.), -40 to 125°C (V-ver.)

Package 80-pin plastic mold LQFP

Table 1.1 Performance Overview of M16C/29 Group (T-ver./V-ver.) (80-Pin Package)

1.1.2 Specifications

Table 1.1 lists performance overview of M16C/29 Group 80-pin package.

Table 1.2 lists performance overview of M16C/29 Group 64-pin package.

(These circuits contain a built-in feedback

resistor)

NOTES:

1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a trademark of NEC Electronics Corporation.

3. Refer to Table 1.6 to Table 1.11 Product code.


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1. Overview

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Table 1.2 Performance Overview of M16C/29 Group (64-Pin Package)

Item Performance

CPU Number of basic instructions 91 instructions

Shortest instruction 50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V) (Normal-ver./T-ver.)

excution time 100 ns(f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V) (Normal-ver.)

50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V, -40 to 105°C) (V-ver.)

62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V, -40 to 125°C) (V-ver.)

Operation mode Single chip mode

Address space 1 Mbytes

Memory capacity ROM/RAM: See Tables 1.3 to 1.5

Peripheral Port Input/Output: 55 lines

function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels

Three-phase Motor Control TimerTimerS (Input Capture/Output Compare):

16bit base timer x 1 channel (Input/Output x 8 channels )

Renesas M16C/29 Hardware Manual

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