Reliability of MOS Devices and Circuits · Reliability of MOS Devices and Circuits Gilson Wirth ......

Reliability of MOS Devices and Circuits

Gilson WirthUFRGS - Porto Alegre, Brazil

MOS-AK WorkshopBerkeley, CA, December 2014

2 Gilson Wirth

Variability in Nano-Scale Technologies

Electrical Behavior / Parameter Variation

Time Zero Time Dependent

Random:RDF, LER, etc

Systematic:Process

Gradients, etc

Aging:NBTI, HCI,

Electrom., etc

Transient:SET/SEU, Noise, etc

There are also environmental sources of variation:Voltage, Temperature, etc.

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Issues in Nano-Scale Technologies

Transient Error

MinimumAcceptable

Performance

AverageSpeed

Time

Perf

orm

ance

Permanent Failure

4 Gilson Wirth


Transient Error

MinimumAcceptable

Speed

Time

Spee

d

Permanent Failure

Variability

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- VDD saturating at ≈ 1V due to non-scaling of sub-threshold slope.- Increased Electric Field in Gate Dielectric and Semiconductor.- Increased power density: Increased Temperature.

6 Gilson Wirth. IEEE/ACM Workshop on Variability Modeling and Characterization

Discrete Charges and Traps

Source: Hans Reisinger


Charge Trapping

• Our Modeling Approach for Charge Trapping

• Low-Frequency Noise:• Frequency Domain Models (DC and AC Large Signal)

• Time Domain Analysis and Simulation

• NBTI: Charge Trapping Component

• Amplitude of the VT Induced by a Trap

• Conclusion


BTI x RTS

time

curr

ent

time

curr

ent

Semiconductor

Dielectric

Gate Contact

VG

Semiconductor

Dielectric

Gate Contact

VG

VG Positive: PBTIVG Negative: NBTI


Low-Frequency Noise

EF EF

Traps within a few kT from the Fermi Levelcontribute to noise


Charge Trapping Component of BTI

Transistor Off Transistor On

Traps Mostly Empty Traps Mostly Occupied

After a“Long” Time

EF

EF


BTI x RTS

Traps that contribute to noise are the ones withC E

i.e., traps that keep switching state

Traps that contribute to NBTI are the ones withC < E

i.e, traps that become occupied


Modeling ApproachBased on Microscopic (Random) Quantities,instead of distributed (homogeneous) quantities.

1. Charge trapping and de-trapping are stochastic events governed by characteristic time constants, which are uniformly distributed on a log scale.

2. Number of traps is assumed to be Poisson distributed.

3. Amplitude of the fluctuation induced by a single trap is a random variable, studied by atomistic simulations.

4. Trap energy distribution is assumed to be U shaped(key to explain the AC behavior).


Some Advantages of our Approach

1. Can be Applied to both DC and AC Large Signal Excitation.

2. Can be Applied also for Transient Simulation.

3. Random Variables Lead to Statistical Model (Today Variability is a Major Issue).

4. Can be Applied to Different Phenomena where Charge Trapping Plays a Role, such as Noise and NBTI.


Low-Frequency Noise

• Frequency Domain Modeling (DC)• Noise due to a Single Trap• Noise due to the Ensemble of Traps

• AC Large Signal Excitation

• Time Domain (Transient) Analysis and Simulation


Evaluating the Noise Power due to One Trap

• Poisson Process


Evaluating the Noise Power due to One Trap

• The autocorrelation is given by

• And the power spectrum density (Fourier Transform) is a Lorentzian

+ Singular term

It is not important


RTS: Random Telegraph Signal

f(log)

S(lo

g)

Time

Cur

rent

e

c

d


Evaluating the Noise Power due to Many Traps

10−2

10−1

100

101

102

103

104

105

106

10−7

10−6

10−5

10−4

10−3

10−2

10−1

100

101

102

f(Hz)

S(f

) S(f) = i=1

Ntr

Ai2

1 fi

1

1+f

fi

2



• Superposition of Lorentzians

• Averaging on many variability sources



• Average Value

• Standard Deviation

< S (f) > = <A2> Ndec WL

f π 2

σ S(f) < S (f) > =

2 π Ndec WL

<A4>

<A2>2

G Wirth et al. IEEE Trans Electron Dev, 2005


Average Value and Variability

Frequency [Hz]100 101 102 103 104 105G

ate

refe

rred

vol

tage

noi

se[V

Hz-1

/2]

10-8

10-7

10-6

10-5

10-4

10-3n-MOS, W / L = 25µm / 0.25µm

Vd = 1.0V, Vg,eff = 0.5V

R Brederlowiedm 1999



Frequency [Hz]100 101 102 103 104 105G

ate

refe

rred

vol

tage

noi

se[V

Hz-1

/2]

10-8

10-7

10-6

10-5

10-4

10-3n-MOS, W / L = 2.5µm / 0.25µm

Vd = 1.0V, Vg,eff = 0.5V




Frequency [Hz]100 101 102 103 104 105G

ate

refe

rred

vol

tage

noi

se[V

Hz-1

/2]

10-8

10-7

10-6

10-5

10-4

10-3n-MOS, W / L = 0.25µm / 0.25µm

Vd = 1.0V, Vg,eff = 0.5V



Variability: Dependency on Frequency


1 10 100 10000

1

2

3

4

5

6

Sf /

<S f>

Frequency [Hz]


Variability Scaling

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.00

1

2

3

4

np/<

npB

W>

(Ndec W L)-0.5

Triangles: MeasurementDots: Monte Carlo SimulationLine: Model


26 Gilson Wirth

Low-Frequency Noise





Switched Bias: Modulaton Theory

Klumperink et al., IEEE J. SOLID-STATE CIRC, VOL. 35, NO. 7, 2000

Noise Spectra for a Single Trap under Square Wave Excitation

TBktEoff

Eon

Eeq e/2

),,(

<1/c> = ( /c,on + (1-) /c,off)

<1/e>=( /e,on + (1-) /e,off)

TB

koff

Ee

TB

kon

Ee

TB

koff

Ee

TB

kon

Ee

offE

onE

/)1(

/

/)1(

/

),,(

G Wirth et al. iedm 2009

Noise Reduction under Cyclo-Operation

• Modulation theory predicts four times noise reduction for CS operation • Noise reduction is larger and in good agreement to the proposed

model.

100 101 102 103 10410-23

10-22

10-21

10-20

10-19

10-18

10-17

10-16

WL

S ID [ m

2 A2 /

Hz]

f [ Hz]

VDS = 0. 55 VL = Lnom = 0.04 mVGS,OFF = 0 VGS,ON = VT

1/f fit = 1

CONST BIAS FREQ = 10 kHz FREQ = 100 kHz FREQ = 100 kHz SIM_CONST BIAS SIM_FREQ_10kHz


Normalized Variability of Noise Behavior

Variability is seen to increase underCyclo-Stationary Operation.

10-21

10-20

10-19

10-18

10-17

10-16

WL

S ID [

A2

m 2 /H

z]

DC CYCLOCYCLOL = 1 m

CHANNEL LENGTHL = 0.04 m

DC

SAMPLE SIZE = 40CYCLO_FREQ = 1 KHz


31 Gilson Wirth

Low-Frequency Noise





RTS and Time Domain

VT Fluctuations

33

Possible Simulation Methodologies

VTVT

Change dVt at instantiation Verilog-A wrapper to

Trans. model

StaticDynamic

Change transistor Model equations

Ids = … + f(delvto(t))


RTS: Transient Simulation (1)

• Charge trapping and de-trapping are stochastic events, governed by capture and emission time constants, c and e, which are uniformly distributed on a log-scale;

• the number of traps (Ntr) is assumed to be Poisson distributed, and the average number of traps (parameter of the Poisson) is assumed to be proportional to the channel area;

• trap energy distribution, g(ET), is assumed to be U-shaped;• the amplitude of the VT fluctuation induced by a single trap,

is a random variable given by atomistic device simulations.


RTS: Transient Simulation (2)

• At each simulation time step, it is checked if a trap changes state.

• Trap switching probability is evaluated based on the device bias point at each transient simulation step.

• If one or more trap change state, transistor threshold voltage is changed accordingly.

• Simulators do not support this kind of simulation:• ngspice and BSIM4 code modified.


VT Fluctuates Over Time

+ -

VT (t)

2.0x10-7 3.0x10-7 4.0x10-7

0.04

0.06

0.08

0.10

VT Fl

uctu

atio

n (V

)

Time (s)


Transient Simulation of a Ring Oscillator


Period Jitter

• Period Jitter– Period Jitter is the difference between a clock period

and the ideal clock period (it can occur after orbefore the ideal transition).


Transient Simulation of a Ring Oscillator

6.60E-011 6.70E-011 6.80E-011 6.90E-011 7.00E-011 7.10E-0110

500

1000

1500

2000

Cou

nts

Period

Non-StationaryWith FBB

7.25E-011 7.50E-011 7.75E-011 8.00E-011 8.25E-0110

200

400

600

800

1000

1200

Cou

nts

Period

StationaryNo FBB

7.20E-011 7.40E-011 7.60E-011 7.80E-011 8.00E-0110

500

1000

1500

2000

2500

Cou

nts

Period

Non-StationaryNo FBB

Histogram of oscillation period:(a) stationary DC noise analysis,(b) and (c) non-stationary simulation methodology here proposed.Case (c) is for the oscillator under forward body biasing (FBB).Stationary noise analysis predicts a jitter (σT) of 2.2ps, non stationary analysis predicts a 1.3ps jitter. FBB decreases σT to 0.8ps.

(a) (b) (c)

40

Comments Pros

Properly implements the physical-based equations into a circuit simulator Computationally efficient (minor impact on the run time of the transient simulation) Easy to use: Transparent for the circuit designer (no change needed in the netlist). Monte Carlo “by its nature”.

Cons Changes made on simulator source code: time intensive work, and restriction to access proprietary code (HSpice, Spectre, etc.)


Outline






• Conclusion


NBTI: Charge Trapping Component

Huard et al.,IRPS 2008

Modeling Approach

time

curr

ent

VG

Semiconductor

Dielectric

Gate Contact

VG Positive: PBTIVG Negative: NBTI

Motivation

To propose a Unified Model for DC and AC Bias Temperature Instability.The model should be based on first principlesable to model both short term (cycle-to-cycle or ripple) and long term (“permanent”) components of AC BTI.Model equations should be simple and ease to implement in simulation tools.

Fast and Slow Traps

VT,Total = VT,Slow +VT,Fast

0 5000 10000 15000 20000 250000,00

0,02

0,04

0,06

0,08

V

T,To

tal (a

.u)

Time (a.u.)

VT,Fast

VT,Slow

Fast TrapsTransistor Off Transistor On

Fast Traps Mostly Empty Fast Traps Mostly Occupied

At the End ofStress Semi-Cycle

EF

EF

Relevant Trap Time Constant: τC,On

Fast TrapsTransistor OffTransistor On

Fast Traps Mostly EmptyFast Traps Mostly Occupied

At the End ofRecovery Semi-Cycle

EF

EF

Relevant Trap Time Constant: τe,Off

Slow Traps

Traps are too slow to follow bias point change.Equivalent Time Constants

<1/c>=(/c,stress+(1-)/c,recovery)

<1/e>=(/e,stress+(1-)/e,recorery)

Off

EF

On

EF

Off

EF

On

EF

On

EF

Off

EF

Fast and Slow Traps

Stress followed by Recovery.Stress of 500 time units, followed by 500 time units of Recovery.

Please note that Recovery is shifted by 500 time units in the Time axis, so that start of both Stress and Recovery correspond to time equal to zero.

100 101 102

100

Time [a.u.]

V

T [a.

u.]

StressReceovery

Slow Traps

102 1030

2

4

6

8

10

12

Time (a.u)

V T,

Slo

w (a

.u)

VT,Slow ≈ kS. [log(α+ kA)-log(1-α+ kA)].log(t)

Slow Traps

0,0 0,2 0,4 0,6 0,8 1,00,00

0,02

0,04

0,06

0,08

V

T,S

low (V

)

Duty Cycle

VT,Slow ≈ kS. [log(α+ kA)-log(1-α+ kA)].log(t)

Fast Traps

VT,Fast = [kC+kFlog(TS)] *[ (log(α+kA)+log(1-α+kA)]

Figure fromJ. Martin‐Martinez et al., IRPS 2011

Fast Traps


Figure fromD S Ang et alIEEE TDMR

pp.19, March 2011

Fast Traps

0,0 0,2 0,4 0,6 0,8 1,00,0

0,5

1,0

1,5

2,0

2,5

V

T,Fa

st (a

.u)

Duty Cycle


ΔVT Total

0 1 2 3 4 5 6x 104

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

Time (a.u.)

V T,

Tota

l (a.u

)

Monte Carlo Simulation


NBTI: Temperature Dependence

0.01 0.1 10.00

0.01

0.02(V

G-V

t0)

I D/I D

0[V

]

Stress Time [seconds]

200C / 3.07 175C / 2.75 150C / 2.42 125C / 2.02 100C / 1.67 75C / 1.49 50C / 1.23 25C / 1.00


Model for the Charge Trapping Component

G Wirth et al, IEEE TED 2011


Normalized standard deviation of the BTI induced VT shift


: Model: MC Simulation


Circuit Activity (Duty Cycle) Dependence

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Duty Cycle

V

T [a.u

.]


: Measurement: Model

: MC Simulation


Simulation of Both RTN and BTI



Source: M Agostinelli et al. (Intel), IEDM 05

Vmin on some SRAM arrays varied from one measurement to the next (90nm node).


Outline






• Conclusion


RDF: Random Dopant FluctuationsIn the past all

transistors were similar because of

self averaging

Today, Each Transistor is

Different

Slide Courtesy Prof Dragica Vasileska, ASU


Threshold Voltage Values For Different RDF Configurations

N Ashraf et al, IEEE EDL 2011

0 5 10 15 200

0.1

0.2

0.3

0.4

0.5

Random dopant configuration (integer)

Thre

shol

d vo

ltage

(V)

Vt(threshold voltage) data from EMC simulationVt(threshold voltage) data from analytical modelVt(threshold voltage) data from percolation theory model


Dependence of VT Fluctuations on Trap Position Along the Channel

N Ashraf et al, IEEE EDL 2011

0 5 10 15 20 25 30 35 400

0.005

0.01

0.015

0.02

0.025

0.03

Trap position along the interface (nm)

Thre

shol

d vo

ltage

fluc

tuat

ion

( V )

Threshold voltage deviation (analytical model 1)Threshold voltage deviation (EMC simulation(with short range e-e and e-i force))Threshold voltage deviation (EMC simulation(without short range e-e and e-i force))


Conclusion

A microscopic, statistical modeling approach for charge trapping is presented.It is applied to study the role of charge trapping and de-trapping in Noise and BTI.Mutual relation between different reliability phenomena (LF noise, BTI and RDF) is discussed.The modeling approach may be applied for time domain (transient) or frequency domain analysis.


Work here presented is due to

• People at UFRGS, Brazil: Roberto da Silva, Lucas Brusamarello, Vinicius Camargo, Mauricio Silva, Gilson Wirth, and many others …• People at ASU, USA: Dragica Vasileska, Nabil Ashraf, Yu Cao, Jyothi B Velamala, Ketul B Sutaria.• People at Texas Instruments: Ralf Brederlow and P Srinivasan (SP).• People at IMEC, Belgium: Ben Kaczer, Philippe Roussel, Guido Groeseneken, Maria Toledano-Luque, Jacopo Franco, ...• and many others …

Reliability of MOS Devices and Circuits · Reliability of MOS Devices and Circuits Gilson Wirth ......

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