Reliability and Yield of MOS Devices and Circuits · Drain voltage - effective gate voltage [V] 0.0...
Transcript of Reliability and Yield of MOS Devices and Circuits · Drain voltage - effective gate voltage [V] 0.0...
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Reliability and Yield of MOS Devices and Circuits
Prof Gilson Wirth
UFRGS - Porto Alegre, Brazil
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This set of slides is a summary of the lecture. The lecture may be tailored to the
needs and interest of the audience, and composed by a larger set of slides.
The lecture covers new phenomena which play a role on the performance and
reliability of highly scaled MOS devices. Performance and reliability become
influenced also by factors other than physical dimensions.
Furthermore, variations of parameters over time (aging and transient effects such
as noise and soft errors) may lead to dramatically increased overhead in the
timing budget, as well as on test procedures.
We need to understand the underlying physical mechanisms, and develop analysis
and modeling techniques to support IC designers.
Among the effects discussed in this lecture, the major ones are:
- Parametric variability due to effects such as random dopant fluctuations and line
edge roughness.
- Aging effects such as Bias Temperature Instability (BTI), Hot Carrier Injection
(HCI), Electromigration and Time Dependent Dielectric Breakdown (TDDB).
- Radiation Effects, such as Single Event Transients (SET) and Single Event
Upsets (SEU).
- Device intrinsic noise, with focus on the Random Telegraph Signal (RTS).
A short CV and list of publications may be found at
http://lattes.cnpq.br/1745194055679908
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Issues in Nano-Scale Technologies
Electrical Behavior / Parameter Variation
Spatial Temporal
Designer must consider both Process and Temporal Variations
Random:
RDF, LER, etc
Systematic:
Process
Gradients, etc
Aging:
NBTI, HCI,
Electrom., etc
Transient:
SET/SEU, Noise, etc
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Issues in Nano-Scale Technologies
Transient Error
MinimumAcceptable
Performance
AverageSpeed
Time
Perf
orm
an
ce
Permanent Failure
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Issues in Nano-Scale Technologies
Transient Error
MinimumAcceptable
Speed
Time
Sp
eed
Permanent Failure
Variability
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Sources & Types of VariationsSources & Types of Variations
<Lg> and <W>, <layer thicknesses>,
<R>’s, <doping>, <tox>, <Vbody>
Process
Line Edge Roughness (LER), Discrete doping,
Discrete oxide thickness, R and Vbody distributions
Environment
Operating temperature range,
VDD range
Self-heating, Hot spots,IR drops
Globalor
Cor-rela-ted
LocalOr
Ran-dom
Temporal
<NBTI> and <HCI>
Distribution of NBTI, HCI, Noise,
Radiation Eff. (SET/SEU),Oxide breakdown currents
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Sources & Types of VariationsSources & Types of Variations
<Lg> and <W>, <layer thicknesses>,
<R>’s, <doping>, <tox>, <Vbody>
Process
Line Edge Roughness (LER), Discrete doping,
Discrete oxide thickness, R and Vbody distributions
Environment
Operating temperature range,
VDD range
Self-heating, Hot spots,IR drops
Globalor
Cor-rela-ted
LocalOr
Ran-dom
Temporal
<NBTI> and <HCI>
Distribution of NBTI, HCI, Noise,
Radiation Eff. (SET/SEU),Oxide breakdown currents
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Long Range x Short Range Variations
VT
Fre
quency
VT
Fre
quency
Long Range
Variation in VT
Short Range
Variation in VT(also mismatch in
analog circuits)
Different Averages
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Different Types of Process Variation
Total Parameter Variation
Systematic Random
Layout and
Neighborhood
Dependent
Systematic
Across Chip
Intra-Die Inter-Die
Short range
Mismatch
Random
Across Chip
After Saxena et al, IEEE-TED 2008
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Systematic x RandomSystematic x Random
130 nm: Systematic 90 nm: More Random
Ring Oscillator Freq VariabilityNeuberger, Wirth el al. ESSCIRC 2006.
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Systematic VariationsSystematic Variations
Example of Layout Dependent Systematic Variations:CMP affects dense areas of lines differently than sparsely populated areas of lines.
Design Measure: Regularity and Dummies also in Digital Circuits
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250 180 130 90 65 45 nm
Defect limited
yield
Parametric limited
yield
250 180 130 90 65 45 nm
Defect limited
yield
Parametric limited
yield
hard fails, screenablesoft fails, sensitive to Temp / Vdd / f ,difficult to screen
Random VariationsRandom Variations
σσσσ / µµµµ ≈ (Area)-0.5
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Variability Increases with ScalingVariability Increases with Scaling
Current-ratio variability of 10:1 current mirror for 130-nm, 90-nm, and 65-
nm technologies [Bernstein et al., IBM J. RES. & DEV., 2006].
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Pessimistic Design Hurts PerformancePessimistic Design Hurts PerformanceP
erfo
rman
ce
Technology generation
Is This Worth a Huge
Investment?
Average Performance
Worst Case
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Optimistic Design Hurts Reliability & YieldOptimistic Design Hurts Reliability & Yield
- Parametric Yield Loss- Wear Out Before End of Expected Product Life Time
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Random Process VariationsRandom Process Variations
RDF: Random Dopant FluctuationsLER: Line Edge Roughness
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RDF: Random RDF: Random DopantDopant FluctuationsFluctuations
The simulationParadigm now A 22 nm MOSFET
In production 2009
A 4.2 nm MOSFETIn production 2023A Asenov et al., IEEE-TED 2003
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LER: Line Edge RoughnessLER: Line Edge Roughness
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Parameters become Random Variables Parameters become Random Variables
[Source: S. Y. Borkar, Intel, 2004]
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Power Power xx TimingTiming
[Source: S. Y. Borkar, Intel, 2004]
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Too
leaky
Too
slow
Pro
bab
ilit
y
Vt
Good
chips
Power Power xx TimingTiming
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AgingAging
NBTI: Negative Bias Temperature InstabilityShifting of PMOS Vt over time, reducing On Current
HCI: Hot Carrier InjectionShifting on NMOS Vt over time, reducing On Current
ElectromigrationIncrease of Interconnect Resistance (or Rupture)
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HCI: Hot Carrier StressHCI: Hot Carrier Stress
Noise relevance of traps
Hot carrier stress generates additional trap states near to the drain:
- Locally shifts Vt at the drain side.
- Is also a source of noise.
Source: R Brederlow, PhD Thesis
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HCI: Hot Carrier StressHCI: Hot Carrier Stress
Drain voltage - effective gate voltage [V]
0.0 0.5 1.0 1.5
Ch
an
ge
s in
ga
te r
efe
rre
dvo
lta
ge
no
ise
[%
]
101
102
103
Ch
an
ge
s in
dra
in c
urre
nt [%
]100
101
102
Stress @ Vg=1.2V, Vd=5.5V
n-MOS W / L = 15µm / 0.75µmCharacterization @ Vg= 1.2V
105 s
3x104 s
HCI in NMOS: Reduced On Current and Increased Noise.
Source: R Brederlow, PhD Thesis
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NBTI: Negative Bias Temp InstabilityNBTI: Negative Bias Temp Instability
-Vt increases over time- Ids reduces affecting PMOS Speed.
Source: K Kang et al., IEEE ICCD 2006
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Design Centering Over Product LifetimeDesign Centering Over Product Lifetime
NBTI-Aware Technique for Transistor Sizing of High-Performance CMOS Gates.M da Silva, V Camargo, L Brusamarello, G Wirth and R da Silva. LATW 2009
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HCI and NBTIHCI and NBTI
• Note that these effects are also history dependent, varying according to total time spent in the 'on' or 'off' state.
• Associated with the average threshold shift, there are also random shifts.
• Even for identical use conditions and devices, there are mismatch shifts due to random variations in the number and spatial distribution of the charges/interface states formed.
• Small gate area devices will experience more random mismatch.
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ElectromigrationElectromigration
• Particularly likely to affect the thin tightly spaced interconnect lines of deep-submicrometer design.
• Difficult to be prevented by product testing.• Main cause: generation of stress in the grain boundaries and
interfaces.
Common Failure Modes:Grain Boundaries andInterfaces.
M. A. Meyer and E. Zschech,
Proc. 9th Int. Workshop
Stress Induced Phenom.
Metallization, 2007.
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Transient FaultsTransient Faults
Radiation Effects:SET: Single Event TransientSEU: Single Event Upset
RTS: Random Telegraph Signal
Signal Integrity Issues (e.g., Noise Coupling, Substrate Noise Coupling, etc).
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Radiation EffectsRadiation Effects
Please clic on Fig to run movie
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Radiation EffectsRadiation Effects
OUT (Vdd)
PMOS
NMOS
VDD
IN (GND)
CNODE
IP
IC
ID
10
OUT (Vdd)
PMOS
NMOS
VDD
IN (GND)
CNODE
IP
IC
ID
10
Charge Collection Mechanism
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SET in Combinational LogicSET in Combinational Logic
1
1
1
0
1
1
0
0
0
1 0
1 0
1 0
1 00 10 1
1
Particle
strike
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SEU in Sequential LogicSEU in Sequential Logic
1 0OF
F
OF
F
PN N
gnd
OF
F
OF
F
0 1
BIT-FLIP
ionization
P
WL WL
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Sequence of Events from Ionization to FailureSequence of Events from Ionization to Failure
+
-+-
-+-
+
+-
+-
ionization Transient current (injected or extracted from
the junction)
Transient voltage pulse(capacitor node) clk
BIT-FLIP ERROR
FAULT FAULT EFFECT
FAILURE
Sensors(detection)
Time redundancy(detection, mitigation)
Hardware redundancy
Error correcting codes(detection and mitigation)
Fault tolerant techniques
Self-checking mechanisms with recovery
Recomputation(detection and mitigation)
Redundancy
/ Spare components
Error latencyFault latency
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BulkBulk--BICSBICS
gnd
+ +- --
α particles
protons,
heavy ions
ionization
Bulk-
BICS
Bulk-
BICS
VDD
+
Wirth et al., IEEE Micro, 2007
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RTS: Random Telegraph SignalRTS: Random Telegraph Signal
Inversion layer
Trap
Gate Oxide
Interaction with the inversion layerDrain Current ID
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RTS: Random Telegraph SignalRTS: Random Telegraph Signal
Leads to modulation of the local mobility and number of free carriers in the channel
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Variability: Dependency on Circuit BandwidthVariability: Dependency on Circuit Bandwidth
1 10 100 1000 100002,5
3,0
3,5
4,0
4,5
5,0
5,5
6,0
σnp/<
np
BW
>
fH/f
L
G Wirth et al. IEEE Trans Electron Dev, 2007
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RTS: Random Telegraph SignalRTS: Random Telegraph Signal
f(log)
S(lo
g)
Time
Cu
rre
nt
τe
τc
δΙd
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RTS and RTS and DigitalDigital CircuitsCircuits
VT Fluctuations
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RTS and RTS and DigitalDigital CircuitsCircuits
VT Fluctuations
+ -
∆∆∆∆VT
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RTS in SRAMRTS in SRAM
RTS causes instability issues on SRAM memoriesRTS impact on cell characteristics: far from Normality
Accurate Model for RTS noise in digital circuits: Statistical RTS model for digital circuits. L Brusamarello, G Wirth and R da Silva. Microelectronics Reliability, 2009.
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RTS: Erratic Fluctuations of SRAM Cache RTS: Erratic Fluctuations of SRAM Cache
VminVmin at the 90nm Process Technology Nodat the 90nm Process Technology Nodee
Source: M Agostinelli et al. (Intel), IEDM 05
Vmin on some SRAM arrays varied from one measurement to the next.
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RTS in CMOS Image Sensor PixelsRTS in CMOS Image Sensor Pixels
Source: X Wang, P R Rao, A Mierop, A Theuwissen. IEDM 06.
Temporal output behavior of pixels
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RTS Flash MemoriesRTS Flash Memories
FANTINI et al. IEEE-EDL December 07
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Signal Integrity IssuesSignal Integrity Issues
Crosstalk Noise:Due to electromagnetic coupling between Signal Lines.
Power/Ground Noise:Due to Simultaneous Switching of Many Gates.
Substrate Noise:Signal can couple from one node to another via thesubstrate.
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Could Variability & Could Variability & ReliabReliab. . CostCost BecomeBecomeShow Stopper ?Show Stopper ?
Technology Node
Co
st
Cost per Transistor
Reliability Cost
TotalProduct Cost
ScalingNot Profitable
High-cost reliability solutions (increased design cost, increased silicon area, etc) and service may lead to unacceptable costs.
Based on T Austin et al., IEEE D&T of Comp., 2008.
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Technology Node
Co
st
Cost per Transistor
Reliability Cost
TotalProduct Cost
Need for New Low-Cost, Resilient Design Methodologies
Based on T Austin et al., IEEE D&T of Comp., 2008.
Could Variability & Could Variability & ReliabReliab. . CostCost BecomeBecomeShow Stopper ?Show Stopper ?
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HW & SW Techniques for Enhancing HW & SW Techniques for Enhancing ReliabReliab..
SW
HW
Application
Operating Sys
BIOS
Intercon. & I/O
Memory
Logic
Check-point and Roll Back,
Application Replication & SW
Voting, Robust Data Structures,
Memory Management, etc.
Space, Time and Information
Redundancy & HW Voting.
Sense & Correct.
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Issues for TestIssues for Test
- Traditional Go-Don’t Go Test (usually intended toscreen hard failures, not Adequate
- Burn-In and Iddq Test Challenged by Leakage Currents- Complex Aging Mechanisms
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ConclusionConclusion
• Process parameter variations and variations of parameters over time (both aging and transient) are very important in Nano-scale technologies• Tools for automated estimation of yield and reliability are mandatory• New design methodologies to assure yield and reliability are required• New test methodologies to coupe with parametric and transient failures needed• It is needed to simultaneously address power, speed and reliability constraints• Proper process eng., modeling, simulation and design can lead to high yield and reliability.
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