Reference Design for SARA / LISA modules...

Nested Design Reference Design for SARA / LISA modules Application Note

Abstract

This document describes the nested design for SARA and LISA

modules. This reference design is intended to be used as a template to assist in making application-specific products. Reference designs,

including example schematics, Bill of Materials (BOM), and routing

suggestions, are available to u-blox’ customers.

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Nested Design - Application Note

GSM.G2-CS-12001-1 of 26

Document Information

Title Nested Design

Subtitle Reference Design for SARA / LISA modules

Document type Application Note

Document number GSM.G2-CS-12001-1

Document status Preliminary

This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They can be downloaded from www.u-blox.com.

u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make

changes to specifications and product descriptions at any time without notice.

u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without

express permission is strictly prohibited. Copyright © 2013, u-blox AG.



GSM.G2-CS-12001-1 Preliminary of 26

Contents

Contents .............................................................................................................................. 3

1 Introduction .................................................................................................................. 4

2 Nested design description ........................................................................................... 5

2.1 Overview .............................................................................................................................................. 5

2.2 Power management ........................................................................................................................... 11

2.2.1 Module supply (VCC) .................................................................................................................. 11

2.2.2 RTC supply (V_BCKP) ................................................................................................................... 12

2.2.3 Interfaces supply output (V_INT) .................................................................................................. 12

2.3 System functions ................................................................................................................................ 12

2.3.1 Module power-on (PWR_ON) ...................................................................................................... 12

2.3.2 Module power-off ....................................................................................................................... 12

2.3.3 Module reset (RESET_N) .............................................................................................................. 13

2.3.4 External 32 kHz input (EXT32K) ................................................................................................... 13

2.4 RF connection ..................................................................................................................................... 14

2.4.1 RF interface for Tx/Rx antenna (ANT) ........................................................................................... 14

2.4.2 RF interface for Rx diversity antenna (ANT_DIV) ........................................................................... 14

2.4.3 Antenna detection interface (ANT_DET) ...................................................................................... 15

2.5 SIM interface ...................................................................................................................................... 17

2.6 Serial interfaces .................................................................................................................................. 17

2.6.1 UART interface ............................................................................................................................ 17

2.6.2 UART AUX interface .................................................................................................................... 17

2.6.3 USB interface............................................................................................................................... 17

2.6.4 SPI interface ................................................................................................................................ 18

2.6.5 DDC (I2C) interface ...................................................................................................................... 18

2.7 Audio interface ................................................................................................................................... 19

2.7.1 Analog Audio .............................................................................................................................. 19

2.7.2 Digital audio ................................................................................................................................ 21

2.8 General Purpose Input/Output (GPIO) ................................................................................................. 22

2.8.1 GPIOs with GPS / GNSS functionalities ......................................................................................... 23

2.9 Reserved pins (RSVD) .......................................................................................................................... 23

2.10 Production guidelines ...................................................................................................................... 23

2.11 Deliverable package ........................................................................................................................ 24

Related documents........................................................................................................... 25

Revision history ................................................................................................................ 25

Contact .............................................................................................................................. 26



1 Introduction The following symbols are used to highlight important information within the document:

An index finger points out key information pertaining to module integration and performance.

A warning symbol indicates actions that could negatively impact or damage the module.

This document applies to the following products:

o SARA-G3 series

o LISA-U1 series

o LISA-U2 series

o LISA-C2 series

u-blox uses the term “Nested Design” to describe application boards on which different series of modules can

be mounted on the same space.

In this document LISA-U1 series, LISA-U2 series and LISA-C2 series modules will be referred to as LISA and

references applicable to SARA-G3 series modules will be referred to as SARA.

The Nested Design Application Note focuses at the following topics:

All SARA and LISA modules interfaces

This document includes only HW guidelines for mounting LISA and SARA modules on the same spaces of the

nested application board. Firmware topics are not considered, but SARA and LISA modules enjoy fairly

straightforward compatibility for AT commands (for more details refer to the corresponding module AT commands manual [2], [8]).



2 Nested design description

2.1 Overview

Migrating between LISA-U1, LISA-U2, LISA-C2 series and SARA-G3 series wireless module designs is a fairly

straightforward procedure that allows customers to take maximum advantage of their hardware and software

investments.

SARA wireless modules (26.0 x 16.0 mm LGA) have a different form factor than LISA wireless modules (33.2 x

22.4 mm LCC). Even so the footprints for the SARA and LISA modules have been developed so that all the pads

on the side with the antenna pin can be shared on the application board. The pins on this side have the same pitch and nearly the same functions, as described in Figure 1.

64 63 61 60 58 57 55 54

22 23 25 26 28 29 31 32

11

10

8

7

5

4

2

1

21

19

18

16

15

13

12

43

44

46

47

49

50

52

53

33

35

36

38

39

41

42

65 66 67 68 69 70

71 72 73 74 75 76

77 78

79 80

81 82

83 84

85 86 87 88 89 90

91 92 93 94 95 96

CTS

RTS

DCD

RI

V_INT

V_BCKP

GND

RSVD

RESET_N

RSVD/ GPIO1

PWR_ON

RXD

TXD

3

20

17

14

9

6

24 27 30

51

48

45

40

37

34

5962 56

GND

GND

DSR

DTR

GND

RSVD

GND

GND

RX

D_A

UX

TX

D_A

UX

EX

T3

2/R

SV

D

GN

D

RS

VD

/G

PIO

2

RS

VD

/G

PIO

3

RS

VD

/S

DA

RS

VD

/S

CL

RS

VD

/G

PIO

4

GN

D

GN

D

GND

RSVD/ SPK_P

RSVD/ MIC_BIAS

RSVD/ MIC_GND

RSVD/ MIC_P

GND

VCC

VCC

RSVD

RSVD/ I2S_TXD

RSVD/ I2S_CLK

SIM_CLK

SIM_IO

VSIM

SIM_DET

VCC

RSVD/ MIC_N

RSVD/ SPK_N

SIM_RST

RSVD/ I2S_RXD

RSVD/ I2S_WA

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

RS

VD

/A

NT

_D

ET

AN

T

SARA-G3 seriesTop View

Pin 65-96: GND

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

GND

VCC

VCC

VCC

GND

SPI_MRDY

SPI_SRDY

SPI_MISO

SPI_MOSI

SPI_SCLK

RSVD / SPK_N

GND

RSVD / SPK_P

RSVD

GPIO5

VSIM

SIM_RST

SIM_IO

SIM_CLK

SDA

SCL

RSVD / I2S_RXD

RSVD / I2S_CLK

RSVD / I2S_TXD

RSVD / I2S_WA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V_BCKP

GND

V_INT

RSVD

GND

GND

GND

DSR

RI

DCD

DTR

GND

RTS

CTS

TXD

RXD

GND

VUSB_DET

PWR_ON

GPIO1

GPIO2

RESET_N

GPIO3

GPIO4

GND26

27

USB_D-

USB_D+

40

39

RSVD / MIC_P

RSVD / MIC_N

28 29 30 31 32 33 34 35 36 37 38

76 75 74 73 72 71 70 69 68 67 66

LISA-U1 seriesTop View

GN

D

RS

VD

GN

D

GN

D

GN

D

GN

D

GN

D

AN

T

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

GND

VCC

VCC

VCC

GND

SPI_MRDY / GPIO14

SPI_SRDY / GPIO13

SPI_MISO / GPIO12

SPI_MOSI / GPIO11

SPI_SCLK / GPIO10

GPIO9 / I2S1_WA

GND

GPIO8 / I2S1_CLK

RSVD / CODEC_CLK

GPIO5

VSIM

SIM_RST

SIM_IO

SIM_CLK

SDA

SCL

RSVD / I2S_RXD

RSVD / I2S_CLK

RSVD / I2S_TXD

RSVD / I2S_WA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V_BCKP

GND

V_INT

RSVD

GND

GND

GND

DSR

RI

DCD

DTR

GND

RTS

CTS

TXD

RXD

GND

VUSB_DET

PWR_ON

GPIO1

GPIO2

RESET_N

GPIO3

GPIO4

GND26

27

USB_D-

USB_D+

40

39

GPIO7 / I2S1_TXD

GPIO6 / I2S1_RXD

28 29 30 31 32 33 34 35 36 37 38

76 75 74 73 72 71 70 69 68 67 66

LISA-U2 seriesTop View

GN

D

RS

VD

/A

NT

_D

IV

GN

D

GN

D

GN

D

GN

D

GN

D

AN

T

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

GND

VCC

VCC

VCC

GND

RSVD

RSVD

RSVD

RSVD

RSVD

SPK_N

GND

SPK_P

RSVD

GPIO5

VSIM

SIM_RST

SIM_IO

SIM_CLK

RSVD

RSVD

PCM_DI

PCM_CLK

PCM_DO

PCM_SYNC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RSVD

GND

V_INT

RSVD

GND

GND

GND

RSVD

RI

RSVD

RSVD

GND

RTS

CTS

TXD

RXD

GND

VUSB_DET

PWR_ON

GPIO1

GPIO2

RESET_N

GPIO3

GPIO4

GND26

27

USB_D-

USB_D+

40

39

MIC_P

MIC_N

28 29 30 31 32 33 34 35 36 37 38

76 75 74 73 72 71 70 69 68 67 66

LISA-C2 seriesTop View

GN

D

RS

VD

GN

D

GN

D

GN

D

GN

D

GN

D

AN

T

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

Figure 1: Pin assignment on LISA series and SARA-G3 series modules: highlighted pads can be shared on the application board

This is the basis of the Nested Design concept: any SARA-G3, any LISA-U1, any LISA-U2, any LISA-C2 module

can be alternatively mounted on the same nested board, as shown in Figure 2. This enables straightforward

development of products supporting either GSM/GPRS, W-CDMA or CDMA wireless technology with the same application board.

LISA

NESTED APPLICATION BOARD

Top Layer and Solder MaskLISA mounting option

with LISA Paste Mask

SARA

SARA mounting option

with SARA Paste Mask

ANT pad

Figure 2: Nested Design concept description: LISA and SARA modules alternatively mounted on the same application board



The voltage level of all the digital interfaces of SARA and LISA series modules is 1.8 V: this allows the direct connection from a 1.8 V external device (e.g. application processor) to all the modules.

The following chapters explain the points to consider when nesting LISA and SARA modules.

For further details regarding SARA and LISA series modules characteristics, usage, or settings, refer to the relevant Data Sheet [1], [3], [4], [5], System Integration Manual [6], [7], [9] and AT commands manual [2], [8].

Table 1 summarizes the electrical differences of pins on LISA and SARA wireless modules.

Pin Name N° SARA-G3 series N° LISA-C2 series LISA-U1 series LISA-U2 series

Power

VCC 51-53 Normal op. range:

3.35 V – 4.5 V

Extended op. range:

3.00 V – 4.5 V

High pulse current

due to GSM TDMA

61-63 Normal op. range:

3.3 V – 4.4 V

Extended op. range:

Not applicable

No high pulse current

due to CDMA

Normal op. range:

3.4 V – 4.2 V

Extended op. range:

3.1 V – 4.2 V

High pulse current

due to GSM TDMA

Normal op. range:

3.3 V – 4.4 V

Extended op. range:

3.1 V – 4.5 V

High pulse current

due to GSM TDMA

V_BCKP 2 Output characteristics:

2.3 V typ, 2 mA max

Input op. range:

1.0 V – 2.4 V

2 Not Available Output characteristics:

2.3 V typ, 3 mA max

Input op. range:

1.0 V – 2.5 V

Output characteristics:

1.8 V typ, 3 mA max

Input op. range:

1.0 V – 1.9 V

V_INT 4 Output characteristics:

1.8 V typ, 50 mA max

4 Output characteristics:






Antenna

ANT 56 RF input/output for Tx/Rx antenna

68 RF input/output for Tx/Rx antenna

RF input/output for Tx/Rx antenna

RF input/output for main Tx/Rx antenna

ANT_DIV Not Available 74 Not Available Not Available LISA-U230 only:

RF input for

Rx diversity antenna

ANT_DET 62 SARA-G350 only:

Input for antenna

detection circuit

Not Available Internal antenna detection circuit

Internal antenna detection circuit

System

PWR_ON 15 No internal pull-up

L-level: -0.10 V – 0.65 V

H-level: 2.00 V – 4.50 V

ON L-level time:

5 ms min

OFF L-level pulse time:

Not Available

19 180 k internal pull-up

L-level: -0.30 V – 0.30 V

H-level: 2.00 V – 4.70 V

ON L-level pulse time:

150 ms min


Not Available

No internal pull-up

L-level: -0.30 V –0.65 V

H-level: 2.00 V – 4.50 V


5 ms min


Not Available

No internal pull-up

L-level: -0.30 V – 0.65 V

H-level: 1.50 V – 4.40 V


50 µs min / 80 µs max


Not Available

RESET_N 18 Internal diode & pull-up

L-level: -0.30 V – 0.30 V

H-level: 2.00 V – 4.70 V

Reset L-level pulse time:

50 ms min

22 550 internal pull-up

L-level: -0.30 V – 0.63 V

H-level: 1.32 V – 2.10 V


300 ms min

10 k internal pull-up

L-level: -0.30 V – 0.65 V

H-level: 1.69 V – 2.48 V


50 ms min

10 k internal pull-up

L-level: -0.30 V – 0.51 V

H-level: 1.32 V – 2.01 V


50 ms min

EXT32K 31 SARA-G300/G310:

32 kHz input for RTC

& low power idle mode

SARA-G350:

Internal 32 kHz for RTC

& low power idle mode

Not Available Internal 32 kHz for RTC & low power idle mode

Internal 32 kHz for RTC & low power idle mode

SIM

SIM_CLK 38 1.8V / 3V SIM clock 47 1.8V / 3V SIM clock (upcoming FW releases)

1.8V / 3V SIM clock 1.8V / 3V SIM clock

SIM_IO 39 1.8V / 3V SIM data

Internal 4.7k pull-up

48 1.8V / 3V SIM data (upcoming FW releases)

Internal 10k pull-up

1.8V / 3V SIM data


1.8V / 3V SIM data


SIM_RST 40 1.8V / 3V SIM reset 49 1.8V / 3V SIM reset (upcoming FW releases)

1.8V / 3V SIM reset 1.8V / 3V SIM reset




VSIM 41 1.8V / 3V SIM supply 50 1.8V / 3V SIM supply (upcoming FW releases)

1.8V / 3V SIM supply 1.8V / 3V SIM supply

SIM_DET 42 1.8 V, SIM detect input

Inner pull-down: 103 µA

Not Available Provided by GPIO5:

1.8 V, SIM detect input


Provided by GPIO5:

1.8 V, SIM detect input


UART

DSR 6 1.8 V, DSR output

Driver strength: 6 mA

9 Not Available 1.8 V, DSR output


1.8 V, DSR output


RI 7 1.8 V, RI output


10 1.8 V, RI output


1.8 V, RI output


1.8 V, RI output


DCD 8 1.8 V, DCD output


11 Not Available 1.8 V, DCD output


1.8 V, DCD output


DTR 9 1.8 V, DTR input

Internal pull-up: -55 µA

12 Not Available 1.8 V, DTR input


1.8 V, DTR input


RTS 10 1.8 V, Flow ctrl input


13 1.8 V, Flow ctrl input


1.8 V, Flow ctrl input




CTS 11 1.8 V, Flow ctrl output


14 1.8 V, Flow ctrl output


1.8 V, Flow ctrl output




TXD 12 1.8 V, Data input


15 1.8 V, Data input


1.8 V, Data input


1.8 V, Data input


RXD 13 1.8 V, Data output


16 1.8 V, Data output


1.8 V, Data output


1.8 V, Data output


UART AUX

TXD_AUX 29 1.8 V, Data input


Not Available Not Available Not Available

RXD_AUX 28 1.8 V, Data output



USB

VUSB_DET Not Available 18 5 V, Supply detection 5 V, Supply detection 5 V, Supply detection

USB_D- Not Available 26 Full-Speed USB 2.0 High-Speed USB 2.0 High-Speed USB 2.0

USB_D+ Not Available 27 Full-Speed USB 2.0 High-Speed USB 2.0 High-Speed USB 2.0

SPI

SPI_SCLK Not Available 55 Not Available 1.8 V, Clock input


1.8 V, Clock input


SPI_MOSI Not Available 56 Not Available 1.8 V, Data input


1.8 V, Data input


SPI_MISO Not Available 57 Not Available 1.8 V, Data output

Driver strength: 2.5 mA

1.8 V, Data output


SPI_SRDY Not Available 58 Not Available 1.8 V, Flow ctrl output




SPI_MRDY Not Available 59 Not Available 1.8 V, Flow ctrl input




DDC (I2C)

SCL 27 SARA-G350 only:

1.8 V, open drain


45 1.8 V, open drain (upcoming FW releases)

1.8 V, open drain


1.8 V, open drain


LISA-U200-00S: N.A.

SDA 26 SARA-G350 only:

1.8 V, open drain


46 1.8 V, open drain (upcoming FW releases)

1.8 V, open drain


1.8 V, open drain


LISA-U200-00S: N.A.

Audio

Analog audio

MIC_BIAS 46 SARA-G350 only:

2.2 V supply output for external microphone





MIC_GND 47 SARA-G350 only:

Local ground sense for

external microphone


MIC_P 49 SARA-G350 only:

Differential input (+)

No internal capacitor

for DC blocking

40 Differential input (+)

100 nF internal capacitor

for DC blocking

LISA-U120/U130 only:

Differential input (+)


for DC blocking

Not Available

MIC_N 48 SARA-G350 only:

Differential input (-)

No internal capacitor

for DC blocking

39 Differential input (-)


for DC blocking


Differential input (-)


for DC blocking

Not Available

SPK_P 44 SARA-G350 only:

Differential output (+)

16 Ω load capable

53 Differential output (+)

32 Ω load capable


Differential output (+)

16 Ω load capable

Not Available

SPK_N 45 SARA-G350 only:

Differential output (-)

16 Ω load capable

54 Differential output (-)

32 Ω load capable


Differential output (-)

16 Ω load capable

Not Available

Digital audio

I2S_TXD 35 SARA-G350 only:

1.8 V, Data Out

PCM / Normal I2S mode


42 PCM_DO:

1.8 V, PCM Data Out


1.8 V, Data Out



1.8 V, Data Out



LISA-U200-00S: N.A.

I2S_RXD 37 SARA-G350 only:

1.8 V, Data In



44 PCM_DI:

1.8 V, PCM Data In


1.8 V, Data In



1.8 V, Data In



LISA-U200-00S: N.A.

I2S_WA 34 SARA-G350 only:

1.8 V, Word align. Out

Fixed frequency


41 PCM_SYNC:

1.8 V, PCM Sync Out


1.8 V, Word align. In/Out

Configurable frequency



1.8 V, Word align. In/Out




LISA-U200-00S: N.A.

I2S_CLK 36 SARA-G350 only:

1.8 V, Clock Out

Fixed frequency


43 PCM_CLK:

1.8 V, PCM Clock Out


1.8 V, Clock In/Out




1.8 V, Clock In/Out




LISA-U200-00S: N.A.

I2S1_WA Not Available 54 Not Available Not Available 1.8 V, Data Out



LISA-U200-00S: N.A.

I2S1_TXD Not Available 40 Not Available Not Available 1.8 V, Data In



LISA-U200-00S: N.A.

I2S1_CLK Not Available 53 Not Available Not Available 1.8 V, Word align. In/Out




LISA-U200-00S: N.A.

I2S1_RXD Not Available 39 Not Available Not Available 1.8 V, Clock In/Out




LISA-U200-00S: N.A.

Other

CODEC_CLK Not Available 52 Not Available Not Available 1.8 V, 13/26 MHz Out


LISA-U200-00S: N.A.




GPIO

GPIO1 16 SARA-G350 only:

1.8 V, configurable GPIO

Default: Pad disabled



20 1.8 V, configurable GPIO














Default: GPS supply ena.








Default: GPS supply en.




Default: GPS supply en.





Default: GPS data ready

















Default: GPS RTC shar.








Default: GPS RTC sharing (4.7 k external pull-down

required for RTC sharing)




Default: GPS RTC sharing



GPIO5 Not Available 51 1.8 V, configurable GPIO





Default: SIM detection




Default: SIM detection



GPIO6 Not Available 39 Not Available Not Available 1.8 V, configurable GPIO

Default: I2S1_RXD




Default: I2S1_TXD




Default: I2S1_CLK




Default: I2S1_WA




Default: SPI_SCLK




Default: SPI_MOSI




Default: SPI_MISO




Default: SPI_SRDY







Default: SPI_MRDY



Table 1: Summary of pin differences and compatibility level among modules

The printed circuit board for the Nested Design application board is IP06_HW_CS_170000 (shown on the bottom side of the board). Table 2 lists the different Bills of Materials (BoM) available as mounting options on

this PCB1.

Mounting option Description Remarks

IP06_HW_BM_170000_BOM_COUNT.xls SARA-G350 mounting version Just one schematic file HS_170000 is provided with the necessary comments.

IP06_HW_BM_1700A0_BOM_COUNT.xls SARA-G310 mounting version All BOM versions refer to schematic HS_170000

IP06_HW_BM_1700B0_BOM_COUNT.xls LISA-U200 mounting version All BOM versions refer to schematic HS_170000

IP06_HW_BM_1700C0_BOM_COUNT.xls LISA-U230 mounting version All BOM versions refer to schematic HS_170000

IP06_HW_BM_1700D0_BOM_COUNT.xls LISA-C200 and LISA-U1x0 mounting version All BOM versions refer to schematic HS_170000

Table 2: Nested Design mounting options description

1 The Nested Design Reference Design can be mounted on the EVB-WL1 evaluation board for wireless modules:

In general peripheral voltages on the EVB-WL1 board can be set to 1.8 V or 2.85 V. The SARA/LISA Nested Design, HR_1700x0 sets this voltage to 1.8 V by tying to GND pin 41 of J401 in the schematic IP06_HW_HS_170000.pdf.



2.2 Power management

2.2.1 Module supply (VCC)

The same compatible external circuit can be implemented for SARA-G3 and LISA series even if there are minor differences in the VCC input voltage ranges and some differences in the current consumption figures.

The voltage provided must be within the normal operating range limits to allow module switch-on and must be

above the minimum limit of the extended operating range to avoid module switch-off. For the detailed VCC input voltage ranges values refer to Table 1 or to the Data Sheet relating to the module [1], [3], [4], [5].

The maximum average current consumption of SARA-G3 is lower than that of the LISA due to the lower data

rate or the different channel access technology. SARA-G3 modules require large current pulses in connected-mode, significantly lower than LISA-U series when a 2G call is enabled. LISA-C2 series do not require large

current pulses, due to the CDMA channel access technology. For the detailed current consumption values, refer

to the Data Sheet relating to the module [1], [3], [4], [5].

The System Integration Manual corresponding to the module [6], [7], [9] describes the detailed supply circuit

design-in guidelines.

VCC pads of SARA and LISA modules are not shared on the top layer of the nested application board, but they are positioned very close each other to facilitate routing as shown in the Nested Design top layer description

reported in Figure 6 and in Figure 5.

A bypass capacitor with Self-Resonant Frequency in the 800/900 MHz range is placed very close to the VCC pins, at the narrowing of the VCC line implemented in the design, to filter EMI in the lower bands. Additional bypass

capacitors are placed close to the VCC pins to filter EMI in higher bands and to filter the digital logic noise from

clocks and data sources, as suggested in the System Integration Manual relating to the module [6], [7], [9].

If the application device integrates an internal antenna (which is not provided on the nested design board), it is

highly recommended to implement the VCC circuit described in Figure 3 and Table 3, in particular when the

LISA-U modules are mounted, to improve the RF performance. This implementation provides a series ferrite bead for GHz band noise as close as possible to the VCC pins of the module and bypass capacitors, with SRF in the

800/900 MHz and 1800/1900 MHz ranges where the VCC line narrows close to the module.

C1

GND

C2 C4

LISA-U series

62VCC

63VCC

61VCC

3V8

C5

+

LISA-U series

C5

GND plane

VCC line

Capacitor with SRF ~900 MHz

FB1

C1 C3 C4

FB1

Ferrite Bead for GHz noise

C2

C3

Capacitor with SRF ~1900 MHz

Figure 3: Suggested schematic and layout design for the VCC line; highly recommended when using an integrated antenna

Reference Description Part Number - Manufacturer

C1 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata

C2 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata

C3 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata

C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata

C5 330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET

FB1 Chip Ferrite Bead EMI Filter for GHz Band Noise

220 at 100 MHz, 260 at 1 GHz, 2000 mA

BLM18EG221SN1 - Murata

Table 3: Suggested components for VCC circuit close to module pins; highly recommended when using an integrated antenna



2.2.2 RTC supply (V_BCKP)

The same compatible external circuit can be implemented for SARA-G3 and LISA-U series even if there are minor

differences in the V_BCKP typical output voltage and input voltage range, as shown in Table 1 or in the Data

Sheet relating to the module [1], [3], [4], [5].

LISA-C2 series do not provide V_BCKP RTC supply input/output as well as the whole RTC functionality.

V_BCKP pads of SARA and LISA modules are not shared on the top layer of the nested application board, but

they are positioned very close each other to facilitate routing.

2.2.3 Interfaces supply output (V_INT)

The same compatible external circuit can be implemented for SARA-G3 series and LISA series; there are no

differences in the V_INT output characteristics.

V_INT pads of SARA and LISA modules are not shared on the top layer of the nested application board, but they are positioned very close each other to facilitate routing.

2.3 System functions

2.3.1 Module power-on (PWR_ON)

Table 4 summarizes the allowed power-on sequences of SARA-G3 series and LISA series. For more details, refer

to the System Integration Manual relating to the module [6], [7], [9].

SARA-G3 series LISA-C2 series LISA-U1 series LISA-U2 series

Rising edge on the VCC pins to a valid voltage as module supply

Rising edge on the VCC pins to a valid voltage as module supply with PWR_ON pin permanently low when VCC is applied



Low level on the PWR_ON pin for appropriate time period

Low pulse on the PWR_ON pin for appropriate time period



Pre-programmed RTC alarm (32 kHz signal at EXT32K input needed for SARA-G300 /

SARA-G310)

Pre-programmed RTC alarm Pre-programmed RTC alarm

RESET_N input pin released from the low level

RESET_N input pin released from the low level

Table 4: Summary of power on events among modules

The same compatible external power-on circuit can be implemented for SARA-G3 series and LISA series even if there are minor differences in the PWR_ON input voltage levels ranges and in the low level time or low pulse

time to switch-on the module, as reported in Table 1 or in the Data Sheet relating to the module [1], [3], [4], [5].

PWR_ON falling edge (i.e. low pulse) is required for LISA series, but it is not required for SARA-G3 series.

External pull-up is not needed for LISA-C2 series since internal pull-up is provided.

PWR_ON pads of SARA and LISA modules are not shared on the top layer of the nested application board, but


2.3.2 Module power-off

SARA-G3 and LISA series modules can be all properly switched off by means of the AT+CPWROFF command.

All LISA-U2 series modules except LISA-U200-00S modules can be additionally properly switched off by low pulse

on PWR_ON pin, as reported in Table 1 or in the LISA-U2 series Data Sheet [5].



2.3.3 Module reset (RESET_N)

Perform a reset of SARA-G3 series and LISA series modules in one of the following ways:

Forcing a low level on the RESET_N pin, causing an “external” or “hardware” reset

By means of the AT+CFUN command, causing an “internal” or “software” reset

The same compatible external reset circuit can be implemented for SARA-G3 and LISA series even if there are

minor differences in the RESET_N input voltage levels ranges and in the low level time. For these values, see Table 1 or the Data Sheet relating to the module [1], [3], [4], [5].

RESET_N pads of SARA and LISA modules are not shared on the top layer of the nested application board, but


On the RESET_N line of the nested application board there are spaces to mount proper bypass capacitors and

series ferrite bead / EMI suppression filter as additional circuit precautions for LISA-U series modules to satisfy

ESD immunity test requirements as suggested in LISA-U series System Integration Manual [7]. These additional components are not required for SARA-G3 series modules.

2.3.4 External 32 kHz input (EXT32K)

The external 32 kHz signal input pin (EXT32K) is available only on the SARA-G300 and SARA-G310 modules to

provide the 32 kHz reference clock for the Real Time Clock (RTC) timing, used by the module processor to reach

the low power idle mode and provide the RTC functions.

SARA-G350 series and LISA-U series are equipped with an internal 32 kHz oscillator to provide the same

functions.

LISA-C2 series do not provide RTC and the related functions.

The Y100 32 kHz oscillator, provided on the nested application board, is mounted only when SARA-G300 or

SARA-G310 is present (nested design version HR_1700A0), for implementing the application circuit described in

the SARA-G3 System Integration Manual [9].



2.4 RF connection

2.4.1 RF interface for Tx/Rx antenna (ANT)

The same compatible external circuit can be implemented for SARA-G3 and LISA series ANT pin even if there are some differences in the frequency ranges of the operating bands, as summarized in Figure 4.

VV II II

850

900

850

800 850 900 950

900 1800

1900 1900

1800

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

824 960 1710 1990

LISA-U100

LISA-U120

LISA-U260

LISA-U200

LISA-U230

VV II II

850

900

850

800 850 900 950

900 1800

1900 1900

1800

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

IIVIVI

VIIIVIII IV IV

824 960 1710 2170

850

900

850

800 850 900 950

900 1800

1900 1900

1800

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

IIVIIIVIII

824 960 1710 2170

LISA-U110

LISA-U130

LISA-U270

850

900

850

800 850 900 950

900 1800

1900 1900

1800

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

824 960 1710 1990

SARA-G310

SARA-G350

900

800 850 900 950

900 1800 1800

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

880 960 1710 1880

SARA-G300

800800

800 850 900 950

1900 1900

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

824 894 1850 1990

LISA-C200

Figure 4: Summary of operating bands frequency ranges among modules

On the ANT line of the nested application board there are spaces to mount a high-pass filter (series capacitor

and shunt inductor) as additional circuit precaution for LISA-U2 series modules to satisfy ESD immunity test requirements, as suggested in LISA-U series System Integration Manual [7]. These additional components are not

required for SARA-G3 series modules, which already provide ESD immunity up to ±4 kV / ±8 kV for Contact / Air

Discharge according to IEC 61000-4-2, and they are not applicable for are LISA-U1 series, which require an insulating enclosure of the device / antenna providing protection to contact / air discharge, and LISA-C2 series.

2.4.2 RF interface for Rx diversity antenna (ANT_DIV)

Only the LISA-U230 modules provide the RF input for Rx diversity antenna (ANT_DIV). So, the J200 SMA

connector and the R202 0 Ω resistor are mounted only when LISA-U230 is present (nested design version

HR_1700C0).

SARA-G3 series, LISA-C2 series, LISA-U1 series and the other LISA-U2 series modules do not support Rx diversity.



2.4.3 Antenna detection interface (ANT_DET)

An external application circuit, connecting ANT_DET to ANT pin, is implemented when the SARA-G350 module

is mounted, to provide antenna detection functionality. In the HR_170000 nested design version, the antenna

detection components are R105, L100, C104 and D100 and C103. R103 is not part of antenna detection circuit but is used only during the production to test the SARA-G350 ANT_DET pin. The antenna detection circuit is

identical to the one described in the SARA-G3 series System Integration Manual [9].

LISA-U modules are equipped with an internal circuit for antenna detection support. The external antenna detection circuit is not implemented in nested design versions with LISA-U. C103 / L101 become 15 pF / 39 nH

for LISA-U2 nested design versions that implement the recommended high pass filter to satisfy ESD immunity

test requirements at the antenna port. But by implementing this high-pass filter, the support of the antenna detection functionality is missed. C103 / L101 become 0 Ω / not-mounted for LISA-U1 version, allowing the

support of the antenna detection functionality.

SARA-G300, SARA-G310 and LISA-C2 series modules do not support antenna detection. Thus external antenna detection components are not mounted in the HR_1700A0 and HR_1700D0 nested design versions, and C103 is

a 0 Ω resistor.

Diversity antenna for LISA-U230

Common VCCline

Main antenna

Diversity antennaRF line

Tank capacitor

Common RFline

LISA-U230 diversityantenna pad

GND vias around RF lines

Common RF

antenna pad

Resistors used only for adapter testing during production

Figure 5: RF lines routing



Ground interconnection

vias

Ground vias around the RF tracks


Ground

interconnection

vias

Ground

interconnection

vias


Top Layer

Layer 2

Layer 3

Bottom Layer

Stack up of the board Ground vias around the RF tracks

VCC line

Common

antenna

Diversity

antenna for LISA-U2

Figure 6: Stack up of the nested design board and view of the different layers



2.5 SIM interface

The same compatible external circuit can be implemented for SARA-G3 and LISA modules: 1.8 V and 3.0 V SIM

card / IC are supported. LISA-C2 modules do not need an external SIM for Sprint and Verizon mobile operators. The LISA-C2 series SIM interface is hardware ready but the support of external SIM card / IC will be provided by

the upcoming firmware releases.

The SIM_DET pin on SARA-G3 series modules and the GPIO5 pin on LISA-U series modules provide a SIM detection function. LISA-C2 series modules do not support SIM detection. Refer to Table 7 for the availability of

this feature in the various modules.

SIM card hot insertion/removal is supported by all LISA-U2 series except LISA-U200-00S.

The SIM interface pads of SARA and LISA modules are positioned to facilitate routing in the nested design board.

2.6 Serial interfaces

2.6.1 UART interface

The same compatible external circuit can be implemented for SARA-G3 series and LISA series: 1.8 V unbalanced

asynchronous serial port with RS-232 functionality is provided on SARA-G3 modules (for AT command, data communication, MUX functionality, FW upgrade over AT), LISA-C2 modules (for AT command, data

communication, MUX functionality), LISA-U modules (for AT command, data communication, MUX functionality,

FW upgrade over AT or using the u-blox EasyFlash tool).

LISA-C2 series modules do not support DSR, DCD and DTR functions.

Table 1 and the Data Sheet relating to the module [1], [3], [4], [5] report minor differences in the internal pull-

ups and drivers strengths.

These are the default settings of the UART interfaces:

SARA-G3 series modules: automatic baud rate and frame format detection

LISA-U2 series except LISA-U200-00S modules: one-shot automatic baud rate and frame format detection

LISA-C2 series, LISA-U1 series and LISA-U200-00S modules: 115200 b/s baud rate and 8N1 frame format

For further details regarding UART interface settings and application circuits, refer to the relevant Data Sheet [1], [3], [4], [5], AT commands manual [2], [8] and System Integration Manual [6], [7], [9].

The UART pads of SARA and LISA modules are positioned to facilitate routing in the nested design board.

2.6.2 UART AUX interface

Only the SARA-G3 modules provide an auxiliary UART interface for FW upgrades using the u-blox EasyFlash tool,

and for trace log capture (debug purpose).

LISA modules do not provide auxiliary UART interface.

2.6.3 USB interface

SARA-G3 modules do not provide a USB interface.

LISA-U modules provide a High-Speed USB 2.0 interface for AT commands, data communication, FW upgrades

over AT or using the u-blox EasyFlash tool, and for trace log capture.

LISA-C2 modules provide a Full-Speed USB 2.0 interface for AT commands, data communication, FW upgrades.

In the nested design versions for LISA modules, the R200 routes the VBUS pin of the USB connector (J201) to the

VUSB_DET pad of LISA modules.

Refer to LISA series System Integration Manual [6] and [7] for suggestions about routing rules for USB_D- and

USB_D+ lines.



2.6.4 SPI interface

LISA-U modules provide an SPI interface (5-wire IPC interface for AT command, data communication, MUX

functionality, FW upgrade over AT). SARA-G3 and LISA-C2 modules do not provide an SPI interface.

Refer to LISA-U series System Integration Manual [7] for application circuits and further details.

2.6.5 DDC (I2C) interface

The same compatible external circuit can be implemented for SARA-G350 and LISA series: 1.8 V DDC (I2C bus

compatible) interface allows the communication with u-blox GNSS receivers.

SARA-G300, SARA-G310 and LISA-U200-00S modules do not support the DDC (I2C) interface.

LISA-C2 series modules will support the DDC (I2C) interface by the upcoming firmware releases.

All LISA-U2 series, except LISA-U200-00S modules, additionally support the communication with I2C slaves (other

than u-blox positioning receivers over the same DDC (I2C) interface) by means of dedicated AT commands.

Table 5 summarizes additional GPS/GNSS functionalities provided over GPIOs.

Function SARA-G350 pin name/number LISA pin name/number Comments

GPS data ready GPIO3 / pin 24 GPIO3 / pin 23 The GNSS receiver sends this interrupt to the wireless module to communicate there is data available for the DDC (I

2C) interface

GPS RTC sharing GPIO4 / pin 25 GPIO4 / pin 24 The wireless module sends this interrupt to the GNSS receiver to provide timing information

GPS supply enable GPIO2 / pin 23 GPIO2 / pin 21 This is an output of the wireless module used to enable/disable the supply of the GNSS receiver

Table 5: GPS/GNSS custom function overview over GPIOs



2.7 Audio interface

2.7.1 Analog Audio

Table 6 highlights the main characteristics and differences between the analog audio interface of LISA and SARA modules. SARA-G300 / SARA-G310, LISA-U100 / LISA-U110, LISA-U200-00S modules do not provide analog

audio interfaces.

Function SARA-G350 LISA-C2 LISA-U120/LISA-U130 LISA-U2

MIC_BIAS Supply output No bias circuit inside


MIC_GND Reference Not Available Not Available Not Available

MIC_P Diff. signal input (+) No DC blocking capacitor inside

Diff. signal input (+) DC blocking capacitor inside

Diff. signal input (+) DC blocking capacitor inside

Not Available

MIC_N Diff. signal input (-) No DC blocking capacitor inside

Diff. signal input (-) DC blocking capacitor inside

Diff. signal input (-) DC blocking capacitor inside

Not Available

SPK_P Diff. signal out (+)

16 load

Diff. signal out (+)

32 load

Diff. signal out (+)

16 load

Not Available

SPK_N Diff. signal out (-)

16 load

Diff. signal out (-)

32 load

Diff. signal out (-)

16 load

Not Available

Table 6: Summary of analog audio pin characteristics and differences among modules supporting audio interface

2.7.1.1 Analog Audio output

In the Nested Design, the analog audio output of LISA and SARA-G350 is used to drive a speaker (Figure 7):

SARA-G350:

o SPK_P, SPK_N pads are routed as a differential pair directly to the external speaker

LISA-C2 and LISA-U1 series:

o SPK_P, SPK_N pads are routed as a differential pair by R207 and R208 resistors the external speaker

LISA-U2 series:

o I2S1_WA, I2S1_CLK pads are routed by R203 and R204 resistors towards an audio codec, which provides the conversion between digital and analog audio

o Speaker lines are routed as differential pair up to the analog output of the codec

SARA-G350

LISA-U120 / LISA-U130 / LISA-C2

LISA-U2

44SARA SPK_P

53LISA-U2 I2S1_CLK or LISA-U1/C2 SPK_P

54LISA-U2 I2S1_WA or LISA-U1/C2 SPK_N

Headset Speaker

R208

R207

Nest

ed D

esi

gn L

imit

Use

r C

ircu

it

45SARA SPK_N

APPLICATION PROCESSOR

R204

R203

CODEC

Figure 7: Analog audio output circuit in the Nested Design



2.7.1.2 Analog Audio input

In the Nested Design, the analog audio input of LISA and SARA-G350 is connected to microphone (Figure 8):

SARA-G350:

o MIC_BIAS is used to bias the microphone by means of a bridge structure created by R413, R412 and R414 resistors. The MIC_GND pad constitutes the star connection to ground for microphone lines

o MIC_P, MIC_N pads are routed as a differential pair by means of C100 and C111 capacitors to the

microphone bias circuit

LISA-C2 and LISA-U1 series:

o LDO U301 is used to bias the microphone by means of a bridge structure created by R413, R412 and R414 resistors. The R415 0 Ω resistor constitutes the star connection to ground for microphone lines

o MIC_P, MIC_N pads are routed as a differential pair by means of R209 and R210 resistors to the

microphone bias circuit

LISA-U2 series:

o I2S1_TXD, I2S1_RXD pads are routed by R205 and R206 resistors towards an audio codec, which

provides the conversion between digital and analog audio

o Microphone lines are routed as a differential pair up to the analog input of the codec, which provides

also the bias for the microphone by means of the R312 and R313 resistors circuit

SARA-G350LISA-U120 / LISA-U130 / LISA-C2

LISA-U2

49SARA MIC_P

48SARA MIC_N

40LISA-U2 I2S1_TXD LISA-U1/C2 MIC_P

39LISA-U2 I2S1_RXD LISA-U1/C2 MIC_N

IN OUT

GND

Low Noise LDO Regulator

U301

R415

R323

R412R413

C310

Forces Star

connection

VMAIN

C301

Microphone

R414

V_MIC

47SARA MIC_GND

46SARA MIC_BIAS

R209

R210

R324

C110

C111

R110

R411

R206

R205 APPLICATION PROCESSOR

Nest

ed

Desi

gn

Lim

it

Use

r C

ircu

it

CODEC

R312

R313

CODEC_BIAS

Figure 8: Analog audio input circuit in the Nested Design



2.7.2 Digital audio

2.7.2.1 First digital audio interface (I2S/PCM)

Although the pads for the digital audio interface of SARA-G350 and LISA modules are not shared on the Nested

Design application board, they are positioned to facilitate routing, as shown in Figure 9.

Digital audio interface is provided on the I2S_TXD, I2S_RXD, I2S_CLK, I2S_WA pins of SARA-G350 modules

(1.8 V, PCM & Normal I2S modes, master, fixed sample rate) and LISA-U120 / LISA-U130 and most LISA-U2

series modules (1.8 V, PCM & Normal I2S modes, master & slave, configurable sample rate). LISA-U200-00S modules do not support audio. In LISA-C2 series modules, digital audio is provided on the PCM_DO, PCM_DI,

PCM_CLK, PCM_SYNC pins (1.8 V, PCM). The same compatible external circuit can be implemented according

to external digital audio device capabilities.

SARA-G300 / SARA-G310, LISA-U100 / LISA-U110, LISA-U200-00S modules do not provide digital audio

interfaces.

LISA-U1 I2S or PCM

LISA-U2 I2S or PCMLISA-C2 PCM

SARA-G350 I2S or PCM

Figure 9: Pads for the I2S interface of LISA and SARA-G350 modules are positioned to facilitate routing

For further details regarding digital audio interface settings and application circuits, refer to the relevant Data Sheet [1], [3], [4], [5], AT commands manual [2], [8] and System Integration Manual [6], [7], [9].



2.7.2.2 Second digital audio interface (I2S1)

All LISA-U2 modules (except LISA-U200-00S) provide a second I2S interface. This interface is not available on

LISA-U1 and LISA-C2 modules, which have analog audio pins mapped there instead. On SARA-G3 modules the

second I2S interface (I2S1) is also not available.

2.7.2.3 Enabling analog audio feature on LISA-U2 series modules

Since LISA-U2 series modules supporting an audio interface do not have analog input and output, it is necessary to provide a conversion between the digital audio and the analog one. Use an external codec audio connected

to a digital audio interface of the module for this conversion, as shown in Figure 7 and Figure 8.

The DDC interface of the module can control the external audio codec. A digital clock output (CODEC_CLK pin) is provided for the external audio codec. For more details on external codec integration refer to LISA-U series

System Integration Manual [7] I2S interface application circuits.

2.8 General Purpose Input/Output (GPIO)

LISA and SARA support a different number of GPIO pins:

SARA-G3 modules support 4 GPIOs: GPIO1-GPIO4 (SARA-G350 only)

LISA-C2 modules support 5 GPIOs: GPIO1-GPIO5

LISA-U1 modules support 5 GPIOs: GPIO1-GPIO5

LISA-U2 modules support 14 GPIOs: GPIO1-GPIO14 (except LISA-U200-00S supporting GPIO1-GPIO9)

Table 7 summarizes the features provided on GPIO1-GPIO5 pins of the different modules.

The GPIO1-GPIO4 and SIM_DET/GPIO5 pads of SARA-G350 and LISA modules are positioned to ease routing

on the nested application board.

SARA-G3 LISA-U1 LISA-U2 LISA-C2

Pin Name and Functions SARA-G350 SARA-G310 SARA-G300

LISA-U1x0-00S LISA-U1x0-01S LISA-U200-00S Other LISA-U2 LISA-C200

GPIO1

General Purpose Input 16 20 20 20 20 20

General Purpose Output 16 20 20 20 20 20

Pad disabled 16 16 20 20 20 20 20

Network status indication 16 20 20 20 20

GPS supply enable 16 20 20 20

GSM Tx burst indication 16 20 20 20 20

Module status indication 20

GPIO2



Pad disabled 22 22 21 21 21 21 21





SARA-G3 LISA-U1 LISA-U2 LISA-C2

Pin Name and Functions SARA-G350 SARA-G310 SARA-G300

LISA-U1x0-00S LISA-U1x0-01S LISA-U200-00S Other LISA-U2 LISA-C200

GPIO3



Pad disabled 24 24 23 23 23 23 23



GPS data ready 24 23 23

GPIO4



Pad disabled 25 25 24 24 24 24 24



GPS RTC sharing 25 24 24

GPIO5

General Purpose Input 51 51 51 51 51

General Purpose Output 51 51 51 51 51

Pad disabled 42 51 51 51 51 51

Network status indication 51 51 51 51

SIM card detection 42 51 51 51 51

GPS supply enable 51 51 51

Module operating mode 51

SIM hot insertion/removal 51

Table 7: GPIO function compatibility among modules

In the Table 7 above, the pin number is present if the function is available on the module, and the default

settings are highlighted in bold. For more details, refer to the corresponding module Data Sheet [1], [3], [4], [5], System Integration Manual [6], [7], [9] and AT commands manual [2], [8] +UGPIOC AT command.

2.8.1 GPIOs with GPS / GNSS functionalities

When LISA or SARA modules are used with u-blox positioning chips/modules, some GPIO pins enhance the

performance of the two systems through special functions. See Table 5 and Table 7 for the GPIO special

functions for GPS/GNSS functionalities and their availability on the various series of modules.

2.9 Reserved pins (RSVD)

The RSVD pin 33 of SARA-G3 series modules must be connected to ground, as must RSVD pin 5 on LISA series modules.

2.10 Production guidelines

For more details on SARA and LISA handling and soldering on the Nested Design board, refer to the SARA-G3

series System Integration Manuals [9] and LISA series System Integration Manual [6] and [7].



2.11 Deliverable package

Five Hardware Releases (HR) are provided together with this Reference Design

1) HR_170000 SARA G350 mounting version

2) HR_1700A0 SARA-G310 or SARA-G300 mounting version

3) HR_1700B0 LISA-U200, LISA-U260 or LISA-U270 mounting version

4) HR_1700C0 LISA-U230 mounting version

5) HR_1700D0 LISA-C200 or LISA-U1x0 mounting version

It is possible to mount different modules with the same BOM, due to the hardware compatibility

between SARA-G300 / SARA-G310 modules, LISA-U200 / LISA-U260 / LISA-U270 modules, LISA-C200 /

LISA-U1 series.

The above directories contain the following subfolders:

HS_Schematic where the hardware release schematic (in PDF format) is stored. HS_Schematic is available only with release HR_170000 as it applies to all versions. The text comments inside the schematic indicate

the BOM variations for the different versions

CS_Gerber where the Gerbers for board production are stored. Gerber files are available only with HW release HR_170000, and it is the same for all HW releases

BM_BOM provide list of materials, coordinates of components and paste mask Gerber files. This is available

for all HW releases. A different stencil is needed for production because paste mask Gerber files are different for SARA and LISA versions, as described in Figure 2. BoM and component coordinates are present in the file

IP06_HW_BM_1700x0_BOM_COUNT.xls, while paste masks are present in the files:

o 07_PASTEMASK_SARA_TOP.art top paste mask for versions with SARA

o 08_PASTEMASK_LISA_TOP.art top paste mask for versions with LISA

o 09_PASTEMASK_BOTTOM.art bottom paste mask for all versions.



Related documents [1] u-blox SARA-G3 Data Sheet, Docu No GSM.G2-HW-12001

[2] u-blox AT Commands Manual, Docu No WLS-SW-11000

[3] u-blox LISA-C200 series Data Sheet, Docu No CDMA-2X-11001

[4] u-blox LISA-U1 series Data Sheet, Docu No 3G.G2-HW-10001

[5] u-blox LISA-U2 series Data Sheet, Docu No 3G.G3-HW-11004

[6] u-blox LISA-C200 & FW75-C200 System Integration Manual, Docu No CDMA-2X-11004

[7] u-blox LISA-U series System Integration Manual, Docu No 3G.G2-HW-10002

[8] u-blox C200 AT Commands Manual, Docu No CDMA-2X-11002

[9] u-blox SARA-G3 System Integration Manual Docu No GSM.G2-HW-12003

All these documents are available on our homepage (http://www.u-blox.com).

For regular updates to u-blox documentation and to receive product change notifications, register on

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Revision history

Revision Date Name Status / Comments

- Nov. 14, 2012 ebez Initial release

1 Apr. 24, 2013 sses Updated status to Preliminary

Updated additional recommendations for VCC application circuits

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Reference Design for SARA / LISA modules...

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