Microelectronics Reliability 52 (2012) 1975–1980

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Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Reduction of annealed-induced wafer defects in dual-damascenecopper interconnects

Y. Abdul Wahab a,⇑, A.F. Ahmad b, H. Hussin a,c, N. Soin a

a Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysiab Silterra Malaysia Sdn. Bhd., 09000 Kulim, Kedah, Malaysiac Center of Electronic Engineering Studies, Faculty of Electrical Engineering, Universiti Teknologi MARA, 40450 Selangor, Malaysia

a r t i c l e i n f o a b s t r a c t

Article history:Received 29 May 2012Received in revised form 29 June 2012Accepted 4 July 2012Available online 31 July 2012

0026-2714/$ - see front matter � 2012 Elsevier Ltd. Ahttp://dx.doi.org/10.1016/j.microrel.2012.07.008

⇑ Corresponding author. Tel.: +60 12 4530542.E-mail address: nimsay_222@yahoo.com (Y. Abdu

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanicalstress in passivated interconnect lines. These mechanisms play a collective role for intensive researchof thermal stability for Cu interconnects reliability in CMOS technologies. This paper presents capabilitiesand performance on samples annealed using furnace vs He in situ anneal and in-line technique developedto reduce total defect count.

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1. Introduction

As MOSFETs have been scaled into the nanometer range, back-end of the line (BEOL) interconnects trigger major reliability con-cerns for integrated circuits [1,2]. The adoption of Cu interconnec-tion uses dual damascene technology, electrochemical plating(ECP) deposition, and chemical mechanical polished (CMP) plana-rization processes. Interconnects with larger grain size are pre-ferred to achieve lower electrical resistance and therefore bettercircuit performance. Post-electrochemical plating anneal has beenrecognized as a critical step and an efficient way to modulate thefinal Cu texture and internal mechanical stress. Higher anneal tem-peratures are required to stabilize the microstructure by initiatingand promoting Cu grain growth. Defects arise gradually due tothermal expansion coefficient mismatch between Cu and its sur-rounding ultralow k dielectric material and the Si substrate [1–3]. Electromigration (EM) and stress migration (SM) reliabilitystrongly depend on post-electrochemical plating (ECP) Cu filmgrain size, orientation, and intrinsic stress in patterned structures[2]. This can lead to electrical discontinuity through missing metaldefect (MMD) (or commonly known as Cu void) indirectly affectingyield process [3]. For copper dual-damascene interconnects twomain EM failure modes have been identified, namely the later(strong) mode and the early (weak) mode [1,4]. The later mode isdominated by void growth, while the early mode is governed bycombination of both void nucleation and subsequent morphologi-cal evolution due to thermomechanical stresses induced duringcooling after the thermal annealing [1,2,4–6].

In this work, we investigate yield enhancement by either Hein situ or furnace electro-plated anneals of Cu films. A significant

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l Wahab).

improvement is observed when the annealing temperature ofECP Cu is lowered below 200 �C with slower temperature ramprates. He in situ anneal has shown a lower defect counts whichindicates that ramp rate and temperature play an important rolein reducing MMD and other defects as presented in this work. Thisdevelopment has led to the explanation of the multimodal inte-grated problem of the defects distribution raised in BEOL processesparticularly in dual damascene Cu.

2. Experiments

Blanket 200 mm Si wafers were used for studying annealed-in-duced wafer defects. TaNx/Ta barrier layers of Cu seed were depos-ited using a 200 mm Barrier Seed Endura physical vapor deposition(PVD) system that uses a hollow cathode magnetron. Step cover-age, morphology, seed oxidation and corrosion are properties ofthe seed layer that are crucial for total feature fill. A seed layer withpoor step coverage can aggravate the formation of voids during theprocess of gap filling [3–5]. In order to ascertain a smooth and con-tinuous surface morphology of the seed, pre-stress measurementof seed layer was studied before the plating process. A systematiccomparison of defect formation on samples annealed using furnacevs He in situ anneal was carried out in this work. All copper depo-sition and He in situ anneal processing were performed on AppliedMaterials SlimCell™ ECP system. A post-ECP He in situ anneal wascarried out over a 60–180 �C temperature range, with annealduration ranging from 6 s to 2 h. In the He in situ anneal, thewafers began to be ramped at over 100 �C with less than a minutesoak time. For the furnace anneal, the wafers were loaded for al-most an hour with less than 200 �C soak temperature. The furnaceand He in situ anneal temperature profiles are displayed in Fig. 1aand b, respectively. The temperature profile for the furnace shows

Fig. 2. Box and Whisker Plot comparison between furnace and He in situ annealedsamples for the formation of missing metal defects (a) analyses of stress by anneal(b) analyses of reflectivity at 480 nm by anneal.

Fig. 1. Temperature profiles of (a) furnace and (b) He in situ anneals.

1976 Y. Abdul Wahab et al. / Microelectronics Reliability 52 (2012) 1975–1980

that the wafers were loaded onto zone 1 with less than 5 �C permin ramp up and for the He in situ, the wafers were ramped at30 �C per minute. The temperature reached a maximum pointand was then ramped down at the end of the pre-cool step in theHe in situ process. The wafers cooled down at the end of the coolrecipe.

It is impossible to uniformly heat the wafers at furnace geome-try. The temperature at wafer edges is higher than at their centersince they are exposed to the high temperature of the furnace wall.The edges will lose heat faster than the center during the coolingprocess [6,7]. Due to the non-uniform distribution of the wafer sur-face temperature during heating or cooling temperature transientsin furnace annealing, the temperature ramp rates of a furnace arelimited by the onset of plastic deformation of silicon wafers: dislo-cations will be induced if the yield strength of silicon is exceeded[7].

The results of post-stress and reflectivity of the plated Cu layerwere then recorded. As a final stage of defects qualification, CuCMP partial polish was employed and followed by a particle scan

check prior to plating defect monitoring. Detailed review and clas-sification of all defects on each processed wafers was carried outusing a scanning electron microscope (SEM), to build up a defectPareto chart for each wafer. On top of that, SEM images of MMDwere captured and selected defects were examined by SEM imagesof cross sections created by focused ion-beam (FIB). As a part of thedefect inspection and classification system, the classification codesand SEM images for every individual defect were automaticallydownloaded into a defect database system after the wafers werereviewed. In addition, the number and distributions of the defectsat the end of polishing step would be available for post-defect re-view analysis.

3. Experimental results

3.1. Process parameter comparison

The results of the process parameter comparison between fur-nace and He in situ anneal are presented in Fig. 2. Analysis of stressand reflectivity shows a significant difference in both processparameters between the two annealing conditions. The resultsshown in Fig. 2a indicate that high stress in the He in situ annealoccurred because of the faster ramp rate during the annealing pro-cess, resulting in stress-induced damage, such as voids or grooves[4–6]. Meanwhile, the high reflectivity observed in furnace-an-nealed samples is due to different grain size as shown in Fig. 2b[1]. Reflectivity is measured at 480 nm of wavelength and writtenin percentage with respect to silicon (WRS), with silicon being100%.

Fig. 4. Grain size comparison in optimized He in situ anneal (a) wafer center and (b)wafer edge.

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3.2. Grain size

Grain size during electrochemical plating depends on the linewidth of the Cu line and is smaller in thin lines. Annealing enlargesthe grain size and increases the conductivity of the Cu where thegrains span the full width of the line in a columnar structure [7–9].

Grain size comparison results for the two anneal processes areshown in Figs. 3 and 4. He in situ annealed films showed largeaverage grain diameters especially those excluding Canadian LightSource (CLS) boundaries since there are a much higher number ofsmaller grains. Notably, the average grain size at the wafer edge issignificantly higher than the average grain size at the center forboth types of annealing. However, from grain size distribution his-togram, furnace anneal still exhibits a higher frequency of hugegrains, with diameters greater than 10 lm. This is because furnaceanneal is optimized for large grain sizes to give lower Cu resistivity.In that case, line edge roughness limits the ultimate resistivity andit is suggested that the reduced resistivity is due to an increase inaverage grain size in the Cu interconnects [2].

These annealing treatment data reveal that the lattice structureat the wafer edge is likely to deform to a more negative free energy.Less energy input during thermal cycling to induce plastic defor-mations is required due to higher energy state upon deposition.This drawback is due to weaker texture and hence lower bindingenergies, disparity in twin formation from center to edge increasesas higher anneal condition applied. Excessive grain growth and thecorresponding weaker texture effectuate stress migration failure atthe wafer edge [1,5,10] as shown in Figs. 3b and 4b.

Since most semiconductor manufacturers anneal plated copperfilms immediately after plating to enable grain growth and lowresistivity, large grains are obtained. Studies have shown thatECP CU films demonstrate a self-annealing effect or recrystalliza-tion behavior [11]. The recrystallization of ECP Cu at room temper-ature, which is termed self-annealing, is a very distinctphenomenon [11,12]. Microstructure evolution occurs during atransient period of hours following deposition. It includes an in-crease in grain size, a change in film stress, and a decrease in sheetresistance [13]. During the re-crystallization progress, maximumsheet resistance drops by approximately 18–20% for a 1 lm copperfilm before stabilizing. The sheet resistance depends on the resis-tivity and thickness of a material, it can therefore be used to indi-cate the thickness of copper and reflects the deposition condition.This affects the process of electrochemical plating and manifestedin post CMP defects and yield loss phenomenon. Therefore, a ther-mal anneal process is an essential step to stabilize the electro-plated Cu films before CMP.

Fig. 3. Grain size comparison in furnace anneal sample (a) wafer center (b) waferedge.

Thin metal films have a strong (111) sheet texture which is afunction of the deposition process and the geometry of the film.The current density exponent in Black’s equation is about 2 forboth (111) and (200) electrochemical deposition copper lines,but the time-to-failure (TTF) of (111) copper lines is about fourtimes longer than that of (200) copper lines under the same cur-rent density [1,14]. The cause of a longer lifetime of (111) electro-chemical deposition copper lines over (200) copper lines is due tothe smaller variance of the grain boundary tilting distributionresulting in slower atomic diffusion. The growth of voids nucleatedin (111) grains is rather uniform [1,13], but if they move into anon-(111) grain, the void geometry changes dramatically. Fre-quently, the voids become very narrow and nearly slit-like, span-ning the entire interconnect and causing a failure without anactual increase in volume. Figs. 5 and 6 depict the grain texturecomparison in furnace and He in situ anneal samples at wafer cen-ter and edge, respectively.

Fig. 6 shows that He in situ anneal sample features stronger(111) sheet texture compared to furnace anneal and exhibits theadvantages of longer lifetime and uniformity.

3.3. Annealed-induced defects of furnace vs He in situ

MMD is related to the electroplating process, and is one of themost commonly seen defects in electro-plated Cu films [3]. The

Fig. 5. Grain texture comparison in furnace anneal sample (a) wafer center (b)wafer edge.

Fig. 8. MMD map and top-view SEM image of a defect.Fig. 6. Grain texture comparison in optimized He In-situ anneal (a) wafer center (b)wafer edge.

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comparison of the defect counts per wafer in furnace vs He in situanneal is shown in Fig. 7. It indicates higher MMD counts in fur-nace anneal process step. The overall defect count for both annealprocesses are not comparable and do differ significantly. We cantherefore conclude there was a significant difference in missingmetal defect counts between the two annealing process.

Fig. 8 illustrates a defect map of a wafer with MMDs and its cor-responding top-view SEM image. These defects were found onlyafter CMP partial polishing step. The defects are mainly concen-trated at wafer edge, and show a ‘ring’ signature at distances of20–30 mm from the wafer edge. The defect size ranged from0.2 lm to 8 lm where a big chunk of metal is lifted up from thetrench and bottom via. The important factors that influence theoccurrence of these MMDs is the anneal duration with high tem-perature as conducted in this study. In fact, Cu migrated throughstress away from the damascene features, leaving voids in its place,giving rise to metal defects [2]. Other possible cause of MMD wasattributed to the missing Cu seed from the wafer at the beginningof electroplating or preferentially etched during plating, thereforeno Cu is plated in that area, giving rise to missing metal at thisplace. Post-CMP defect review and classification can reveal previ-ously undetected defects that are unrelated to the CMP processstep. Defect detection and classification of other types of post-plat-ing defects were performed in detail in this work. For missing me-tal faults, the major types of post-plating defects are gouges,embedded particle, Cu void and corrosion.

Chemical–mechanical polishing (CMP) introduces defects in theform of scratches, metal rip-out, corrosion, dishing and erosion.One of the key areas of focus has been a defect type named a

Fig. 7. Missing metal defect (MMD) counts for Cu films annealed in furnace and Hein situ.

‘‘gouge’’ which is a scratch that is typically on the surface ofinterconnects.

Comparison of the gouge defect counts per wafer in furnace vsHe in situ anneal is shown in Fig. 9. The result indicates that thenumber of gouges is different for both anneals and differs in highercounts for three particular slots that underwent furnace annealsystem. This could be due to the type of slurry used, in particularthe abrasive particles employed since scratching is predominantlya mechanical wear phenomenon [4–6]. Fig. 10 shows pit, void andcrater counts for both annealing systems used in this study. Theamounts for all such defects were found to be comparable.

Fig. 11 demonstrates that embedded defect counts showed sig-nificantly different behavior between the two anneals. The embed-ded defect level was found to increase in furnace-annealed waferswith respect to He in situ. Any contaminant particles or surfacecontaminations will disrupt the growth of a uniform film. Thefunction of the time between seed deposition and plating, specificdeposition equipment (vacuum quality of physical vapor deposi-tion, cleanliness of the load locks, especially during venting, etc.)and also a time window between plating process and annealingstep can all contribute to the existence of embedded flaws [1].Other possibility of embedded particles is a core defect in the bar-rier or seed layer prior to the ECP process. Previous study showsthat surface particles (dielectric or metal) on top of the seed willbe lifted up by the plated Cu layer and will remain on top afterthe copper electrochemical plating process [6,7]. If the core defectis smaller than 1 lm, the embedded defect appears dome-shapedwith a particle sticking out of the top and if the core defects arebigger than 1 lm the defect takes up the appearance of the coredefect.

Fig. 9. Gouge defect counts for Cu films annealed in furnace and He in situ.

Fig. 10. Box plot of pit/void/crater defect counts for Cu films annealed in furnaceand He in situ.

Fig. 11. Box plot of embedded defect counts for Cu films annealed in furnace and Hein situ.

Fig. 13. MMD performance on patterned wafers after recipe optimization.

Y. Abdul Wahab et al. / Microelectronics Reliability 52 (2012) 1975–1980 1979

Defects are tremendously reduced after implementing new pro-cess recipe and hardware modification from baseline in situ annealto modified (He) in situ anneal as shown in Fig. 12, where the MMDdata decrease for the improved in situ annealing. A significantimprovement is observed when the annealing temperature ofECP Cu is lowered with a slower temperature ramp rate in Hein situ. MMD performance on patterned wafers after recipe optimi-zation is depicted in Fig. 13.

Fig. 12. Defects are tremendously reduced after implementing a new process recipeand hardware modification.

4. Conclusion

This paper reveals the impact of annealing conditions seen indual damascene copper technology, with an emphasis on major de-fects that affect yield. As a conclusion, there is a significant differ-ence in annealed-induced defect levels between He in situ andfurnace annealed films. Investigation quantified the difference incopper grain size and (1 1 1) sheet texture has a significant perfor-mance as a consequence of the annealing conditions. A further sys-tematical study is currently underway on the interplay betweengeometry features, microstructure, and void evolution.

Acknowledgements

This work was supported by Thin Film Metal Group from Silter-ra Malaysia and University Malaya High Impact Research Grant(UM.C/HIR/MOHE/ENG/ 19).

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