Reducing Noise Problems in LSI Services Part B(2) and low drive VSS Xin Xout RD Ø Rf LSI device...

© 2008, Renesas Technology America, Inc., All Rights Reserved

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Course Introduction

Purpose

This Part-B course discusses design techniques that are used to reduce

noise problems in large-scale integration (LSI) devices.

Objectives

Learn approaches and design methods for minimizing electromagnetic

interference emitted by LSI devices.

Gain insight into how Renesas applies these techniques for handling

noise problems in its microcomputer products.

Content 26 pages

Learning Time 30 minutes


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Reducing EMI

EMI reduction is a goal shared by

the semiconductor experts who design LSI devices and by the

system engineers who apply those devices.

Process encompasses techniques for reducing the

electromagnetic interference emitted by a specific system, circuit

or device that causes other devices/circuits to operate incorrectly.


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EMC Electromagnetic Compatibility

EMI Electromagnetic Interference

EMS Electromagnetic Susceptibility

SSCG Spread-Spectrum Clock Generator

WDT Watchdog Timer

PLL Phase Locked Loop

I/O Input/Output Port

Core A microcontroller chip is composed of a core, I/O ports, and power supply circuitry. The core consists of the CPU, ROM, RAM, and blocks implementing timers, communication, and analog functions.

Power supply

Two power supplies are applied to the LSI: Vcc and Vss. The core power supply internal to the LSI is VCL (internal step-down). The Vss-based power supply routed through the LSI is VSL.

Driver buffer

Output circuit transistors as well as output circuits for driving signals with large load capacitance and I/O port output transistors. Clock/bus driver, signals between blocks, etc.

OSC

CPG Clock Pulse Generator

Oscillator

POR/LVD Power-On Reset/Low-Voltage Detect functions

Harness Cables (wires) connecting a board and power supply

or connecting one unit in a system to another.

Explanation of Terms


4

Desired output waveform

Clipped waveform produces EMI

"H"

Externalcomponents

Rf

Vcc

Vss

Vcc

Vss

Oscillator Circuit Design

For minimum EMI, oscillator’s output should be a sine wave

Excessive gain in the oscillator circuit’s inverting amplifier can cause clipping.

The EMI that results contaminates power supply lines and other circuits


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EMI can be reduced by adjusting the drive-capacity (gain) of the oscillator’s amplifier circuit

Manual adjustment is via an external resistor, RD

Automatic or software-controlled capacity-switching uses logic-controlled circuits to implement high and low drive VSS

Xin Xout

RD

ØRf LSI device

"H”

High drive capacity

High gain“L”

Low drive capacity

Low gain

Adjusting Gain of Oscillator


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fo = N x fs

fs fo

PLL Circuit

Phase-locked Loop Circuit

PLL allows frequency of oscillator circuit to be lowered (decreased by

a factor of 1/N), thereby reducing higher frequency harmonics and EMI

Circuit can be built with jitter function to disperse high-frequency

noise, thereby decreasing overall noise level


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OCO

System clock

Supplied to cores and functions

I/O

I/O

I/O

Primary oscillator

(+ PLL)

CPG

Oscillation stop detect (OSD) feature provides automatic switching for

fail-safe operation

Pads

On-chip oscillator circuit

On-chip Oscillator Circuit

OCO = Built-in alternative, high-performance oscillator circuit

Provides backup for

primary crystal-

controlled oscillator

circuit

Protects application

against failure due to

loss of system clock

Allows system

operation to continue

or lets application

shut down safely


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-0.5%

Time

f

Example of SSCG modulation waveform

33kHz

f0 = 1.0GHz

Noise emissions data

Gain

(dB)

-0.5%

With SSCG

Without

SSCG-7 to -10 dB

f0 Freq

Spread-spectrum Clock Generator

SSCG is an ideal solution for high-speed products

Is combined with the PLL circuit in LSI devices

Produces modulated waveform with wider spectrum

Reduces noise emissions

Is a very useful noise reduction technique for devices that can withstand

variations in clock frequency


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I/O

I/O

I/O

CPGOscillator(+ PLL)

System clock

To cores and

functions

Clock and Bus Driver Capacity

Capacity should be matched to the operating frequency and

signal load of the lines being driven

Excess capacity wastes

power and generates

unnecessarily high levels

of EMI

Inadequate capacity

causes performance

degradation

Design challenge is to

optimize clock and bus

lines and their drive

circuits


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Clock line

Bus line

CPG

ROM RAM

CPU

TIMERSC

OM

MU

NIC

AT

ION

Clock and Bus Signal Lines

Signal lines with high frequencies and high drive levels should

be kept as short as possible


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Some transistors are drawn physically large here to indicate

a large current capacity. In reality, this may not be the case

Typical On-chip Module

Transistors in Logic Circuits

Transistors should be carefully selected so that size (current

capacity) is as small as it can be, considering the design

function, to minimize chip area, power, and EMI

Can be selected from a large library of different sizes


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~100Ω to

150Ω~

Vcc

GND

~50Ω~

~100Ω~

Impedance Mismatch

Vcc

GND

~100Ω~

~100Ω~

Impedance Match

Vcc

GND

~50Ω~

~100Ω~

If required, an external series resistor, (R = 50Ω to 1kΩ) can be used to stabilize the output R1

I/O-port Transistors

Transistors should match

characteristic impedance

of circuit-board wiring

(~100 to 150Ω when parts are mounted)

Mismatches cause ringing at port, producing EMI


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2. Using slew-rate control tolimit shoot-through current

V

t

NMOS turns on

after PMOS

turns off

V

1. Staggering timing of I/O port lines

•

•

•

•

•

•

t

V

t

t

V

V

P00

P01

P07

•

•

•

•

•

•

Delay ckt

Port triggered

Delay ckt

Delay ckt

Delay ckt

Delay ckt

Delay ckt

I/O-port Rush Current Reduction

Rush current can be reduced in various ways


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3. Connecting multiple transistors in parallel to I/O terminal output buffersand turning them on in stages

Vdd

Vss

1 2 3

1 +1 2 +1 2 + 3

t1 t2 t3

4. Using feedback capacitors in the I/O buffers to broaden the output waveform

Feedback capacitors

Vss

Vdd

I/O-port Rush Current Reduction

Rush current can be reduced in various ways


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Clock driver circuit

Pooled charge

Vdd

Vss

CLKC1

Bus driver circuit

Pooledcharge

Vdd

Vss

BUS

Put capacitors near bus-driver

transistors

C2

Rush Current Reduction in Core

Rush current in core can be reduced by using capacitors to

store a signal’s excess charge over a period of time

Examples: Clock driver circuit, bus driver circuit


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Flash ROM

memory array

Step-up

circuit

Vcc

Vss

Vpp

C

Current-limitcircuit


Rush current can be decreased in core by implementing in the

step-up circuit a circuit that limits the current that charges the

large storage capacitor

Example: Flash ROM


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•

•

•

•

•

•

•

•

•

•

•

•

• • •

• • •

Step-down circuit

Vcc

Vss

Vcl

Vslor

Vss

5V I/O

A/D, D/A

ROM

RAM

CPU

Peripheral modules

Vdd

• • • • • •

C1


Another way to reduce rush current in the core is sequence the

activation of the various power supplies that drive the core circuits


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Indicates module-stop signal

ROM

CLOCK RAM

TIMER-1 SCI

TIMER-2 IIC

TIMER-3 CAN

I/O

BUS

System controller

CPU

Module-stop Function

The Module-stop function disconnects the supply voltage to a

module not being used

This saves power and eliminates the noise the module produces


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Indicates main

clock signal

Clockto module

Module-stopsignal

Clock signal inside

module

I/O

ROM

CLOCK RAM

TIMER-1 SCI

TIMER-2 IIC

TIMER-3 CAN

BUS

CPU

Clock-signal Control

EMI is reduced when the clock distributed within the module is

turned off when it isn’t needed


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I/O

Oscillatorcircuit

Systemclock line

Clock line for φ

CPG

φφφφ-pin Output Control

The φφφφ clock is turned off in Single-chip mode and also when it

isn’t required for clock synchronization in Extended mode

Can be implemented

using a switch at the

output driver

Performs best when

the φ clock control is

configured at the source


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Can be implemented


output driver

Performs best when



Clock line for φφφφremains active

Traditional design(not recommended)

I/O

Oscillatorcircuit

Systemclock line

CPG

Traditional Method


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Improveddesign

Clock line to φφφφ driveris disconnected

I/O

Oscillatorcircuit

Systemclock line

CPG

Innovative Method



Can be implemented


output driver

Performs best when




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I/O

CPU ROM

RAM

TIMER-1 SCI

IIC

CAN

BUS

TIMER-2

40MHz

Div

ide b

y 2

Switch

SYSTEM CLOCKO

sc. ckt.

High-speedon-chip oscillator

(40MHz)

20MHz 40MHz

20MHz

Independent High-speed Clock

The built-in high-speed clock is generated by an on-chip

oscillator and supplied only to peripherals that require it

Can be used

as a backup

for the main

system clock


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I/O

20MHz 10MHz

CPU ROM

RAM

TIMER-1

SCI

IIC

CAN

BUS

SYSTEM CLOCK

TIMER-2

TIMER-3

10MHz

10M

Hz

PSCOsc. C

kt.

Low-speed Clock

Some Renesas LSI devices have a low-speed clock that is software

switched and supplied to the peripheral modules that can operate at

lower frequencies

20MHz


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Simulation circuit diagram (conceptualization)

Internal step-down circuit

Internal capacitance

of chip

Oscill

ato

r buffer

Vcc

Vss

Pa

ck

ag

e e

qu

iva

len

t c

irc

uit

EM

I n

ois

e e

va

lua

tio

n c

irc

uit

eq

uiv

ale

nt

cir

cu

it

R+L

CPG

Estimating EMI Noise Levels

Can be performed by making simplifying assumptions about

the chip, then performing SPICE simulation


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Course Summary

For more information on specific devices and related support products and material, please visit our Web site:

http://america.renesas.com

Techniques for reducing EMI in oscillator circuits

Ways to optimize the capacity of clock and bus

drivers and clock and bus lines

Methods for reducing rush current

Ways to slow down a device’s overall operating rate

Technology for estimating noise levels

Reducing Noise Problems in LSI Services Part B(2) and low drive VSS Xin Xout RD Ø Rf LSI device...

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Transcript of Reducing Noise Problems in LSI Services Part B(2) and low drive VSS Xin Xout RD Ø Rf LSI device...