REDNET Overview

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REDNET Overview Rok Stefanic ( [email protected] ) the best people make cosylab

description

the best people make cosylab. REDNET Overview. Rok Stefanic ( [email protected] ). Outline. What does REDNET provide to the users How it looks like How it works (MTG & MTR) Responses - controlling the devices What we have done in CWO2 Refine the requirements - PowerPoint PPT Presentation

Transcript of REDNET Overview

Page 1: REDNET Overview

REDNET Overview

Rok Stefanic ([email protected])

the best people make cosylab

Page 2: REDNET Overview

Outline

What does REDNET provide to the users How it looks like How it works (MTG & MTR) Responses - controlling the devices

What we have done in CWO2 Refine the requirements Architecture and design Mock-up demo of the system

What follows in future CWOs Detailed FPGA and LV architecture Implementation of the system

Cosylab 2010 2

Page 3: REDNET Overview

What does REDNET provide to the usersHow it looks like

SCS

1.MTG

2.Transport

3. receivers w. equipment

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• prepare data

• process data in hard real-time

• make sure everybody gets

it @ the same time (200m =

~1s)

• decode events and poke

equipment

MTGMTG

LabVIEW code running on crate controller

Transport Layer

Fast

Equ

ipm

ent I

nter

face

(re

al-t

ime

opt

ic c

onn

ect

ion)

PVSS

MTG

MTG FECOS Component

MRF EVG

Equipment

BDCS

VAA

Fanout

MTR

MTR FECOS Component

MRF EVG

PXI Crate

FECOS

Equipment under

control

PXI

Users and Control Systems

FECOS

Slow

Equ

ipm

ent I

nter

face

(no

n re

al-t

ime

feed

bac

k lin

k)

PXI

LabVIEW code running on crate controller

Controlled Equipment

PXI Crate

User Interface (UI)

Supervisory Interface (SI)

Auxi

liary

In

terf

aces

Equipment under

control

Equipment under

control

Other FECOS components

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MTG redistributes the Run file with a list of cycles

VAA requests the generation of a cycle from the run list

Receiver components generate responses(digital signals, irq, triggers…)

What does REDNET provide to the usersHow it works

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MTR PXIMTR PXI

MTG PXI

Server DatabaseR

PXI - System Controller

FECOS Component

hard drive

RAM

VAAPVSS

BDCS

UI SI

MRF EVG

FEI Fanout

Internal HW interface (cPCI)

Internal HW interface (cPCI)

Fast Equipment Interface - FEI (real-time fiber optic link)

Slo

w E

qu

ipm

en

t In

terf

ace

- S

EI

(Gig

ab

it E

the

rne

t)

ProfiBUS

TX

MTR PXI

MRF EVR

Internal HW interface (cPCI)

Internal HW interface (cPCI)

FlexRIOFlexRIO ProfiBUS

AuxiliaryInterface

AI1

AuxiliaryInterface

AI2

AuxiliaryInterface

AI3Interlock

Interlock

FEI

Req Req

ResReq

Ack

Timing Events

Commands

Equipment under control

Load

ing

of c

ycle

s be

long

ing

to a

req

uest

ed r

un fr

om lo

cal

stor

age

into

mem

ory

Req

uest

s fo

r ac

tivat

ion

of a

ccel

erat

or r

uns

Loading of individual cycles into the EVG module

Emission of timing events and commands

Distribution of tim

ing events to all receiver com

ponents

Retrieval and storing the MTG accelerator cycle files to the MTG local storage

Rec

eptio

n of

tim

ing

even

ts a

nd c

omm

ands

Acknowledging received commands

Res

Generation of responses to received timing events

Device specific FECOS component configures the MTR with desired responses

GPS Receiver

GPS 1PPS Trigger signal

PXI backplane

GPS 10 MHz clock signal

GPS Current time

GPS 10 MHz clock signal extraction from the FEI and its distribution to PXI modules

PXI - System Controller

Device specificFECOS

Component

hard drive

MTRFECOS

Component

RAM PXI backplane

Req

Res

Ack

Device specific configuration retrieval(desired responses...)

VAA Activates a Run (+ run file)

MTG Generates timing events from the requested cycle

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What does REDNET provide to the usersMTG

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PXI crate Controller LV RT MRF EVG

5 Execution slot tables (priorities) 1s granularity of event emission Emission of asynchronous timing

events 10 Hz heartbeat timing event (time

grid) GPS time and clock distribution

TX

MTG PXI

PXI backplane

MRF EVG

FEI Fanout

Supervisory Control Systems

Receivercomponent

Receivercomponent

Internal HW interface (cPCI)

Internal HW interface (cPCI)

Fast Equipment Interface - FEI (real-time fiber optic link)

FEI

Slow Equipment Interface - SEI(Gigabit Ethernet)

Supervisory Interface(Gigabit Ethernet)

FEI

Users

ProfiBUS InterlockPXI - System Controller

hard drive

RAM

FECOS Component

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What does REDNET provide to the usersMTR – controlling the devices

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Digital/optical signals on the MRF EVR outputs

Re-distribution of timing events to PXI cards Trigger neighbor PXI cards LabView application notification

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PXI crate Controller LV RT MRF EVR Other PXI modules

Page 7: REDNET Overview

What does REDNET provide to the usersMTR - controlling the devices

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No configuration files are needed. Device specific application requests the MTR which responses it

needs (+ parameters such as timing event, pulse delay, width…) Multiple interfaces can be used concurrently Global propagation delay compensation parameter (<10ns steps)

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What does REDNET provide to the usersResponses – Auxiliary interface outputs

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Pulses or output toggle Configurable pulse delay and width (< 10 ns steps) Each digital/optic output can have different configuration (ES,

event, delay, width, type)

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What does REDNET provide to the usersResponses – Redistribution of events to PXI cards

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Each received timing event can be distributed to other PXI modules EVR distributes timing event value and execution slot to which the

event belongs

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What does REDNET provide to the usersResponses – Triggering PXI cards

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Trigger pulses generated on PXI star trigger lines Useful for simple devices (ADC cards etc.) which only need trigger

signals

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What does REDNET provide to the usersResponses - LabView application notification

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EVR issues an IRQ when a specific timing event is received MTR distributes the received event to all subscribed device specific

applications as a FECOS event

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What we have done in CWO2

Documentation Refined the requirements in detail Finished top level architecture and design All documents are ported to Enterprise Architect models

All requirements covered by the top-level architecture Traceability

Fully mastered the MRF EVG and EVR cards FPGA + 2.5 Gbps LabView support for MRF

Made mock-up demo of the system Emission of timing events, commands, asyn. events,

acknowledgments, uses FECOS… Defined tasks for future CWOs

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What have we done in CWO2REDNET Mock-up demo

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What have we done in CWO2REDNET Mock-up demo

Listing of available sequence files on HDD

Sequence file editing

Emission and reception: Timing events Commands Asynchronous timing

events (Emitted at any time)

Acknowledgments Each MTR sends ACK MTG lists all received

ACKs

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What have we done in CWO2REDNET Mock-up demo contd.

Response generation:

I/O signals on MRF EVR

Distribution of received events over PXI RT trigger bus (to PCC)

SW notifications

User can configure which responses are generated for received events

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What follows in future CWOs

Internal architecture design for the MTG and MTR: LabView application FPGA (MRF EVG & EVR)

Implementation of the system Full size accelerator cycles Execution slot support Full auxiliary interface outputs support Synchronization with GPS Heartbeat event generation MTR & MTG configuration (xml files) …

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Page 17: REDNET Overview

Cosylab 2010

Thank you for your attention

Questions?