Realization of Cascade of Resonators with Distributed Feed-Back ...

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

REALIZATION OF CASCADE OFRESONATORS WITH DISTRBUTED

FEED-BACK SIGMA-DELTA

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av

Jawad SaleemAbdul Mateen Malik

LiTH-ISY-EX--09/4314--SE

Linköping 2009

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

REALIZATION OF CASCADE OFRESONATORS WITH DISTRBUTED


Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av


LiTH-ISY-EX--09/4314--SE

Handledare: SupervisorPer Löwenborg, Linköpings universitet

Examinator: ExaminerPer Löwenborg, Linköpings universitet

Linköping, 14 August, 2009

Avdelning, InstitutionDivision, Department

Department of Electrical EngineeringDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2009-008-14

SpråkLanguage

� Svenska/Swedish� Engelska/English

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�

RapporttypReport category

� Licentiatavhandling� Examensarbete� C-uppsats� D-uppsats� Övrig rapport�

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URL för elektronisk versionhttp://www.ep.liu.se

ISBN—

ISRNLiTH-ISY-EX--09/4314--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED


FörfattareAuthor


SammanfattningAbstract

The Sigma Delta Modulator (SDM) based analog to digital conversion is costeffective and have the advantages as higher reliability, increased functionality, andreduction in chip cost.

The thesis work includes the modeling of SDM with the signal flow graph inMatlab, optimization of the coefficients to improve the noise transfer function andsignal transfer function. A procedure to find the maximum stable input rangefor the design. Scaling the inputs of the integrator so that the maximum outputsignal can be obtained according to the operational transconductance amplifier(OTA) output range. Further we derived error bound for the design. Then stepby step realization of the SDM form the signal flow graph (SFG) to a fully differ-ential switched-capacitor (SC) network is shown. The work also includes completedifferential transistor level realization for 3-bit flash analog to digital converter(ADC), thermometric to binary encoder, a switch-capacitor digital to analog con-verter (DAC) circuit and an on-chip circuit realization of the non-overlapping clockgeneration circuitry.

NyckelordKeywords sigma-delta modulator, operational transconductance amplfier, analog to digital

converter, digital to analog converter, signal flow graph

Abstract

The Sigma Delta Modulator (SDM) based analog to digital conversion is costeffective and have the advantages as higher reliability, increased functionality, andreduction in chip cost.

The thesis work includes the modeling of SDM with the signal flow graph inMatlab, optimization of the coefficients to improve the noise transfer function andsignal transfer function. A procedure to find the maximum stable input rangefor the design. Scaling the inputs of the integrator so that the maximum outputsignal can be obtained according to the operational transconductance amplifier(OTA) output range. Further we derived error bound for the design. Then stepby step realization of the SDM form the signal flow graph (SFG) to a fully differ-ential switched-capacitor (SC) network is shown. The work also includes completedifferential transistor level realization for 3-bit flash analog to digital converter(ADC), thermometric to binary encoder, a switch-capacitor digital to analog con-verter (DAC) circuit and an on-chip circuit realization of the non-overlapping clockgeneration circuitry.

v

Acknowledgments

In The Name of Allah The Most Beneficent the Most Merciful. We are verymuch thankful to our supervisor Dr. Per Löwenborg for his kind support, helpand guidance. We are very thankful to our parents, grand parents, teachers andfamilies who encouraged us and prayed for our success. We are thankful to ourfriend Khurram Shahzad, Abdul Majid, Abdul Whaeed for their support, time andhelp in all respects. We are thankful to Peter Johansson for his help regardingcomputers and software availibility. We are also thankful to Fahad Qazi andFarooq-ul-Amin for their comments on our thesis. We are also thankful to HECPakistan for their support.

vii

Contents

1 Introduction 31.1 Why sigma-delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Goals of the project . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4 Design challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.5 Work flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.6 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Sigma-Delta Modulator 72.1 Basic concept of SDM . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 Noise shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.4 Limitations of SDM . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 CRFB with feed forward and feed back connections 113.1 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Matlab realization . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.1 Coefficient calculation for third-order SDM . . . . . . . . . 133.3 Matlab model of the third-order CRFB SDM . . . . . . . . . . . . 163.4 Maximum stable input range . . . . . . . . . . . . . . . . . . . . . 18

4 Clocking for SC SDM 214.1 Clock generation module . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Switched-capacitor realization of SDM 255.1 Realization from SFG to SC network . . . . . . . . . . . . . . . . . 25

6 OTA modeling for SDM 316.1 Small signal model . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Analog to digital converter 377.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.2 Resolution of ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.3 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

ix

x Contents

7.5 Behavioral level design . . . . . . . . . . . . . . . . . . . . . . . . . 397.6 Circuit realization . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.6.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.6.2 Inverter and SR-latch . . . . . . . . . . . . . . . . . . . . . 407.6.3 Simulation results of ADC . . . . . . . . . . . . . . . . . . . 41

8 Digital to analog converter 438.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438.2 Behavioral level design . . . . . . . . . . . . . . . . . . . . . . . . . 438.3 Circuit realization . . . . . . . . . . . . . . . . . . . . . . . . . . . 438.4 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9 Results 479.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.1.1 SC realization of the SDM structure . . . . . . . . . . . . . 479.1.2 OTA modeling . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . 489.2.1 Matlab model results . . . . . . . . . . . . . . . . . . . . . . 489.2.2 Cadence model results . . . . . . . . . . . . . . . . . . . . . 49

Bibliography 51

List of Figures1.1 Principle amplitude spectrum of a multicarrier WCDMA signal. . 41.2 Heterodyne receiver architecture. . . . . . . . . . . . . . . . . . . . 5

2.1 First-order sigma-delta modulator with 3-bit quantizer. . . . . . . 72.2 FFT analysis showing signal and quantization noise for a Nyquist

rate ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 FFT analysis illustrating oversampling. . . . . . . . . . . . . . . . 92.4 FFT analysis showing shaped noise. . . . . . . . . . . . . . . . . . 10

3.1 Third-order SDM with interconnections. . . . . . . . . . . . . . . . 113.2 Third-order SDM with placement of delays. . . . . . . . . . . . . . 123.3 Magnitude response of the third-order SDM. . . . . . . . . . . . . 133.4 General structure of a three bit quantizer sigma-delta modulator . 143.5 Pole-zero plot for L0 and L1. . . . . . . . . . . . . . . . . . . . . . 153.6 Integrator model for Matlab. . . . . . . . . . . . . . . . . . . . . . 163.7 Precedence graph for third-order SDM. . . . . . . . . . . . . . . . . 163.8 Output spectrum of third-order SDM. . . . . . . . . . . . . . . . . 173.9 Filtered signal amplitude spectrum. . . . . . . . . . . . . . . . . . . 183.10 SNDR versus input signal amplitudes. . . . . . . . . . . . . . . . . 183.11 MSIR (minimum of the maximum amplitudes). . . . . . . . . . . . 19

4.1 Clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 214.2 Non-overlapping clock generator. . . . . . . . . . . . . . . . . . . . 224.3 Clock generator schematics results. . . . . . . . . . . . . . . . . . . 23

5.1 Third order SDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.2 Third order SDM with full or half delay at the integrator input. . . 265.3 A general integrator model. . . . . . . . . . . . . . . . . . . . . . . 265.4 Inverting and non inverting connection. . . . . . . . . . . . . . . . 275.5 Integrator with two inverting inputs. . . . . . . . . . . . . . . . . . 285.6 Integrator having one inverting and one non inverting input. . . . . 295.7 Fully differential SC CRFB network . . . . . . . . . . . . . . . . . 30

6.1 SC integrator with several inputs. . . . . . . . . . . . . . . . . . . . 316.2 Return ratio model of the SC integrator. . . . . . . . . . . . . . . . 326.3 Two pole small signal model . . . . . . . . . . . . . . . . . . . . . . 326.4 SFG with error sources used to simulate SNDR degradation due to

incomplete settling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.5 SNDR vs Error bound. . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1 Three-bit flash ADC with decoder. . . . . . . . . . . . . . . . . . . 387.2 Comparator schematics. . . . . . . . . . . . . . . . . . . . . . . . . 407.3 The SR-latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417.4 Test bench for the ADC. . . . . . . . . . . . . . . . . . . . . . . . . 417.5 Simulation results of ADC schematic design. . . . . . . . . . . . . . 42

2 Contents

8.1 Architecture of DAC element. . . . . . . . . . . . . . . . . . . . . . 448.2 SC DAC structure for the SDM. . . . . . . . . . . . . . . . . . . . 448.3 Test bench setup to check the functionality of the DAC . . . . . . 458.4 Simulations results from the schematic of DAC. . . . . . . . . . . . 46

9.1 Output spectrum of the third-order modulator. . . . . . . . . . . . 489.2 Test bench for the third-order CRFB SDM. . . . . . . . . . . . . . 499.3 Simulation results from cadence model. . . . . . . . . . . . . . . . 50

Chapter 1

Introduction

In the introductory chapter, we discuss why there is a need of Sigma Delta A/Dconverter in newer trends and what are the main goals of our project, as we workedon Sigma Delta Modulator so the Objectives, Limitations in our thesis and thedesign flow through which we proceed will be described.

1.1 Why sigma-deltaThe signal processing tasks are mostly performed in digital domain because of

the robustness, increasing speed and the inexpensive implementation of the digitalcircuits. As most of the signals are analog there be a need for the data converters,a very important block in the communication system and the interface betweenthe analog world and digital domain.

Sigma Delta Analog to Digital conversion is commonly used in many communi-cation applications because of its high-speed and accuracy. As opposed to Nyquistrate data converter, sigma delta data converter employ oversampling and noiseshaping. These concepts are described in detail in upcomming chapters.

1.2 Goals of the projectThe objectives of our project is to investigate the Signal Flow Graph (SFG)

of the resonator based SDM structure, with realizable delay placement inside theloops of the SDM to avoid the instability of overall design. This can be done inMatlab by using different topologies of the delay placement in the SDM model.Checking the SNR and then go for the circuit realization of the proposed SDM.

When the above step is completed, the scaling of the capacitors and outputrange of the integrators is investigated because without scaling the SDM can notremain stable for longer period of time.

ADC and DAC should also be realized at circuit level.

3

4 Introduction

1.3 SpecificationsWe are designing the ADC for the WCDMA applications, that usually uses the

direct sequence CDMA. In WCDMA the channel separation is 5Mhz per carrierand the signal band width is of 3.84Mhz as shown in Fig 1.1

Figure 1.1. Principle amplitude spectrum of a multicarrier WCDMA signal.

The ADC which we design can also be used in the heterodyne receiver archi-tecture shown in Fig 1.2 where a radio frequency (RF) signal is received by theantenna and is then filtered by the bandpass filter and amplified by the Low NoiseAmplifier (LNA). The intermediate frequency (IF) signal is given to Voltage GainAmplifier (VGA). The output of the VGA is then down converted and passedthrough an anti-aliasing filter. The signal is finally digitized by the ADC whichin our case is an SDM and processed by the DSP. The SNR we want to achieve is80db with a sampling frequency of 320MHz.

1.4 Design challenges 5

Figure 1.2. Heterodyne receiver architecture.

1.4 Design challengesThe design challenges of our design are as follows:

• The loop filter in the modulator with optimized coefficients.

• The circuit realization of the ADC and DAC .

• OTA design in the modulator.

• Timing, settling and internal noise in the integrator.

• Settling time and mismatch errors in the DAC.

• Power consumption minimization.

1.5 Work flowOur thesis work was performed according to the top down working methodology.

The design flow of the thesis work is given below :

• There were two structures of the SDM 5th order SDM and the 3rd orderSDM out of which we had to finalize one for our final design.

• Noise Transfer Function (NTF) optimization of our SDM.

• Coefficient calculation of the multipliers in our design.

• To make the SFG in precedence form.

• Matlab executable model from the system of equations in computable order.

6 Introduction

• Run the complete model of SDM in matlab and try to achieve the requiredSNDR.

• Find the maximum stable input range (MSIR) for which the SDM remainsstable, and this will also be done in matlab.

• Switched capacitor realization of the modulator from a given SFG descrip-tion.

• Timing extraction.

• Circuit level model in Cadence using 0.18µm technology.

• Dynamic range scaling.

• Settling error simulations.

• DC gain simulation.

• Capacitor size optimization from noise and area perspective.

• SDM noise budget.

• OTA design and compensation.

• Track and hold amplifier design.

• Switch design.

• Quantizer design.

• DAC design.

• Run the complete schematic model of SDM’s in Cadence and try to achievethe required SNDR.

• The circuit layout.

• Finally the tape out.

1.6 LimitationsDue to the lack of time the circuit realization of the Operational Transcon-

ductance Amplifier (OTA), optimization of the capacitors regarding to the areaperspective and noise optimization are not performed.

The decimation filter which filters the signal after the SDM is out of our scopeand finally the switches which we use in our switched capacitor network are ideal.

Chapter 2

Sigma-Delta Modulator

2.1 Basic concept of SDM

“According to Nyquist theory, minimum sampling frequency (fs) to avoid alias-ing should be twice the bandwidth of the signal to be digitized“. The ratio betweensampling frequency and Nyquist frequency is called Over-Sampling Ratio (OSR).By over-sampling, an analog signal with fewer number of bits per sample can beused compared to Nyquist rate ADC. ADCs operated at higher sampling ratethan the Nyquist rate also relaxes the specifications of the anti-aliasing filter thatis used after the SDM.

The name Sigma-Delta is used because it has a differentiator (delta) which takesthe difference of the incoming sample and the feed back sample. The higher theorder of the loop filter, the more accurate is the feed back sample. The basic blockof the SDM is shown in Fig 2.1 with the main building blocks which are, ADC,DAC, integrator and a subtractor.

Figure 2.1. First-order sigma-delta modulator with 3-bit quantizer.

7

8 Sigma-Delta Modulator

The digital output is fed back to the DAC and is subtracted from the inputsignal, the difference signal is accumulated in the integrator and then quantizedby the ADC. The purpose of the DAC is to maintain the average output of theintegrator near to the comparator reference level. By summing the error voltagethe integrator functions as a low pass filter to the input signal and high pass filterto the quantization noise.

2.2 OversamplingThe ratio between the sampling frequency and the nyquist frequency is called

the oversampling ratio, with higher OSR the signal band become smaller but theNTF more effective. The OSR thus can be defined as:

OSR = Fs

2Fin (2.1)

where Fs is the sampling frequency and Fin is the input signal frequency. Tounderstand the basic concept of oversampling, consider a signal that is sampled ata Fs, according to Nyquist theorum. The Fast Fourier Transform (FFT) analysiswhere we see a signal and noise extending from DC to Fs/2 shown in Fig 2.2 [3].

Figure 2.2. FFT analysis showing signal and quantization noise for a Nyquist rateADC.

2.3 Noise shaping 9

By increasing the sampling frequency Fs by a factor k, an FFT analysis showsthat the noise floor has dropped. SNR is the same as before but noise energy hasspread as shown in the Fig 2.3 [3]. In other words SNR is improved within theband of interest.

Figure 2.3. FFT analysis illustrating oversampling.

2.3 Noise shapingThe advantage of the oversampled ADC is that noise can be shaped at higher

frequencies by using oversampling as shown in Fig 2.4 [3].We can see that by noise shaping the noise energy within the signal band

is reduced. The quantization noise of the ADC is highpass filtered to yield lowquantization noise in the signal bandwidth (low frequencies), and noise at thehigh frequencies can be removed by the digital filters before the signal is furtherprocessed.

10 Sigma-Delta Modulator

Figure 2.4. FFT analysis showing shaped noise.

The basic advantages of using the SDM over other converters are that the SDMhas high speed, good resolution and integration and most important that theimplementation cost is low.

2.4 Limitations of SDMThe key principle of oversampling in SDM is to trade the bandwidth for the

resolution. To increase the signal frequency range one must increase the samplingfrequency which also means fast switching and more power. By using a high OSR,the number of quantization bits can be reduced to achieve good SNR. So here wecan conclude that there are different trade-offs on the different components in thesigma delta modulator. For low power ADC the accuracy can be traded off andfor high speed ADC and to get good SNR the over sampling will be high as wellas modulation order. More quantization means more power consumption.

Chapter 3

CRFB with feed forwardand feed back connections

3.1 MethodologyThe SDM used in the thesis project is described by the signal flow graph shown

in Fig 3.1.

Figure 3.1. Third-order SDM with interconnections.

This SFG shows the cascade of resonator with distributed feed-forward andfeed-back (CRFB) structure for the third-order modulator. Here, ’X’ is the inputsignal and ’Y’ is the output signal, ’Y’ is also the quantized version of the signal’U’.

For the third-order sigma delta modulator which is shown in Fig 3.1 [4] one canhave one or sveral delay elements at m0-m11. There are a lot of combinations for

11

12 CRFB with feed forward and feed back connections

the delay elements to be placed but one realizable placement of delays which weconcluded in our design is shown in Fig 3.2.

Figure 3.2. Third-order SDM with placement of delays.

In the third-order SDM we have one resonator block and one integrator block,the first integrator has a zero placement at Z = 1, and the resonator with thefeedback multiplier coefficient -G1 can be used for adjustable zero placement of thetransfer function. NTF is dependent on the coefficients ’Ai’ and ’Gi’ coefficients.Similarly the signal transfer function (STF) depends on the ’Ai’ , ’Bi’ and ’Gi’, ifthere is no feedback structure (Gi are set to zero) then a noise transfer function(NTF) will be highpass and the SDM will be a lowpass. In the SDM it is possibleto find the optimized coefficients for the NTF and the STF.

3.2 Matlab realization 13

3.2 Matlab realization3.2.1 Coefficient calculation for third-order SDM

From the structure shown in Fig 3.2 the system of equations are developedto calculate the NTF and STF. After that we optimize the NTF in Matlab, themagnitude response for the NTF and allpass STF are shown in Fig 3.3.

Figure 3.3. Magnitude response of the third-order SDM.

The multiplier coefficients for the third-order SDM used in the design are givenin Table 3.1.

Multplier CofficientsA0 -0.049827832780314A1 -0.243788089710989A2 -0.556021050126814G1 -0.007234446402774B0 0.049827832780314B1 0.243788089710989B2 0.556021050126814B3 1

Table 3.1. Multiplier cofficients for the third-order SDM.


The generalized structure of the SDM is shown in Fig3.4 [5] which has beendivided in three main parts which are, Loop filter, ADC and DAC.

Figure 3.4. General structure of a three bit quantizer sigma-delta modulator

The Loop filter here is a system having two inputs X and W therefore U in theZ domain can be express as

U(z) = L0(z)X(z) + L1(z)W (z) (3.1)

And similarly the quantizer can simply be modeled as an output plus an errorsource mathematically can be expressed as

Y (z) = U(z) + E(z) (3.2)

From the equations (3.1) and (3.2) we can write the output Y(z) as the com-bination of modulator input and quantization error.

Y (z) = X(z)STF (z) + E(z)NTF (z) (3.3)

3.2 Matlab realization 15

The NTF and STF can be realized as

NTF (z) = 11− L1(z) (3.4)

STF (z) = L0(z)1− L1(z) (3.5)

we have NTF and STF realization from the Matlab we can compute the L0and L1 as

L0 = STF (z)NTF (z) (3.6)

L1 = 1− 1NTF (z) (3.7)

The DAC and the ADC modules used are assumed to be ideal, it should benoted that the L0 and L1 should be large in the required range because a largeL1 reduces the NTF. L0 can be chosen such that STF approximates or equals tounity.This means that L0 and L1 should have poles in the required range, so theL0 and L1 have the same poles but different zero location, this can be shown inthe Fig 3.5.

Figure 3.5. Pole-zero plot for L0 and L1.


3.3 Matlab model of the third-order CRFB SDMThe signal flow graph of the SDM shown in Fig 3.2 was modeled in Matlab. For

the simulation of the SFG in Matlab the integrator blocks were modeled by anadder and a delay which is shown in Fig 3.6.

Figure 3.6. Integrator model for Matlab.

The precedence graph of the operations in computable order generated in Mat-lab is shown in Fig 3.7.

Figure 3.7. Precedence graph for third-order SDM.

3.3 Matlab model of the third-order CRFB SDM 17

From the graph we can find the equations in computable order. We simulatethe model of the SDM by applying a input sinusoid signal at the input’ X’ shownin Fig 3.2, the quantizer adds the quantization noise and the integrator acts as ahighpass filter to the noise, it shapes the noise towards the high frequencies. Theoutput spectrum of the third-order modulator with three bit quantization andOSR of 32 is shown in Fig 3.8.

Figure 3.8. Output spectrum of third-order SDM.

The high frequency quantization noise can be removed by a digital lowpassfilter without affecting the input signal. This lowpass filter is part of the deci-mation process and the digital filter at the output is used to get the maximumattenuation only for the higher frequency components keeping the analog inputsignal unaffected and the shaped noise is attenuated. Finally at the output fromthe filter, the noise is much flattened as shown in the Fig 3.9.


Figure 3.9. Filtered signal amplitude spectrum.

3.4 Maximum stable input rangeThe maximum stable input range is the range of the input signal for which the

output of the SDM remains stable within the specified SNDR range. For thispurpose the sigma-delta modulator of order three is simulated in Matlab for arange of amplitude versus a range of frequencies and SNDR for these ranges waschecked. After simulating the third-order SDM for MSIR we obtain the plot shownin Fig 3.10.

Figure 3.10. SNDR versus input signal amplitudes.

3.4 Maximum stable input range 19

Figure 3.11. MSIR (minimum of the maximum amplitudes).

Finally the MSIR is the minimum of the maximum amplitudes for a range offrequencies as shown in Fig 3.11.

Chapter 4

Clocking for SC SDM

4.1 Clock generation moduleThe non-inverting connections or the inverting connections of an SC integrator

can be used in the realization of the SC SDM. Such circuits use two phase clockswhich means two non-overlapping clocks P1 and P2 generated from the masterclock Clk and two additional trigger signals P1a and P2a are constructed out ofthe non-overlapping clocks, the timing diagram of the trigger signals along withthe non-overlapping clock is shown in the Fig 4.1.

Figure 4.1. Clock timing diagram

The two extra trigger signals P1a and P2a have the difference that these signalsgo low a little earlier than the clocks P1 and P2. P1a and P2a clocks are used toend the integration phase of the integrator. And also to reduce the charge injection

21

22 Clocking for SC SDM

in the circuit. The complete transistor level realization of the clock module wasimplemented and tested for the correct functionality. Fig 4.2 shows the design ofthe clock generator module [5].

Figure 4.2. Non-overlapping clock generator.

The four inverters in Fig 4.2 having a * sign are the one used for non-overlapadjustment. The width of these inverters can be varied for the adjustment of theclock duty cycles. The results obtained from the transistor level realization areshown in Fig 4.3.

4.1 Clock generation module 23

Figure 4.3. Clock generator schematics results.

Chapter 5

Switched-capacitorrealization of SDM

5.1 Realization from SFG to SC networkThe design in Fig 5.1 of the third-order SDM with CRFB has to be modeled with

a switched-capacitor network. For this the method of equivalence transformationsis used in order to have a full delay or a half delay at the input of every integrator.This means that the two integrators will never have to follow each other withoutsome delay in between them and also gives good settling time.

Figure 5.1. Third order SDM

The delay elements, one after the third integrator and the delay in the feedbackpath (marked as A in the Fig 4.1) are moved back and transformed into one delayelement at each input of the adder three. Then half of the delay element is moved

25

26 Switched-capacitor realization of SDM

from the output of the second integrator to the three inputs of the second adder.Now we have one and a half delay at the output of the first integrator, out ofwhich half delay element is moved back and now we have half delay elements ateach input of the adder one. The final transformed structure having half or a fulldelay at all integrator inputs used in the design is shown in Fig 5.2.

Figure 5.2. Third order SDM with full or half delay at the integrator input.

In the SDM model we can design inverting and non-inverting integrators, thegeneral SC integrator structure is shown in Fig 5.3.

Figure 5.3. A general integrator model.

5.1 Realization from SFG to SC network 27

Figure 5.4. Inverting and non inverting connection.

The switch with clock P2a acts as an integration switch and switches with clockP1 as a sampling switch. If node X of the the structure in Fig 5.3 is connected withnode Y of the Fig 5.4a, the integrator acts as a non-inverting integrator havinga transfer function given in equation (5.1). If the connection X of the structurein Fig 5.3 is connected to the node Z of the Fig 5.4b the integrator acts as aninverting integrator having a transfer function shown in equation (5.2)

V out(z) = C1

C2( Z−1

1− Z−1 )V in(z) (5.1)

V out(z) = −C1

C2( Z

−12

1− Z−1 )V in(z) (5.2)


The integrator in the SDM design having either a full or a half delay at the inputcan be clocked in different ways. For example we take the first integrator of theSDM as shown in Fig 5.2. As both of the inputs are inverting the structure of theswitched capacitor integrator having two inverting inputs with proper switchingof the clocks is shown in Fig 5.5.

Figure 5.5. Integrator with two inverting inputs.

The integrator realized in Fig 5.5 has two inverting inputs. The input controlledby the switches that have P2 as a trigger are conducting in integration phase ofthe integrator.By applying charge analysis and charge conservation methods, thetransfer function can be calculated as given in equation (5.3).

V out(z) = −C1

C3( Z

−12

1− Z−1 )V 1(z)− C2

C3( Z

−12

1− Z−1 )V 2(z) (5.3)

As both the inputs of the integrator are inverting, this results in a negative signat the output and an integration with a half unit delay.

5.1 Realization from SFG to SC network 29

We also flip the input signals Xin+ and Xin- in differential circuit in order tocompensate for the negative sign with voltage V1(z) in equation (5.3)

For a certain case when one of the inputs is inverting and the other is non-inverting the structure of the switched capacitor integrator having one invertingand one non inverting input with proper switching of the clocks is shown in Fig5.6.

Figure 5.6. Integrator having one inverting and one non inverting input.

The integrator realized in Fig 5.6 has one inverting and one non-inverting input.The input controlled by the switches that have P2 as a trigger are conducting inintegration phase of the integrator and the switches triggered by P1 are conductingin the sampling phase of the integrator. Similarly by applying charge analysis andcharge conservation methods, the transfer function can be calculated as given inequation (5.4).

V out(z) = C1

C3( Z−1

1− Z−1 )V 1(z)− C2

C3( Z

−12

1− Z−1 )V 2(z) (5.4)

As one of the inputs of the integrator is non-inverting, this results in a postivesign at the output and an integration with a full delay. Also a negative sign witha half unit delay because of the inverting input.

In the same way we can model the rest of the circuit having other combinationsof a full delay or a half delay at the input of the integrator. The fully differentialcircuit implementation of the third order SDM in Fig 4.2 is given in Fig 5.7.


Figure 5.7. Fully differential SC CRFB network

Chapter 6

OTA modeling for SDM

6.1 Small signal modelFor circuit realization of the sigma-delta modulator one needs to set the require-

ments of the OTA to be used in the switched-capacitor network. The importantparameters to be considered are phase margin, DC-gain, output range, slew-rateand unity gain bandwidth. To design a high performance SC network one needsthe optimization of the components. The integrator model used in the third-ordersigma-delta modulator is shown in Fig 6.1.

Figure 6.1. SC integrator with several inputs.

This realization of the integrator is mapped into a return ratio model [1] whichis shown in Fig 6.2.

31

32 OTA modeling for SDM

Figure 6.2. Return ratio model of the SC integrator.

The feedback factor beta is defined as

β = VopVout

= Ch

Cs+ Ch(6.1)

From Fig 6.1, the integrator having more inputs, the feed-back factor β is givenas

β = VopVout

=∑n

Ch

(Cn+ Ch) (6.2)

To obtain certain requirements of the OTA we use a two-pole model of theOTA as shown in Fig 6.3.

Figure 6.3. Two pole small signal model

6.1 Small signal model 33

The transfer function of the two pole model is given as

H(s) = V out(s)V in(s) = R1gm1R2gm2

(1 +R1C1s)(1 +R2C2s)(6.3)

The DC-gain A0 of the above model is given as

A0 = R1gm1R2gm2 (6.4)

The frequency of the first pole and the second poles are given as

ω1 = 1R1C1

(6.5)

ω2 = 1R2C2

(6.6)

The pole separation factor is defined as

γ = ω2ω1 (6.7)

Using equations (6.4), (6.5), (6.6), (6.7) we obtain

H(s) = V out(s)V in(s) = A0

(1 + s

ω1)(1 + s

γω1)(6.8)

γ can be calculated as

γ = 4(1 +A0β)1 + ( π

lnD)2

(6.9)

34 OTA modeling for SDM

In equation (6.9), D is the error bound which is the maximum settling errortolerated in the design so that the specific requirements on the SNR are met. Tofind the error bound, random error sources are introduced after every integratorin the SDM design as shown in Fig 6.4.

Figure 6.4. SFG with error sources used to simulate SNDR degradation due to incom-plete settling.

After introducing the error sources we need to know the maximum settlingerror tolerated in the design so that the requirements on the SNR are met, for thispurpose the SDM design is simulated in Matlab such that the SNR is not degradedbelow the desired values. The plots are obtained for SNDR limit versus the errorbound in order to get the value for the error bound which is shown in Fig 6.5.

Figure 6.5. SNDR vs Error bound.

6.1 Small signal model 35

From the simulations in Matlab the settling error bound D is 10−4 for thesystem having an SNDR of 80 db.

For finding the phase margin (PM) for minimum settling time (MST) as de-scribed in [1] with a specified feedback factor β and an error bound ’D’ is givenas

φMST = 90o − tan−1[ 1 + (πlnD)4β ] (6.10)

Chapter 7

Analog to digital converter

7.1 IntroductionOur real world is analog and the analog quantities can be weight, time voltage

etc. In the digital domain we have ones or zeros, the analog signals are convertedinto digital signals in proportion to its analog value by analog to digital converters(ADC). There are two main processes in the conversion. One is the samplingand other is the quantization. During sampling, the analog signal is divided in todiscrete time samples with a sampling frequency Fs. This sampled data is thenquantized to N discrete levels or 2N number of bits. By increasing the number ofbits more accuracy is achieved. If the sampling rate is equal to twice the bandwidthof the signal then these are called the Nyquist rate ADC’s. Oversampled ADC’swith a sampling rate more than the Nyquist rate can be used with fewer numberof bits per sample.

7.2 Resolution of ADCThe maximum number of discrete values an ADC can produce is the resolution

of an ADC. These values are usually in a binary form and the resolution of theADC is normally expressed in N bits with 2N number of different levels for theanalog input signal. The least significant bit is represented by VLSB = Vref

2N andVref is the input range of the analog signal. The larger the number of bits thehigher the number of levels and also the higher the resolution of the ADC.

37

38 Analog to digital converter

7.3 QuantizationAfter the sampling of the analog signal each sample is quantized to a discrete

value corresponding to the analog value of input signal. The quantization intro-duces an error which is called the quantization error.

7.4 ArchitectureThere are different types of ADC architectures depending on the different ap-

plications and requirements. Some of the architectures are flash ADC, successiveapproximation ADC, ramp compare ADC, pipelined ADC etc. The architecturewe use in our project is flash ADC with N bits resolution, 2N quantization levels,and 2N -1 comparators, where N = 3. The realization of the 3-bit quantizer isshown in Fig 7.1. The output produced by the comparator is thermometric coded.This thermometric code is converted into binary format as shown in Table 7.1 bya thermometric to binary decoder.

Figure 7.1. Three-bit flash ADC with decoder.

The problem with the ADC architecture is that as the number of bits increases,the number of comparators also increases rapidly and the therefore the hardware

7.5 Behavioral level design 39

increases as well so the number of bits is limited to 10 to avoid the huge powerconsumption and area of a chip. Another problem of using a large number ofcomparators is the large input capacitance so the circuits driving the ADC’s mustbe able to drive the large capacitive load. Therefore, the flash ADC is not suitablewhere one need high resolution.

Thermometer Binary0000000 0000000001 0010000011 0100000111 0110001111 1000011111 1010111111 1101111111 111

Table 7.1. Thermometer to binary code.

7.5 Behavioral level designThe ADC implemented in our design is a 3-bit flash ADC. The output of the

ADC is a thermometric coded value. At behavioral level ADC was implementedby using the VerilogA code.

7.6 Circuit realizationAs the ADC is clocked, we are using four clocks in our overall design ’P1’,

’P1a’, ’P2’, ’P2a’ which are derived from the clock generation module. The ADCis working on the rising edge of the clock P1. The input is differential and therange of the ADC is determined by the reference voltage Vref. The ADC consistof three submodules which are the comparator, the inverter chain, the SR-latch.

7.6.1 ComparatorThe comparator is a differential component which compares the differential input

to the comparator with the reference voltages as shown in Fig 7.2. The ADC workson the rising edge of the clock so, when the clock is low the pull down network isdisconnected from the output while the output nodes are equalized and when theclock goes high (in the evaluation mode) current starts to flow in the pull downnetwork. As one of the input is higher (Vinp with Vrefp, or Vinn with Vrefn orvise versa ) more current flows in those transistors. For example if Vinp is greater,more current flows in the transistors which is connected to V1 as shown in Fig 7.2and achieve its threshold level and switch.


Figure 7.2. Comparator schematics.

7.6.2 Inverter and SR-latchAt the output of the comparator the inverter chain (minimum of two inverters)

is used so that the output stabilizes either to one or zero. The SR-latch shownin Fig 7.3 is used because if the comparator produces some wrong value when thepull down network is disconnected (in equalization mode) the SR-latch then keepsthe previous value.

7.6 Circuit realization 41

Figure 7.3. The SR-latch.

7.6.3 Simulation results of ADCFor simulation purposes a test bench to check the functionality of the ADC was

developed which is shown in Fig 7.4.

Figure 7.4. Test bench for the ADC.


Here the ADC converts the two signals into thermometric code. Vrefn andVrefp are the reference level for the ADC. The thermometric code is convertedinto binary by thermometric encoder.

The results obtained from the schematic design of ADC are shown in Fig 7.5.

Figure 7.5. Simulation results of ADC schematic design.

Chapter 8

Digital to analog converter

8.1 IntroductionA digital-to-analog converter is a device which converts the digital signal (binary,

thermometric code etc.) to analog signal (voltage or current). The SDM loop, thesignal from the ADC which is thermometric code is converted into analog by theDAC, and is then fed back in the SDM loop. The DAC generates differentialoutput signals. The purpose of the feedback DAC is to maintain the averageoutput of the integrator near the comparator’s reference level.

8.2 Behavioral level designThe DAC implemented in our design is a switched-capacitor DAC [2]. At behav-

ioral level this is implemented by using the VerilogA code for the switches whilekeeping the schematic version for capacitors.

8.3 Circuit realizationThe schematic design of the DAC along with the clock signals was made at

transistor level. Fig 8.1 shows the the architecture of DAC element [2].

These DAC elements are connected together as shown in Fig 8.2 to get a fullydifferential output that is DACout+ and DACout-.

43

44 Digital to analog converter

Figure 8.1. Architecture of DAC element.

Figure 8.2. SC DAC structure for the SDM.

8.4 Simulation results 45

Figure 8.3. Test bench setup to check the functionality of the DAC

8.4 Simulation resultsFor simulation purposes a test bench to check the functionality of the DAC was

developed which shown in Fig 8.3.

Here two differential signals Vinn and Vinp are the input to the system the ADCconverts the two signals into thermometric code. The DAC converts this code tothe analog value. The range of the DAC is defined by the Vrefn Vrefp. Thecommon-mode voltage is defined by the Vcmo signal. The Dacoutp and Dacoutnare the two output ports from where we get the corresponding differential analogsignal out. The schematic design of the DAC having ideal switches was tested forcorrect functionality. The results of the simulation of the DAC are shown in Fig8.4.

46 Digital to analog converter

Figure 8.4. Simulations results from the schematic of DAC.

Chapter 9

Results

9.1 Results9.1.1 SC realization of the SDM structure

The thesis work explains the top down approach to model the the SDM stu-ucture, optimization of the coefficients of the NTF and the STF, optimizing themultiplier coefficients of the higher order resonator structure of the SDM’s andthen model the SFG in matlab and find the results.

In the thesis work we try to explain the step by step method of modeling SDMdesign with CRFB modulator structure to a fully differential switch capacitorrealization. The method to use inverting and non inverting SC integrator wereexplained. In the thesis work we also suggested the fully differential architecturesof the ADC, SC DAC and an on-chip clock generation module.

9.1.2 OTA modelingTo design a high performance and a good low power design of the SDM it is

very important to optimize the requirements for the OTA, as it is the main sourceof power consumption of the SDM design. Due to shortage of time we were notable to develop more test benches to fully optimize output range, slew rate andunity gain bandwidth for the OTA. In the thesis work we realized the OTA modelwith differential two-pole resistor capacitor model.

47

48 Results

9.2 Simulation results9.2.1 Matlab model results

The third-order design of the SDM in Fig 3.2 with optimized multiplier coeffi-cients was modeled in Matlab. Precedence graph was made made in order to getthe equations in computable order. The quantizer used in the design is a three-bitquantizer. The maximum stable input range which is the range of the input sig-nal for which the output of the SDM remains stable was determined which cameout to be 0.884. This value of the maximum input amplitude was used in SDMsimulation in Matlab. The output spectrum of the third-order modulator withthree-bit quantization and OSR of 32 is shown in 9.1.

Figure 9.1. Output spectrum of the third-order modulator.

Finally the signal to noise and distotion ratio (SNDR) and the effective numberof bits (ENOB) were calculated. The SNDR calculated for the third order SDMdesign was 81.4783dB and ENOB = 13.2422.

9.2 Simulation results 49

9.2.2 Cadence model resultsAfter the Matlab realization of the SDM, an executable model in cadence using

0.18 micron technology was made. In the first stage test benches of all the mainblocks like ADC, DAC, clock module were made and tested. The results showingthe correct functionality of every block have been shown in the previous chapters.

For simulation purposes a test bench to check the functionality of the completemodel of the SDM was developed which is shown in Fig 9.2.

Figure 9.2. Test bench for the third-order CRFB SDM.

Here two differential signals Vinn and Vinp, with input frequency of 5 MHz anda common mode level of Vcmo are the input to the third-order SDM. The outputfrom the integrators is fed to a 3-bit flash ADC which coverts from analog signalto its corresponding thermometer code. This code is converted into binary by theencoder. The DAC converts this code to the analog value and the range of theDAC is defined by the Vrefn, Vrefp, and the common mode voltage is defined bythe Vcmo signal. The out from the DAC is fed back to the SDM loop. The digitalouput from the ADC is stored in a file through a File write block. This data is readinto the Matlab where one can find the SNDR and ENOB. The output spectrumof the signal read in Matlab is shown in 9.3.

50 Results

Figure 9.3. Simulation results from cadence model.

The SNDR calculated for the third-order SDM design with an input signal of 5MHz and a sampling frequency of 320 MHz, having OSR=32 was 84.7183dB andENOB = 13.7804.

Bibliography

[1] T.Fiez Chilakapati. Settling time considerations for sc integrators. Circuit andSystems Vol. 1, 31pp. 492 - 495 31.

[2] Ian Galton. Delta- sigma data convertion in wireless transceivers. Microwavetheory and techniques, vol. 50 1.

[3] MAXIM. Delta, a/d and d/a conversion/sampling circuits.

[4] Krister Berglund Oskar Matteusson. On the realization of switch capacitorintegrators for sigma delta modulators.

[5] G. Temes R. Schreier. Understanding Delta-Sigma Data Converters.

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