Real-Time Systems - Purdue Universityrvoyles/Classes/RealTime...New Bus Paradigm Serial Buses: USB...

Real-Time Systems

Basic Terminology & Computer

Architecture

Richard Voyles

School of Engineering Technology

Basic Computer Architecture

• Three Basic Components: CPU,

Memory, I/O

CPU Memory

I/O

Data andAddressBuses

(control,

Data andAddressBuses

(control,

Printers, Modems, Secondary Storage (disks, tapes, etc),Analog Converters, Motor Controllers, Displays, ...

Main Memory

power)

power)

Memory

Optional Additional MemoryStores such as off-boardmemory, multiprocessorshared memory, etc.

Memory Access

(Bus Transfer Mechanism)

Real-Time & Embedded Systems, Purdue University

Address

Data

Read/Write

Addr Enable

CPU Memory

Addr bus, R/W

AEN

Data bus

DST

Handshake

CPU Operation

• Fetch-

Execute

Cycle

• Macrocode

vs.

Microcode


But Where’s the Memory??


Memory is the “Black Box” of Computing

“If the ‘black box’ always survives a crash, why can’t we make

the entire plane the same way we make the black box?!”


So We Need to Talk About

Types of Memory….• Read Only Memory (ROM)

– ROM - mask programmed (factory - obsolete)

– PROM - Programmable ROM (one-time or multi-shot)

• EEPROM (Non-Volatile Random Access Memory NVRAM)

• FLASH (Non-Volatile Random Access Memory NVRAM)

– EPROM - Erasable PROM (UV light - obsolete)

• Random-Access Memory (RAM)

– Static RAM (SRAM)

– Dynamic RAM (DRAM, includes DDR-SDRAM, etc)


Memory Characteristics

Type Speed Cost Size Power Volatility

ROM J J JJJ NV

EPROM J LLL J NV

SRAM JJJ LL L JJ V

DRAM JJ JJJ JJJ J VR

EEPROM LL L NV

Flash L L NV

• NV = non-volatile, V = volatile, VR = volatile with

refresh

• SDRAM = Synchronous DRAM (not SRAM)


Levels of the Memory Hierarchy

CPU Registers100s Bytes<2 ns

CacheK Bytes1 - 10 ns$0.5 – 2 / KB

Main MemoryM -> G Bytes10ns-1us$.5 – 2.0 / MB

DiskG->T Bytesms$2-5 / GB

CapacityAccess TimeCost

Cloudinfinitesec-min$1-4 / 10GB

Registers

Cache

Memory

Disk (Spinning or SSD)

Backup/Cloud (CD-ROM, DVD, …)

Instr. Operands

Blocks

Pages

Files

StagingXfer Unit

prog./compiler1-8 bytes

cache cntl8-128 bytes

OS4K-64K bytes

user/operatorMbytes

Upper Level

Lower Level

faster

Larger

But, How Does Cache Help at All??

Registers

Cache

Memory

If the CPU needs a value from memory, it still has to read from memory!!• Spatial Locality• Temporal Locality

Virtual Memory

• Main memory can act as a cache for the secondary storage (disk)

• Advantages:– illusion of having more physical memory– program relocation – protection

Physical addresses

Disk addresses

Virtual addresses

Address translation


Basic Issues in Virtual Memory System Designsize of information blocks that are transferred from

secondary to main storage (M)

block of information brought into M, and M is full, then some regionof M must be released to make room for the new block -->replacement policy

which region of M is to hold the new block --> placement policy

missing item fetched from secondary memory only on the occurrenceof a fault --> demand load policy

Paging Organization

virtual and physical address space partitioned into blocks of equal size

page framespages

pages

reg

cachemem disk

frame

Pages: virtual memory blocks

• Page faults: the data is not in memory, retrieve it from disk– huge miss penalty, thus pages should be fairly large (e.g., 4KB)– reducing page faults is important (LRU is worth the price)– can handle the faults in software instead of hardware– using write-through is too expensive so we use write-back

3 2 1 011 10 9 815 14 13 1231 30 29 28 27

Page offsetVirtual page number

Virtual address

3 2 1 011 10 9 815 14 13 1229 28 27

Page offsetPhysical page number

Physical address

Translation

•Must Translate the Virtual Address into a Physical AddressAddress (showing bit positions)

20 10

Byteoffset

Valid Tag DataIndex

0

1

2

1021

1022

1023

Tag

Index

Hit Data

20 32

3130 131211 21 0


Page Tables

Physical memory

Disk storage

Valid

1

1

1

1

0

1

1

0

1

1

0

1

Page table

Virtual page

number

Physical page ordisk address


Virtual Address and a Cache

CPUTrans-

lationCache

Main

Memory

VA PA miss

hit

data

It takes an extra memory access to translate VA to PA

This makes cache access very expensive, and this is the "innermostloop" that you want to go as fast as possible

ASIDE: Why access cache with PA at all? VA caches have a problem!synonym / alias problem: two different virtual addresses map to same physical address => two different cache entries holding data forthe same physical address!

for update: must update all cache entries with samephysical address or memory becomes inconsistent

determining this requires significant hardware, essentially anassociative lookup on the physical address tags to see if you have multiple hits; or

software enforced alias boundary: same lsb of VA &PA > cache size

Interrupts

• An Interrupt is a hardware signal that

initiates an event.

• An event, or change of flow-of-control, is any

occurence that causes the program counter

to change nonsequentially.

• Synchronous Events are predictable

changes in flow

• Asynchronous Events are not predictable.

– Timer tick is not predictable (asynchronous)


CPU Operation

• Fetch-

Execute

Cycle

• Interrupts &

Changes of

Flow of

Control


But Where’s the Memory??


Lab H/W: RecoNode


Bus Architectures

CPUBus

Interface

Bus

Interface

CPU

Bus-Specific

Signals

Processor Side I/O Side

Processor Side I/O Side

FPGA

Converter

Conventional Bus

Morphing Bus

Sensor/

Device

Device-Specific

Signals

Data

Control

New Bus Paradigm

Serial Buses:USBCanBusRS485

Parallel Buses:ISAPCIVMEbus

Multi-Serial:PCIexpress

Multi-Parallel:

Tim

e M

ult

iple

xin

g

Not Multiplexed Multiplexed

Mu

ltip

lexe

dN

ot

Mu

ltip

lexe

d

Space Multiplexing

Morphing

Bus


Real-Time Systems - Purdue Universityrvoyles/Classes/RealTime...New Bus Paradigm Serial Buses: USB...

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