Readout of the ATLAS Liquid Argon Calorimeters John Parsons Nevis Labs, Columbia University...

Readout of theATLAS Liquid Argon

Calorimeters

John ParsonsNevis Labs, Columbia University

Representing the ATLAS LAr Collaboration

ATLAS

J. Parsons, Siena, October 2002

LHC : pp collisions @ √s = 14 TeVDesign Luminosity : 1034 cm-2 s-1

Liquid Argon Calorimeters

Barrel EM ~ 110208 channelsEnd Cap EM ~ 63744HEC ~ 5888FCAL ~ 3584In total ~ 190 K channels


read out 190k channels of calorimeter dynamic range 16 bits measure signals at bunch crossing frequency of 40 MHz (ie. every 25 ns) store signals during L1 trigger latency of up to 2.5 s (100 bunch crossings) digitize and read out 5 samples/channel at a max. L1 rate of 100 kHz

measure deposited energies with resolution < 0.25% measure times of energy depositions with resolution << 25 ns

high density (128 channels per board) low power ( 0.8 W/channel) high reliability over expected lifetime of > 10 years must tolerate expected radiation levels (10 yrs LHC, no safety factors) of:

TID 5 kRad NIEL 1.6E12 n/cm2 (1 MeV eq.) SEU 7.7E11 h/cm2 (> 20 MeV)

Requirements of ATLAS LAr Frontend Crate Electronics


Overview of ATLAS Liquid Argon (LAr) Calorimeter Readout


ATLAS LAr Frontend Crate Electronics Overview

On-detector electronics Boards tested functionally on Mod 0 ATLAS rad-tol boards being finalized

Calibration :116 boards @ 128 ch

Front End Board (FEB) :1524 boards @ 128 ch

Controller :116 boards

Tower builder (TBB) :120 boards @ 32 ch


Approx. 6000 channels of full functionality “Module 0” boards were developed and produced

50 FEB , 12 calib, 2 TBB Provided verification of electronics design concepts Have been operating reliably in testbeam runs withModule 0 and production calorimeter runs at CERN for past several years Performance meets or exceed ATLAS specifications(for sample results, see other ATLAS LAr talks at this conference)

Due to schedule, Mod 0 electronics were developedwithout requiring radiation tolerance

the main task remaining in the development of the final ATLAS boards was to radiation harden the designs, and in particular to replace several FPGAs and other COTs with custom rad-tol ICs

Module 0 Electronics Experience


Over 10 yrs at design luminosity,

on-detector electronics must tolerate

significant exposure to ionizing

rad’n, neutrons, and other hadrons TID 5 kRad NIEL 1.6E12 n/cm2 (1 MeV eq.) SEU 7.7E11 h/cm2 (> 20 MeV)

Rad’n qualification requires extensive

testing of components, including large

SAFETY FACTORS due to uncertainties

in simulation, possible low dose rate effects, and possible lot-to-lot variations Combined safety factors can be as high as 70 (!!)

In addition to total damage, need to pay careful attention to possible single event upsets (SEU) of digital logic

Radiation Tolerance Requirements

BarrelFEC

EndcapFEC


Reduce/avoid use of COTs

Developed 12 different custom ASICs usingspecialized rad-tol processes:

9 DMILL chips 3 DSM chips (using rad-tol standard cell library)

Paid careful attention in ASIC designto “harden” design against SEU.

Triple-redundancy and majorityvoting techniques for critical registers Parameter storage with Hammingcode and EDC logiceg. DSM SCA Controller reducesreq’d FEB Reset rate by factor ~ 70(residual rate < 1 FEB/hr in whole system)

Radiation qualification process requiresTESTING, TESTING, TESTING!!

Radiation Hardening the ATLAS LAr Readout


Provide redundant optical links to off-detectorcontrol electronics for TTC (trigger/timing) andSPAC (serial control fordownloading/reading backconfiguration parameters)

Provide (bussed) SPAC and (point-to-point) TTCsignals to rest of boards in ½ crate

Prototype being developed now; to be delivered end Oct. for beginning of set up of system crate test

Controller Board Overview


Generate 0.1% precision calibration pulses

Rise time < 1 ns

Current pulse amplitude from 200 nA up to 10 mA

Delay programmable from 0 to 24 ns in 1 ns steps

Number of current pulsers per CALIB board is 128

Calibration Board Overview


Overview of Main CALIB Components

128Outputsignals

1 TTCRx

4 pos. Vreg and 1 (non-essential?) neg. Vreg

128 opamp10 μV offset

6 CALogic 1 SPAC

5 Ώ0.1%

50 Ώ0.1% 10 uH128 HF switch 2 delay16 driver

1 DAC16 bits

VDAC

Enable

CMD

IDAC

Spac

TTC

DMILL AMS COTS


8 Channel CALIB Prototype

Include digital control plus analog chain for 8 channels

3 boards received in April 02

Design of full-sized 128 channel board is underway; delivery by Nov.

Opamps & switch DAC

CALlogic

TTCRx

Delay

SPAC2

8 outputs


functionality includes: receive input signals from calorimeter amplify and shape them store signals in analog form using SCA while awaiting L1 trigger digitize signals for triggered events transmit output data bit-serially over optical link off detector provide analog sums to L1 trigger sum tree

Frontend Board OverviewFrontend Board Overview


SCA Analog Memory

Provides analog signal storage during L1 latency of upto 2.5 s (100 bunch crossings) 144 cell pipeline, to give multi-event derandomizing buffer Design developed in rad-soft technology, and then successfully migrated to rad-hard DMILL version Some performance numbers:

• Signal range 3.8V• Noise 300 V• Fixed Pattern Noise 190 V• DC Dynamic range 13.3 bits• Cell-to-Cell DC gain spread < 0.02% • Chan-to-chan offset spread 10mV RMS• Voltage droop < 3mV/ms

To automatically test > 50000 SCA chips,a robotic test station was developed

SCA tests underway (yield ~ 70%); finish by end 2002 Same setup already used to test > 50000 Shaper chips

J. Parsons, Siena, October 2002 10 different custom rad-tol ASICs, relatively few COTs

Overview of main FEB components

32 SCA 16 ADC 8 GainSel

1 GLink1 Config.2 SCAC

1 SPAC

1 MUX32 Shaper

1 TTCRx7 CLKFO14 pos. Vregs+6 neg. Vregs

2 LSB

32 0T

128input

signals

1 fiber to RODAnalog

sumsto TBB

DMILL

DSM

AMS

COTS

2 DCU

TTC,SPACsignals


128 channels/FEB components on both

sides to achieve density

Need neg. Vregs before launching 20 FEB pre-production for system crate test, last major milestone before beginning production

FEB Prototype

Shapers

SCAsADCs

O/P optical link

SPAC

Preamps

GainSel

SCA Controllers

TTCRx

128 I/P signals


one GLink output link per FEB, with rate of 1.6 Gbps

Total raw data rate from 1524 LAr FEBs 2.4 Tera bps

FEB Optical Links

1.6 Gb/s


Overview of ATLAS Liquid Argon (LAr) Calorimeter Readout


Readout Driver (ROD) Overview

Process raw data in real time @ 100 kHz L1 rate: Apply calibration constants From 5 time samples per channel, calculate

(via optimal filtering):• Deposited energy• Time of energy deposition• Pulseshape quality (2)

Format processed data and transmit to L2/DAQ Perform histogramming + monitoring of raw data

ROD Demo program allowedsuccessful prototyping of severaldifferent commercial DSPs

selected 600 MHz TI 6414 ROD prototype being finalized DSP on plug-in daughter boardallows “staging” of ROD system for initial running (at lower L1 rate) by originally producing only 50% of the processing power


Some 6414 ROD Demonstrator Results

600 MHz TI 6414 can process 128 channels (one FEB) in less than 10 s

Independent DMAs for I/P and O/P streams provideenough I/O bandwidth withoutsignificant impact on processing

DSP memory sufficient tostore “reasonable” set of histo’s

Due to 6414 cache structure,simulator gives overly optimistic results

Design of final Double Processing Unit (PU) with two 6414 DSPs, and of ROD Motherboard incorporating 4 Double PUs, is underway Prototypes should be available in early 2003


Summary

Radiation hardening the Module 0 electronics designs has required a VERY significant effort over several years development of a large number of custom ASICs extensive irradiation test programs for both custom ASICs and COTs All components are in, or will move into, production by the end of 2002

Final prototypes of all front end electronics boards will be available by the end of 2002 We have suffered a significant delay due to continued problems in the

development of rad-tol negative Vregs (hopefully resolved very soon) During 2003, a “system crate test” of ~2500 channels will be performed, as the

last remaining major milestone before moving to production

Prototypes of ROD and other off-detector electronics will be available by Spring 2003

Testbeam in 2004 could provide operating experience with final electronics

Final electronics installation in ATLAS pit scheduled to begin Nov. 2004

Readout of the ATLAS Liquid Argon Calorimeters John Parsons Nevis Labs, Columbia University...

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