Reactor wall plasma cleaning processes after InP etching...
Transcript of Reactor wall plasma cleaning processes after InP etching...
Reactor wall plasma cleaning processes after InP etching in Cl 2/CH4/Ar ICP
discharge
R. Chanson a, E. Pargon a, M. Darnon a, C. Petit Etienne a, S. David a, M. Fouchier a, B. Glueck b, P. Brianceau b, S. Barnola b
a Univ. Grenoble Alpes, CNRS, LTM, CEA-Leti
b CEA/LETI
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DBR Gain region
1. Fiber couplingInP
Si waveguide
2. Edge coupling
� Hybrid silicon integration combines:- Silicon and derived components to elaboratewaveguides, filter or photodetector
- III-V materials for light emitter
III-V Laser source
SOI wafer
III-V integrated by molecular wafer bonding
Hybrid photonic integrated circuit (PIC)
� Photonic integration is the key to reduce size,increase functionality and reduce cost ofphotonic devices
Martijn J. R. Heck, SPIE Newsroom 2013
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Plasma etching of III-V materials
� Process requirements:
III-V Chloride Fluoride Hydride
Ga Ga2Cl6, 201°C GaF3, 950°C [GaH3]2, 0°C
In InCl3, 583°C InF3, >1200°C InH, N/A
P PCl3, 76°C PF3, -102°C PH3, -88°C
As AsCl3, 130°C AsF3, 63°C AsH3, -63°C
� Inspection of boiling points for chemistry suitability:
� F unreactive with group III� Cl chemistry suitable for GaAsP system� Low volatility of InClx compounds
http://www.webelements.com
1. High etch rates2. Anisotropic sidewalls3. Selectivity III-V vs SiN hard mask and SiO2 box4. Minimized surface and sidewalls roughness5. Compatible with CMOS technology (contamination)
→ Ar/ Cl2/CH4@170°C
Reactiveetchant
Passivativespecies
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III-V plasma patterning results
� Etch rates acceptable: 472nm/min� III/V SiN selectivity: 14 � Anisotropy : 86°� Surface and sidewalls roughness OK
Ar/ Cl2/CH4@170°C in ICP (AP from AMAT)
Courtesy of P. Brianceau, CEA/LETI
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Reactor wall contamination during plasma etching
InP
Plasma
Etched by-products
InP
Mask Mask
Reactor wallsAl2O3
Passivation layer
Etched by-products redepositionEtched surface
Wall Deposited layer
� Formation of coatings on Al2O3 chamber walls changes the plasma chemistry�Causes process drift, wafer to wafer irreproducibility
@170°C
@60-80°C
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Changes in reactor walls conditions = process drift s
Today's strategy to get a reproducible process: Clean the reactor between wafers
Today’s strategy for process reproducibility
clean Al 2O3chamber Deposit
Etching
clean Al 2O3chamber
Reactor plasma clean
Next wafer
� Aim of this study� Characterize the deposits formed on the reactor wall� Propose plasma cleaning strategies
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Analyses of chamber walls coatings
Chemical nature and thickness of the chamber wall coatings
Quasi in-situXPS analysis
“Floating sample technique”: An electrically floating Al2O3 sample is used to simulate the reactor wall conditions
Reactor wallsurface
≡Al2O3floating sample
RF biasing
Ion energy ~ 15 eV : deposition
SiO2 wafer@170°C
Ion energy > 100 eV : etching
Al2O3 chamber walls@80°CRF coil (ICP reactor)
Air gap
O. Joubert, J. Vac. Sci. Technol. A 22, 553 2004.
InP wafer
N.B. Use of temperature stick to monitor floating sample temperature
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Experimental set-up
� Substrates: 2 ” InP wafer on a 200mm diameter SiO2 carrier wafer
DPS
DPS +
XPS
MERIE
Load locks
Transfer chamber
DPS
DPS +
XPS
MERIE
Load locks
Transfer chamber
ICP with hot cathod @ 170°C→InP etching
ICP with ESC @ 50°C→ Reactor wall cleaningexperiment
XPS: quasi in situ characterization of the coating deposit and its plasma cleaning
2’’ InP wafer
SiO2 wafer
� Etching and characterization experiments: 200 mm plasma etching plateform from AMAT
Floating sample
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� No phosporine detected
� Deposition of a mixed SiOCl-CCl layer with encapsulated InClx residues (8%)
� No significant change after air exposure
XPSChemical composition of the deposit
formed on the Al2O3 sample
Characterization of the deposit on the reactor wall
FIB-SEMMorphological analyses of the deposit
Top view
Pt
Deposition
Al2O3
Si Substrate
100nm
Cross section
� Deposit thickness rangingfrom 50 to 100nm
� Inhomogeneous rough surface
0
20
40
60
80
100
In 6%
Ato
mic
con
cent
ratio
n (%
)
C 52%
F 3%
O 17%
Cl 15%
Si 6%Si 10%
C 31%
F 5%
O 13%
In 8%
Cl 32%
O 44%
F 5%
C 16%
Al 35%
Al2O3sample
After InPetching (in-situ)
After InPetching (ex-situ)
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Chamber walls cleaning strategies
Al2O3 sample coated with the deposit are patched on a carrier wafer and exposed to cleaning plasma in DPS
RF biasingSiO2carrier wafer
Al2O3 chamber walls@80°CRF coil (ICP reactor)
Sample patched on the carrier wafer with Fomblin: - sample temperature regulated by ESC temperature
Sample elevated with Kapton rolls: - no regulation of temperature- temperature controlled with stickers
Quasi in-situXPS analysis
Al2O3 sample
T >100°CT between 60-90°C
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Chamber walls cleaning strategiesPreliminary tests with typical plasma cleaning strategy-Sample temperature >140°C
After InPetching
Clean SF6/O21 min
Clean Cl2
10 min
Clean HBr
10 min
� Clean SF6/O2: removal of SiOCCl matrix but fluorination of Al and In
0
20
40
60
80
100
Al 27%Al 13%
In 18%
In 23%In 9%
C
SiSi 12%
Si 4%
Si 11%
O 17%O 6%
O 38%
F 13%
F 61%
Cl 28% Cl 62%
C 11%C 31%
Ato
mic
con
cent
ratio
n (%
)Gas: 100sccmPressure: 5-10mTSource: 800WBias: 0W
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Chamber walls cleaning strategiesPreliminary tests with typical plasma cleaning strategy-Sample temperature >140°C
After InPetching
Clean SF6/O21 min
Clean Cl2
10 min
Clean HBr
10 min
� Clean Cl2: carbon is removed, Si slightly removed but In remains
� Clean SF6/O2: removal of SiOCCl matrix but fluorination of Al and In
0
20
40
60
80
100
Al 27%Al 13%
In 18%
In 23%In 9%
C
SiSi 12%
Si 4%
Si 11%
O 17%O 6%
O 38%
F 13%
F 61%
Cl 28% Cl 62%
C 11%C 31%
Ato
mic
con
cent
ratio
n (%
)Gas: 100sccmPressure: 5-10mTSource: 800WBias: 0W
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Chamber walls cleaning strategiesPreliminary tests with typical plasma cleaning strategy-Sample temperature >140°C
After InPetching
Clean SF6/O21 min
Clean Cl2
10 min
Clean HBr
10 min
� Clean Cl2: carbon is removed, Si slightly removed but In remains
� Clean HBr: In is removed
� Clean SF6/O2: removal of SiOCCl matrix but fluorination of Al and In
0
20
40
60
80
100
Al 27%Al 13%
In 18%
In 23%In 9%
C
SiSi 12%
Si 4%
Si 11%
O 17%O 6%
O 38%
F 13%
F 61%
Cl 28% Cl 62%
C 11%C 31%
Ato
mic
con
cent
ratio
n (%
)Gas: 100sccmPressure: 5-10mTSource: 800WBias: 0W
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0
20
40
60
80
100F 10%
F 37%
Cl 20%
In 5%In 12%
Si 12%
O 38%
C 11%
Al 14%Al 27%
Al 4%In 9%
Si 6%
Si 3%Si 11%
O 17%O 35%
O 33%
F 13%
Cl 28%Br 10%
C 26%C 31%
Ato
mic
con
cent
ratio
n (%
)
Clean HBr @70°C
10min
After InPetching
Clean HBr @140°C
10min
Clean HBr @90°C
10min
HBr plasma cleaning process: impact of temperature
90°C
140°C
Patchedsample
Surelevatedsample
Patchedsample
At the reactor wall temperature of 80-90°C, In residues still present
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Dual step plasma cleaning process
A dual step cleaning process is efficient to restore the reactor wall:Clean HBr@140°C remove InClx compounds followed by clean
SF6/O2@80°C to remove Si and C based compounds
0
20
40
60
80
100
Al 26%Al 5%In 9%C
Si 2%
Si 17%
Si 11%
O 17%
O 35%
O 28%
F 53%
Cl 28%
Br 10%
C 30%C 31%
Ato
mic
con
cent
ratio
n (%
)
Clean SF6/O2@80°C
1 min
Clean HBr @140°C
5 min
After InPetching
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Conclusion
� Patterning of InP/InGaAs/InGaASP heterostructures can be achieved in Ar/Cl2/CH4plasma with assistance of temperature
� During InP etching, a deposit composed of InClx residues encapsulated in a SiOCCl matrix is formed on the reactor wall.
� HBr plasma can be used to remove Indium residues from the reactor wall but for a complete efficiency, reactor wall should be heated above 100°C
� A dual step plasma cleaning process is recommended to restore the reactor wallafter InP etching : HBr plasma@140°C followed by SF6/O2 plasma
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Acknowledgement to the NANOELEC program for
supporting this work
Questions?