Ravindra Mehta_Resume
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Ravindra Mehta [email protected] 1102 S Abel St., #212 Milpitas, CA, 95035 (M) 201-885- 0560 Education M.S. Materials Engineering, July, 2016 San Jose State University, San Jose, California Bachelors of Engineering in Metallurgy Engineering, June, 2012 Gujarat Technological University, Gujarat, India Skills: RCA cleaning, four points probe, SEM Vision (G6), stylus profilometer, SPC, JMP, Minitab, DOE, data analysis, UV-Vis spectrophotometer, spin coating, aligner, wet and plasma etch, tamar scan, axiospeed, nanospec, PVD-sputter and thermal evaporation, die picking and inspection Employment Experience: Sep, 2016- Dec, 2016: Process Tech at Applied Materials Learnt the hardware control of the deposition tool, dealt with defects in the deposition process, performed adder calculations for imaging defects and performed SEM (SEMVision) and measured particles on KLA Tencor SP3 and SP5 June, 2015- August, 2015: Process Engineer intern at Silicon Microstructures, Milpitas ● Worked in a class 100 clean room of MEMS pressure sensors manufacturing to analyze particle removal efficiency of Isopropyl alcohol vapor [IPA] and bake dryers from surface of the wafers measured using surfscan ● Measured etch depth and total thickness variation of diaphragm using Tamar scan and axiospeed, performed wet KOH etch to build diaphragms, measured oxide and resist thickness on nanospec, performed spin coating of resist using SVG track coater and performed PR stripping ● Worked of aligner, performed tool capability test for oxidation, spin coater, and sputtering by Statistical Process Control method using minitab, performed plasma etch using tegal plasma etch tool to determine the etch rates of photoresist and silicon. ● Studied influence of power on etch rates, measured aluminum step height using alpha step profilometer, measured sheet resistance of film to determine contact resistance using four points probe ● Worked on die picking tool and performed die inspection to eliminate broken dies from the packaging, removed contaminants by RCA clean of wafers prior to diffusion
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Transcript of Ravindra Mehta_Resume
Ravindra [email protected]
1102 S Abel St., #212Milpitas, CA, 95035 (M) 201-885-0560
EducationM.S. Materials Engineering, July, 2016San Jose State University, San Jose, California
Bachelors of Engineering in Metallurgy Engineering, June, 2012Gujarat Technological University, Gujarat, India
Skills: RCA cleaning, four points probe, SEM Vision (G6), stylus profilometer, SPC, JMP, Minitab, DOE, data analysis, UV-Vis spectrophotometer, spin coating, aligner, wet and plasma etch, tamar scan, axiospeed, nanospec, PVD-sputter and thermal evaporation, die picking and inspection
Employment Experience:Sep, 2016- Dec, 2016: Process Tech at Applied MaterialsLearnt the hardware control of the deposition tool, dealt with defects in the deposition process, performed adder calculations for imaging defects and performed SEM (SEMVision) and measured particles on KLA Tencor SP3 and SP5
June, 2015- August, 2015: Process Engineer intern at Silicon Microstructures, Milpitas ● Worked in a class 100 clean room of MEMS pressure sensors manufacturing to analyze particle
removal efficiency of Isopropyl alcohol vapor [IPA] and bake dryers from surface of the wafers measured using surfscan
● Measured etch depth and total thickness variation of diaphragm using Tamar scan and axiospeed, performed wet KOH etch to build diaphragms, measured oxide and resist thickness on nanospec, performed spin coating of resist using SVG track coater and performed PR stripping
● Worked of aligner, performed tool capability test for oxidation, spin coater, and sputtering by Statistical Process Control method using minitab, performed plasma etch using tegal plasma etch tool to determine the etch rates of photoresist and silicon.
● Studied influence of power on etch rates, measured aluminum step height using alpha step profilometer, measured sheet resistance of film to determine contact resistance using four points probe
● Worked on die picking tool and performed die inspection to eliminate broken dies from the packaging, removed contaminants by RCA clean of wafers prior to diffusion
January, 2014- February, 2014: Teaching Assistant at San Jose State University Taught the laboratory section for the course “Introduction to Materials Engineering”. Taught to perform related experiments, graded quizzes and worksheets.
September, 2013 - December, 2013: Grader at San Jose State University Graded Home Work Assignments for the course “Structure-Property Relations in Solids”
Laboratory Experience Fabricated CMOS devices at the Microelectronics Process Engineering lab by RCA cleaning, oxidation, diffusion, photolithography, well implantation, wet and dry etching, and thin film deposition by PVD- thermal evaporation and sputtering, acquainted using four points probe, profilometer measurement techniques, and AFM. Learned and performed DOE and statistical analysis in JMP. Performed sample preparation and microstructural characterization of metals
August, 2015 – May, 2016: Master’s Project: Study of transparency and conductivity of ITO thin films with respect to annealing temperature deposited by sol-gel spin coating Prepared solution using InCl3 and SnCl2.2H2O as precursors and methanol as solvent, optimized spin coating speed and time, annealed the films between 300-600 °C, measured film thickness and studied variation in resistivity and transparency of the films with annealing temperature
