Rasit Onur TopalogluUniversity of California San Diego

Computer Science and Engineering Department Ph.D. candidate

www.cse.ucsd.edu/~rtopalog

“Location Based On-Chip Variation”

•Process model

•Motivation

•On-chip variation model

•Validation methodology

Outline

•Experimental Results

•Conclusions

Motivation

•Process variations, if not considered properly, may cause chips to fail or prone designs to be impossible to attain a spec.

•Currently static timing analysis tools neglect cell locationsCell locations contain a valuable systematic information

Increases design time and reduces yield

Oxide Distribution on Wafer

Ref: Intel Technology Journal, Vol. 06, Issue 2, May 2002

30cm wafer, 0.13m, SEM

Oxide distribution seems to be circular & continuous

Process and OCV Models

Modeling of Process Variations : “Volcano Model”

•Effects such as oxide variation, threshold voltage variation, lumped as cell speed variation

Cell speed

Distance from center Distance from center

Cell speed

Equ-speed circles on wafer

•Linearly increasing or decreasing cell speeds along radius

•Variation curves are circular

1.2

1.15

1.1

1.05

Modeling of On-chip Variation : “Angular Model”

•Cell speeds will be effected depending on angle wrt wafer center

Assumption : max. on-chip speed variation

•On-chip variation available as std. dev. only

•Since chips are small, circle arcs approximated to be straight lines

1

2 1

•Chip may fall anywhere on wafer

-model

-real

Process curves on chip

chip1

chip2

C

Location of Chip Matters

•Equ-lines are taken to be parallel to each other and normal to the linethat connects wafer center and closest corner of chip

C

Calculation of Speed Variation

BA

2/*// BBBABA

|A//B| / |B| ratio is used to find process variation effect at location p

p

•Multiply this ratio by maximum on-chip variation to find cell speed

Hypothesis I : Chips at Same Angle

•If process variation not linearly effecting cell speeds, maximum on-chip variations for chipA and chipB will differ

•Chip2 has more variation, simulating for it is satisfactory

if equ-speed circles not evenly distributed on wafer:

AB

1.2

1.15

1.051.1

Hypothesis II : “Dominant Locations” on Wafer

•Check a number of angles on wafer

•We want other dies to pass too

•Make sure simulating effects of process variations for dies on dominant locations is satisfactory

Test and Validation of Proposed Methods

Comparison Methodology

Extract cell locations from Astro

Run script that changes cell speeds of a chip at a given angle and given max. on-chip variation

Compare minimum setup times and hold times with a nominal run

For each dominant location angle {

}

Used to show that location based variations can be deteriorating as compared to worst-case runs

Comparison with Probabilistic Cell Speeds

Run script that changes cell speeds of a chip using a uniform distribution given max. on-chip variation

Compare minimum setup times and hold times with a location based deterministic run

Run script that changes cell speeds of a chip using a Gaussian distribution given max. on-chip variation

For each dominant location angle {

}

Used to show that location based variations can be deteriorating as compared to probabilistic models due to systematic variation

Proof I : Checking Validity of Method for Chips on Same Angle

Run script that changes cell speeds of a chip at angle

Compare minimum setup times and hold times runs

For a number of variations up to max on-chip variation

{

}

Used to show that for chips at same angle, simulating worst variation is satisfactory

Proof II : Checking Validity of Dominant Locations

Run script that changes cell speeds of a chip given that angle

Check that minimum setup or hold times are higher than found using dominant locations

For a number of (angles \ dominant angles)

{

}

Used to show that simulating for chips at dominant locations satisfactory for any location

Experimental Results

Setup (max delay)

0.12430.10010.12060.1234

Uniform randomGaussian random

Location basedNominal

•Up to 20% variation in minimum slack observed on ARM7

•Or, try setting clock to 1GHz whereas your chip can run @ 800MHz on most locations on wafer

0.1242 when less variation used

•Hypothesis I supported

Where Location Based Method fits in PrimeTime?

Setup (max delay)Hold (min delay)

WC TYP BC BC/WC OCV

max delays paths for setup

1.740.53

max delays paths

1.74 3.92 5.150.531.401.71

max data min clock delays for setup

-1.70-3.29

Location based falls here, more realistic than both directions

underestimate overest.

Conclusions

•Location based variation fits on a more realistic scale as compared to current PrimeTime models

•Probabilistic models fail to be satisfactory as they neglect deterministic systematic relationship between cells

•Dominant locations provide a means to reduce simulation time, yet integrate more accurate process variation effects

Future Directions

•Incorporation of interconnect delay variations

•Proper selection of dominant locations

A layout based mathematical approach