Ramon Chips, Haifa, Israel - NASA · 2008-10-08 · Ramon Chips Converting PLD-based SoC into...
Transcript of Ramon Chips, Haifa, Israel - NASA · 2008-10-08 · Ramon Chips Converting PLD-based SoC into...
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Ramon Chips, Haifa, Israel
Technion 1925 2000
Ramon Chips
Converting PLD-based SoCinto RadSafe™ ASIC
Prof. Ran Ginosar, CEO, Ramon ChipsMAPLD, September [email protected]
Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003
Ramon Chips
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About Ramon Chips• Private company, incorporated 2004• Based in Haifa, Israel• Developed RadSafeTM technology• Made, qualified and delivered several
space grade components • Focused on ASIC for space Most products FPGAASIC conversions Higher reliability and performance
at lower cost and power
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Outline• RadSafeTM concepts• RadSafeTM libraries and cores• Example FPGAASIC conversions
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RadSafeTM concepts• Rad Hard By Design• Rad Hard By Similarity• Commercial CMOS technology Tower Semi 0.18µ CMOS ( 0.13µ)
• Static CMOS circuits• Own library (rad hard circuits)• Own methodology• Proven Rad Hard, qualifiable
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Radiation effects mitigated by RadSafeTM
• TID• SEL• SEU/SET in flip-flops• SEU in SRAMs• SEFI caused by PLL/DLLs
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Mitigating TID effects• Advanced CMOS process – ≤0.18µ with STI
• Fixed layout – predictable parasitic devices; insensitive to placement
• Only 30% area penalty• TID immunity: >300Krad in all tests
INA
INB
OUT
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Performance under TID stress
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.25 0.5 0.75 1 1.25 1.5 1.07 2Vds(V)
Id(A
)
0.0000010
0.0000100
0.0001000
0.0010000
0.0100000
0.1000000
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Vgs(V)
Id(A
)
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0 -0.3 -0.6 -0.9 -1.2 -1.5 -1.8Vds(V)
Id(A
)
m
0.0000100
0.0001000
0.0010000
0.0100000
0.1000000
0 -0.25 -0.5 -0.75 -1 -1.25 -1.5 -1.07 -2
Vgs(V)
Id(A
)
NMOS
PMOS
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Mitigating SEL• Fixed PNPN geometry insensitive to placement
• Double/triple guard rings in I/O circuits• No SEL detected up to 106MeV·cm2/mg
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Mitigating SEU in flip-flops• SEP = Single Error Protected FF• Continuous self-correcting feedback At each latch (x2)
• SET filter for data • SET Filter for clock • SET Filter for async Set/Reset• All flip-flops tested by SCAN• Less than 10-12 errors/bit/day
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RadSafe SRAM cell
• Less than 2×10-7 errors/bit/day• EDAC tested to fix all SEU in SRAM
BL BLB
WL
Conventional SRAM cell
BL BLB
WLB
RadSafeTM SRAM cell
Many NMOS devices connected to bit-lines
Only PMOS devices connected to bit-lines
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Analog PLL sensitive to TID, SET
• TID affects analog transistors• SET unlock PLL• SET Phase accumulation • False relock Missing cycles• Sensitive to process, voltage,
temperature variations
PFD+
CPVCO
/N
clk_refclk_out
Ionizing particle might discharge the capacitor, which hold the control
voltagefrequency
control voltage
frequency
phase
Discharge by ionizing particle
Missing clock cycle
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RH all-digital DLL• Standard cell logic: TID, SEL protection Effective over a wide range of
process, voltage and temperature variations• SEP flip-flops: SET/SEU protection• Low jitter: typical 1% clock cycle• Frequency multiplication by 2X,4X• Clock de-skewing
PHD CTRL
DCDL
up
dn
ctrl[m-1:0]
MUL
clkfb
REFCLK
CLK1XCLK2XCLK4X
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RadSafe™ libraries• Logic 80 cells, 40 Kgates/mm2
• I/O 15 cells (incl. 500 Mbps LVDS)
• SRAM Single / dual port, 100 Kbit/mm2
• DLL• And our own methodology Conversion, design, layout
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Examples of ASICs
FPGAconversion
Radiation &qualification
test
LEON3 SoCprototype
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LEON3FT SoC• Prototype in 2006
GR702RC
• Tested: 120 MHz (CPU)
250 Mbps (SpW)
All SEUs corrected
REG
I-TRC
B-TRC
INSTCACHE
DATACACHE
CLK
SpWCLK
Now developing second generation…
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Image Compression ASIC• Standard JPEG2000• 5 Mbit (250 cores), 750 Kgates
30M transistors, 12×12mm• Less than 3W• Converted from Stratix-II FPGA• For imaging satellites ASIC: 44 12-bit Mpix/s, 1 Tops Many ASICs in system
• Fab in 2008
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Converting FPGA to ASIC• Add mitigation Enforce HDL coding rules SEU detection and recovery
• Add reconfigurability Never believe constants
• Verify new HDL on old FPGA+System Or on FPGA-based test system
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Summary• RadSafe™ On commercial process, using standard EDA Proven Rad-Hard-By-Design High performance, low power, low cost
ASICs
• Example projects FPGA conversions LEON3FT SoC
• Future: Now developing 0.13µ