Rail-to-Rail Output Wide-Input-Voltage Dual … amplifiers from Texas Instruments. The common-mode...

TLV2442, TLV2442A, TLV2444, TLV2444AAdvanced LinCMOS RAIL-TO-RAIL OUTPUT

WIDE-INPUT-VOLTAGE OPERATIONAL AMPLIFIERSSLOS169H – NOVEMBER 1996 – REVISED MARCH 2001

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output Swing Includes Both Supply Rails

Extended Common-Mode Input VoltageRange . . . 0 V to 4.25 V (Min) at 5-V SingleSupply

No Phase Inversion

Low Noise . . . 16 nV/√Hz Typ at f = 1 kHz

Low Input Offset Voltage950 µV Max at TA = 25°C (TLV244xA)

Low Input Bias Current . . . 1 pA Typ

600-Ω Output Drive

High-Gain Bandwidth . . . 1.8 MHz Typ

Low Supply Current . . . 750 µA Per ChannelTyp

Macromodel Included

Available in Q-Temp Automotive HighRel Automotive ApplicationsConfiguration Control/Print SupportQualification to Automotive Standards

description

The TLV244x and TLV244xA are low-voltageoperational amplifiers from Texas Instruments.The common-mode input voltage range of thesedevices has been extended over typical standardCMOS amplifiers, making them suitable for a widerange of applications. In addition, these devicesdo not phase invert when the common-mode inputis driven to the supply rails. This satisfies mostdesign requirements without paying a premiumfor rail-to-rail input performance. They also exhibitrail-to-rail output performance for increaseddynamic range in single- or split-supplyapplications. This family is fully characterized at3-V and 5-V supplies and is optimized forlow-voltage operation. Both devices offercomparable ac performance while having lowernoise, input offset voltage, and power dissipationthan existing CMOS operational amplifiers. TheTLV244x has increased output drive overprevious rail-to-rail operational amplifiers and candrive 600-Ω loads for telecommunicationsapplications.

The other members in the TLV244x family are the low-power, TLV243x, and micro-power, TLV2422, versions.

The TLV244x, exhibiting high input impedance and low noise, is excellent for small-signal conditioning forhigh-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels andlow-voltage operation, these devices work well in hand-held monitoring and remote-sensing applications. Inaddition, the rail-to-rail output feature with single- or split-supplies makes this family a great choice wheninterfacing with analog-to-digital converters (ADCs). For precision applications, the TLV244xA is available witha maximum input offset voltage of 950 µV.

If the design requires single operational amplifiers, see the TI TLV2211/21/31. This is a family of rail-to-rail outputoperational amplifiers in the SOT-23 package. Their small size and low power consumption make them idealfor high density, battery-powered equipment.

Copyright 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinCMOS is a trademark of Texas Instruments.

Figure 1

HIGH-LEVEL OUTPUT VOLTAGEvs

HIGH-LEVEL OUTPUT CURRENT

– H

igh

-Lev

el O

utp

ut

Vo

ltag

e –

VV

OH

3

2.5

2

1.5

1

0.5

00 2 4 6 8 10 12

IOH – High-Level Output Current – mA

VDD = 3 V

TA = 125°C

TA = 85°C TA = 25°C

TA = –40°C

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

TLV2442, TLV2442A, TLV2444, TLV2444AAdvanced LinCMOS RAIL-TO-RAIL OUTPUTWIDE-INPUT-VOLTAGE OPERATIONAL AMPLIFIERSSLOS169H – NOVEMBER 1996 – REVISED MARCH 2001

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2442 AVAILABLE OPTIONS

PACKAGED DEVICES

TAVIOmaxAT 25°C

SMALLOUTLINE

(D)

CHIP CARRIER(FK)

CERAMIC DIP(JG)

TSSOP(PW)

CERAMIC FLATPACK

(U)

0°C to 70°C 2.5 mV TLV2442CD — — TLV2442CPW —

40°C to 85°C 950 µV TLV2442AID — — TLV2442AIPW —–40°C to 85°C µ

2.5 mV TLV2442ID — — — —

40°C to 125°C 950 µV TLV2442AQD — — TLV2442AQPW —–40°C to 125°C µ

2.5 mV TLV2442QD — — TLV2442QPW —

55°C to 125°C950 µV — TLV2442AMFK TLV2442AMJG — TLV2442AMU

–55°C to 125°Cµ

2.5 mV — TLV2442MFK TLV2442MJG — TLV2442MU

The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TLV2442CDR).

TLV2444 AVAILABLE OPTIONS

PACKAGED DEVICES

TAVIOmaxAT 25°C

SMALLOUTLINE

(D)

TSSOP(PW)

0°C to 70°C 2.5 mV TLV2444CD TLV2444CPW

40°C to 125°C 950 µV TLV2444AID TLV2444AIPW–40°C to 125°C µ

2.5 mV TLV2444ID TLV2444IPW

The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TLV2444CDR).

1

2

3

4

8

7

6

5

1OUT1IN–1IN+

VDD – /GND

VDD+2OUT2IN–2IN+

1

2

3

4

8

7

6

5

1OUT1IN–1IN+

VDD– /GND

VDD+2OUT2IN–2IN+

NCVDD +2OUT2IN –2IN +

NC1OUT1IN –1IN +

VDD– /GND

1

2

3

4

5

10

9

8

7

6

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC2OUTNC2IN–NC

NC1IN–

NC1IN+

NC

NC

1OU

TN

C2I

N+

NC

NC

NC

NC

VD

D+

VD

D–

TLV2442FK PACKAGE(TOP VIEW)

/GN

D

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OUT1IN–1IN+

VDD+2IN+2IN–

2OUT

4OUT4IN–4IN+VDD–/GND3IN+3IN–3OUT

(TOP VIEW)

TLV2444D OR PW PACKAGE

TLV2442U PACKAGE(TOP VIEW)

TLV2442D OR JG PACKAGE

(TOP VIEW)

TLV2442PW PACKAGE

(TOP VIEW)

TLV2442, TLV2442A, TLV2444, TLV2444A

WIDE-INPUT-VO

LTAGE O

PERATIONAL AM

PLIFIERSS

LOS

169H – N

OV

EM

BE

R 1996 – R

EV

ISE

D M

AR

CH

2001

RAIL-TO-RAIL O

UTPUTAdvanced LinCM

OS

PO

ST

OF

FIC

E B

OX

655303 DA

LLAS

, TE

XA

S 75265

•3

equivalent schematic (each amplifier)

Q27

R9

Q29Q22

Q23

Q26

Q25

Q24

Q31 Q34 Q36

Q32

Q33 Q35

Q37

D1

Q30

R10

VB3

VB2

VB4

VDD+

VDD–/GND

OUT

R8R1 R2

Q2 Q5

Q1 Q4

Q3

Q12

Q11

Q10Q6

Q7

Q8

Q9

VB3

VB4

C1

C2

C3

R5

R6

Q13 Q15

Q16

Q17

Q14

Q19

Q18

Q20

Q21

R7R3 R4

VB2

IN+

IN–

VB1

COMPONENTCOUNT

TransistorsDiodesResistorsCapacitors

695

266



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VDD (see Note 1) 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input voltage, VID (see Note 2) ±VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI (any input, see Note 1) –0.3 V to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II (any input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current out of VDD– ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix (dual) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I suffix (quad) –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q suffix –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD –.2. Differential voltages are at IN+ with respect to IN–. Excessive current will flow if input is brought below VDD– – 0.3 V.3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C

PACKAGE APOWER RATING ABOVE TA = 25°C

APOWER RATING

APOWER RATING

APOWER RATING

D (8)D (14)

FKJG

PW (8)PW (14)

U

725 mW1022 mW1375 mW1050 mW525 mW720 mW675 mW

5.8 mW/°C7.6 mW/°C

11.0 mW/°C8.4 mW/°C4.2 mW/°C5.6 mW/°C5.4 mW/°C

464 mW900 mW880 mW672 mW336 mW634 mW432 mW

377 mW777 mW715 mW546 mW273 mW547 mW350 mW

145 mW450 mW275 mW210 mW105 mW317 mW135 mW

recommended operating conditions

C SUFFIX I SUFFIX Q SUFFIX M SUFFIXUNIT

MIN MAX MIN MAX MIN MAX MIN MAXUNIT

Supply voltage, VDD 2.7 10 2.7 10 2.7 10 2.7 10 V

Input voltage range, VI VDD– VDD+ – 1 VDD– VDD+ – 1 VDD– VDD+ – 1.3 VDD– VDD+ – 1.3 V

Common-mode input voltage,VIC

VDD– VDD+ – 1 VDD– VDD+ – 1 VDD– + 2 VDD+ – 1.3 VDD– + 2 VDD+ – 1.3 V

Operating free-air temperature,TA

0 70 –40 125 –40 125 –55 125 °C




electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TA†TLV2442

UNITPARAMETER TEST CONDITIONS TA†MIN TYP MAX

UNIT

TLV244xC 25°C 300 2000

TLV244xI Full range 2500

VIO Input offset voltage TLV244xAI25°C 300 950

µVVIO Input offset voltage TLV244xAIFull range 1500

µV

TLV2442AQ 25°C 300 950

TLV2442AM Full range 1600

αVIOTemperature coefficient of input 25°C

2 µV/°CαVIO offset voltageVIC = 1 5 V

to 85°C2 µV/°C

Input offset voltage long-term drift(see Note 4)

VIC = 1.5 V,VO = 1.5 V,RS = 50 Ω

25°C 0.002 µV/mo

IIO Input offset current

RS 50 Ω25°C 0.5 60

pAIIO Input offset currentFull range 150

pA

25°C 1 60

IIB Input bias current

–40°C to85°C 150

pAIIB Input bias current125°C 350

pA

TLV2442Q/AQTLV2442M/AM

Full range 260

25°C0to

2.25

–0.25to

2.5

VICRCommon-mode input voltage

|VIO| ≤ 5 mV RS = 50 Ω

Full range0to2

VVICRg

range|VIO| ≤ 5 mV, RS = 50 Ω

25°C to–55°C

0to

2.25

–0.25to

2.5

V

125°C0to2

IO = –100 µA 25°C 2.98

VOH High-level output voltageIO = 3 mA

25°C 2.5 VIO = –3 mA

Full range 2.25

VIC = 1.5 V, IO = 100 µA 25°C 0.02

VOL Low-level output voltageVIC = 1 5 V IO 3 A

25°C 0.63 VVIC = 1.5 V, IO = 3 A

Full range 1

L i l diff ti l RL = 600 Ω25°C 0.7 1

AVDLarge-signal differentialvoltage amplification

VO = 1 V to 2 VRL = 600 Ω

Full range 0.4 V/mVvoltage am lification

RL = 1 MΩ 25°C 750

rid Differential input resistance 25°C 1000 GΩ

ri Common-mode input resistance 25°C 1000 GΩ

ci Common-mode input capacitance f = 10 kHz 25°C 8 pF

zo Closed-loop output impedance f = 1 MHz, AV = 10 25°C 130 Ω† Full range for the C suffix is 0°C to 70°C. Full range for the dual I suffix is – 40°C to 85°C. Full range for the quad I suffix is – 40°C to 125°C. Full

range for the Q suffix is –40°C to 125°C. Full range for the M suffix is – 55°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated

to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.



electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)(continued)

PARAMETER TEST CONDITIONS TA†TLV2442


UNIT

V 0 t 2 25 V25°C 65 75

CMRR Common-mode rejection ratioVIC = 0 to 2.25 V,VO = 1 5 V

Full range 55dBCMRR Common-mode rejection ratio VO = 1.5 V,

RS = 50 Ω TLV2442Q/AQTLV2442M/AM

Full range 50

dB

kSVRSupply-voltage rejection ratio VDD = 2.7 V to 8 V, VIC = VDD/2, 25°C 80 95

dBkSVRy g j

(∆VDD± /∆VIO)DD , IC DD ,

No load Full range 80dB

IDD Supply current (per channel)VO = 1.5 V, 25°C 725 1100

µAIDD Supply current (per channel) ONo load Full range 1100

µA

† Full range for the C suffix is 0°C to 70°C. Full range for the dual I suffix is – 40°C to 85°C. Full range for the quad I suffix is – 40°C to 125°C. Fullrange for the Q suffix is –40°C to 125°C. Full range for the M suffix is – 55°C to 125°C.

operating characteristics at specified free-air temperature, VDD = 3 V

PARAMETER TEST CONDITIONS TA†TLV244x


UNIT

25°C 0.65 1.3

SR Slew rate at unity gainVO = 1 V to 2 V, RL = 600 Ω,

Fullrange

0.65V/µs

CL = 100 pF TLV2442Q/AQTLV2442M/AM

Fullrange

0.4

V Equivalent input noise voltagef = 10 Hz 25°C 170

nV/√HzVn Equivalent input noise voltagef = 1 kHz 25°C 18

nV/√Hz

VN(PP) Peak to peak equivalent input noise voltagef = 0.1 Hz to 1 Hz 25°C 2.6

µVVN(PP) Peak-to-peak equivalent input noise voltagef = 0.1 Hz to 10 Hz 25°C 5.1

µV

In Equivalent input noise current 25°C 0.6 fA/√Hz

VO = 0.5 V to 2.5 V, AV = 1 0.08%

THD + N Total harmonic distortion plus noiseVO = 0.5 V to 2.5 V,RL = 600 Ω, AV = 10 25°C 0.3%f = 1 kHz AV = 100 2%

Gain bandwidth productf =10 kHz, RL = 600 Ω,

25°C 1 75 MHzGain-bandwidth product,

CL = 100 pFL ,

25°C 1.75 MHz

BOM Maximum output swing bandwidthVO(PP) = 1 V, RL = 600 Ω,

25°C 0 9 MHzBOM Maximum output-swing bandwidth O(PP) ,AV = 1,

L ,CL = 100 pF

25°C 0.9 MHz

AV = –1, To 0 1% 1 5t Settling time

AV = 1,Step = –2.3 V to 2.3 V,

To 0.1%25°C

1.5µsts Settling time ,

RL = 600 Ω,To 0 01%

25°C3 2

µsL

CL = 100 pF To 0.01% 3.2

φm Phase margin at unity gainRL = 600 Ω CL = 100 pF

25°C 65°

Gain marginRL = 600 Ω, CL = 100 pF

25°C 9 dB† Full range for the C suffix is 0°C to 70°C. Full range for the dual I suffix is – 40°C to 85°C. Full range for the quad I suffix is – 40°C to 125°C. Full

range for the Q suffix is –40°C to 125°C. Full range for the M suffix is – 55°C to 125°C.




electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)



UNIT

TLV244xC 25°C 300 2000

TLV244xI Full range 2500

VIO Input offset voltage TLV244xA25°C 300 950

µVVIO Input offset voltage TLV244xAFull range 1500

µV

TLV2442AQ 25°C 300 950

TLV2442AM Full range 1600

αVIOTemperature coefficient of input 25°C

2 µV/°CαVIO offset voltage to 85°C 2 µV/°C

Input offset voltage long-termdrift (see Note 4)

VDD± = ±2.5 V,VO = 0,

VIC = 0,RS = 50 Ω 25°C 0.002 µV/mo

IIO Input offset current25°C 0.5 60

pAIIO Input offset currentFull range 150

pA

25°C 1 60

IIB Input bias current

–40°C to85°C 150

pAIIB Input bias current125°C 350

pA

TLV2442Q/AQTLV2442M/AM

Full range 260

VICRCommon-mode input voltage

|VIO| ≤ 5 mV RS = 50 Ω

25°C0to

4.25

–0.25to

4.5VVICR

grange

|VIO| ≤ 5 mV, RS = 50 Ω

Full range0to4

V

IOH = –100 µA 25°C 4.97

VOH High-level output voltageIOH = 5 mA

25°C 4 4.35 VIOH = –5 mA

Full range 4

VIC = 2.5 V, IOL = 100 µA 25°C 0.01

VOL Low-level output voltageVIC = 2 5 V IOL = 5 A

25°C 0.8 VVIC = 2.5 V, IOL = 5 A

Full range 1.25

L i l diff ti l V 2 5 V R 600 Ω‡25°C 0.9 1.3

AVDLarge-signal differentialvoltage amplification

VIC = 2.5 V,VO = 1 V to 4 V

RL = 600 Ω‡Full range 0.5 V/mVVD voltage am lification VO = 1 V to 4 V

RL = 1 MΩ‡ 25°C 950

rid Differential input resistance 25°C 1000 GΩ

ri Common-mode input resistance 25°C 1000 GΩ

ciCommon-mode inputcapacitance

f = 10 kHz 25°C 8 pF

zo Closed-loop output impedance f = 1 MHz, AV = 10 25°C 140 Ω

CMRR Common mode rejection ratioVIC = 0 to 4.25 V, VO = 2.5 V, 25°C 70 75

dBCMRR Common-mode rejection ratio IC ,RS = 50 Ω

O ,

Full range 70dB


‡ Referenced to 2.5 VNOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated

to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.



electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)(continued)



UNIT

kSVR Supply voltage rejection ratio (∆VDD/∆VIO)VDD = 4.4 V to 8 V, 25°C 80 95

dBkSVR Supply-voltage rejection ratio (∆VDD/∆VIO) DD ,VIC = VDD/2, No load Full range 80

dB

IDD Supply current (per channel) VO = 2 5 V No load25°C 750 1100

µAIDD Supply current (per channel) VO = 2.5 V, No loadFull range 1100

µA


operating characteristics at specified free-air temperature, VDD = 5 V



UNIT

V 0 5 V t 2 5 V25°C 0.75 1.4

SR Slew rate at unity gainVO = 0.5 V to 2.5 V,RL = 600 Ω‡ Full range 0.75

V/µsSR Slew rate at unity gain RL = 600 Ω‡, CL = 100 pF‡ TLV2442Q/AQ

TLV2442M/AMFull range 0.5

V/µs

V Equivalent input noise voltagef = 10 Hz 25°C 130

nV/√HzVn Equivalent input noise voltagef = 1 kHz 25°C 16

nV/√Hz

VN(PP)Peak-to-peak equivalent input noise f = 0.1 Hz to 1 Hz 25°C 1.8

µVVN(PP)q

voltage f = 0.1 Hz to 10 Hz 25°C 3.6µV

In Equivalent input noise current 25°C 0.6 fA/√Hz

VO = 1.5 V to 3.5 V, AV = 1 0.017%

THD + N Total harmonic distortion plus noiseVO 1.5 V to 3.5 V,f = 1 kHz,

‡AV = 10 25°C 0.17%

RL = 600 Ω‡AV = 100 1.5%

Gain-bandwidth productf =10 kHz, CL = 100 pF‡

RL = 600 Ω‡,25°C 1.81 MHz

BOM Maximum output-swing bandwidthVO(PP) = 2 V,RL = 600 Ω‡,

AV = 1,CL = 100 pF‡ 25°C 0.5 MHz

t Settling time

AV = –1,Step = 0.5 V to 2.5 V,

To 0.1%25°C

1.5µsts Settling time

,RL = 600 Ω‡,CL = 100 pF‡ To 0.01%

25°C2.6

µs

φm Phase margin at unity gainRL = 600 Ω‡ CL = 100 pF‡ 25°C 68°

Gain marginRL = 600 Ω‡, CL = 100 pF‡

25°C 8 dB† Full range for the C suffix is 0°C to 70°C. Full range for the dual I suffix is – 40°C to 85°C. Full range for the quad I suffix is – 40°C to 125°C. Full

range for the Q suffix is –40°C to 125°C. Full range for the M suffix is – 55°C to 125°C.‡ Referenced to 2.5 V




TYPICAL CHARACTERISTICS

Table of Graphs†

FIGURE

VIO Input offset voltageDistribution 2, 3

VIO Input offset voltagevs Common-mode input voltage

,4, 5

αVIO Input offset voltage temperature coefficient Distribution 6, 7

IIB /IIO Input bias and input offset currents vs Free-air temperature 8

VOH High-level output voltage vs High-level output current 9, 10

VOL Low-level output voltage vs Low-level output current 11, 12

VO(PP) Maximum peak-to-peak output voltage vs Frequency 13

IOS Short circuit output currentvs Supply voltage 14

IOS Short-circuit output currenty g

vs Free-air temperature 15

VO Output voltage vs Differential Input voltage 16, 17

AVD Differential voltage amplification vs Load resistance 18

Large signal differential voltage amplification and phase margin vs Frequency 19 20AVD

Large-signal differential voltage amplification and phase margin vs Frequency 19, 20AVD

Large signal differential voltage amplification vs Free air temperature 21 22Large-signal differential voltage amplification vs Free-air temperature 21, 22

zo Output impedance vs Frequency 23, 24

CMRR Common mode rejection ratiovs Frequency 25

CMRR Common-mode rejection ratioq y

vs Free-air temperature 26

kSVR Supply voltage rejection ratiovs Frequency 27, 28

kSVR Supply-voltage rejection ratioq y

vs Free-air temperature,

29

IDD Supply current vs Supply voltage 30

SR Slew ratevs Load capacitance 31

SR Slew ratevs Free-air temperature 32

Inverting large-signal pulse response 33, 34

VOVoltage-follower large-signal pulse response 35, 36

VOInverting small-signal pulse response 37, 38

Voltage-follower small-signal pulse response 39, 40

Vn Equivalent input noise voltage vs Frequency 41, 42

Noise voltage Over a 10-second period 43

THD + N Total harmonic distortion plus noise vs Frequency 44, 45

Gain bandwidth productvs Free-air temperature 46

Gain-bandwidth productvs Supply voltage 47

φ Phase marginvs Frequency 19, 20φm Phase margin

q yvs Load capacitance

,48

Gain margin vs Load capacitance 49

B1 Unity-gain bandwidth vs Load capacitance 50

† For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.




Figure 2

VIO – Input Offset Voltage – µV

Per

cen

tag

e o

f Am

plif

iers

– %

DISTRIBUTION OF TLV2442INPUT OFFSET VOLTAGE

–700

16

14

12

10

8

6

4

2

0

20

18

–500

–300

–100 100

300

500

700

900

868 Amplifiers From1 Wafer LotVDD = ±1.5 V

TA = 25°C0

–200

–400

–600 200

400

600

800

Figure 3

VIO – Input Offset Voltage – µV

Per

cen

tag

e o

f Am

plif

iers

– %

DISTRIBUTION OF TLV2442INPUT OFFSET VOLTAGE

–700

16

14

12

10

8

6

4

2

0

20

18

–500

–300

–100 100

300

500

700

900

868 Amplifiers From1 Wafer LotVDD = ±2.5 V

TA = 25°C

0

–200

–400

–600 200

400

600

800

Figure 4

INPUT OFFSET VOLTAGEvs

COMMON-MODE INPUT VOLTAGE2

1.5

1

0.5

0

–0.5

–1

–1.5

–2–0.5 0 0.5 1 1.5 2 2.5 3

VIC – Common-Mode Input Voltage – V

VDD = 3 VTA = 25°C

– In

pu

t O

ffse

t V

olt

age

– m

VV

IO

Figure 5

INPUT OFFSET VOLTAGEvs

COMMON-MODE INPUT VOLTAGE

– In

pu

t O

ffse

t V

olt

age

– m

VV

IO

2

1.5

1

0.5

0

–0.5

–1

–1.5

–2–0.5 0 0.5 1 1.5 2 2.5 3

VIC – Common-Mode Input Voltage – V

VDD = 5 VTA = 25°C

3.5 4 4.5 5





Figure 6

9

6

3

0

Per

cen

tag

e o

f Am

plif

iers

– %

12

15

DISTRIBUTION OF TLV2442 INPUT OFFSETVOLTAGE TEMPERATURE COEFFICIENT

αVIO – Temperature Coefficient – µV/°C–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4

32 Amplifiers From 1Wafer LotVDD = ±1.5 VP Package25°C to 125°C

Figure 7

9

6

3

0

Per

cen

tag

e o

f Am

plif

iers

– %

12

15

DISTRIBUTION OF TLV2442 INPUT OFFSETVOLTAGE TEMPERATURE COEFFICIENT

αVIO – Temperature Coefficient – µV/°C–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4–8

1832 Amplifiers From 2Wafer LotsVDD = ±2.5 VP Package25°C to 125°C

Figure 8

15

10

5

025 45 65 85

20

25

30

105 125

INPUT BIAS AND INPUT OFFSET CURRENTSvs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

35VDD = ±2.5 VVIC = 0VO = 0RS = 50 Ω

IIB

IIO

IIB a

nd

IIO

– In

pu

t B

ias

and

Inp

ut

Off

set

Cu

rren

ts –

pA

IBII I

O

Figure 9



– H

igh

-Lev

el O

utp

ut

Vo

ltag

e –

VV

OH

3

2.5

2

1.5

1

0.5

00 2 4 6 8 10 12


VDD = 3 V

TA = 125°C

TA = 85°C TA = 25°C

TA = –40°C




Figure 10



– H

igh

-Lev

el O

utp

ut

Vo

ltag

e –

VV

OH

3

2.5

2

1.5

1

0.5

00 5 10 15 20 25


VDD = 5 V

TA = 85°C

TA = 125°C

5

4.5

4

3.5

TA = –40°C

TA = 25°C

Figure 11

LOW-LEVEL OUTPUT VOLTAGEvs

LOW-LEVEL OUTPUT CURRENT

– L

ow

-Lev

el O

utp

ut

Vo

ltag

e –

VV

OL

3

2.5

2

1.5

1

0.5

00 2 4 6 8 10

IOL – Low-Level Output Current – mA

VDD = 3 V

TA = 25°C

TA = 125°C

TA = 85°C

TA = –40°C

Figure 12

LOW-LEVEL OUTPUT VOLTAGEvs

LOW-LEVEL OUTPUT CURRENT

– L

ow

-Lev

el O

utp

ut

Vo

ltag

e –

VV

OL

2.5

2

1.5

1

0.5

00 2 4 6 8 10

IOL – Low-Level Output Current – mA

VDD = 5 V

TA = 25°C

TA = 125°C

TA = 85°C

TA = –40°C

Figure 13

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGEvs

FREQUENCY

– M

axim

um

Pea

k-to

-Pea

k O

utp

ut

Vo

ltag

e –

VV

O(P

P)

5

4

3

2

1

0100 1 k 10 k 100 k 1 M 10 M

f – Frequency – Hz

RL = 600 Ω

VDD = 3 V

VDD = 5 V





Figure 14

SHORT-CIRCUIT OUTPUT CURRENTvs

SUPPLY VOLTAGE

– S

ho

rt-C

ircu

it O

utp

ut

Cu

rren

t –

mA

I OS

15

10

5

0

–5

–10

–15

–20

–252 3 4 5 6 7 8 9

VDD – Supply Voltage – V

VO = VDD/2VIC = VDD/2TA = 25°C

25

20

10

VID = 100 mV

VID = –100 mV

Figure 15

SHORT-CIRCUIT OUTPUT CURRENTvs


– S

ho

rt-C

ircu

it O

utp

ut

Cu

rren

t –

mA

I OS

15

10

5

0

–5

–10

–15

–20

–25–75 –50 –25 0 25 50 75 100


VDD = 5 VVO = 2.5 V

25

20

125

VID = 100 mV

VID = –100 mV

Figure 16

OUTPUT VOLTAGEvs

DIFFERENTIAL INPUT VOLTAGE

VDD = 3 VVIC = 1.5 VRL = 600 ΩTA = 25°C

–1000 –750 –500 –250 0

VID – Differential Input Voltage – µV

250 500 750 1000

– O

utp

ut

Vo

ltag

e –

VV

O

2.5

2

1.5

1

0.5

0

3

Figure 17

OUTPUT VOLTAGEvs

DIFFERENTIAL INPUT VOLTAGE

– O

utp

ut

Vo

ltag

e –

VV

O

5

4

3

2

1

0–1000 –750 –500 –250 0

VID – Differential Input Voltage – µV

VDD = 5 VVIC = 2.5 VRL = 600 ΩTA = 25°C

250 500 750 1000




DIFFERENTIAL VOLTAGE AMPLIFICATIONvs

LOAD RESISTANCE

– D

iffe

ren

tial

Vo

ltag

e A

mp

lific

atio

n –

V/m

VA

VD

100

10

10.1 1 10 100 1000

RL – Load Resistance – kΩ

VO(PP) = 2 VTA = 25°C

VDD = 3 V

VDD = 5 V

Figure 18

0

20

10 k 100 k 1 M

40

60

80

LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE MARGIN

vsFREQUENCY

f – Frequency – Hz10 M

VDD = 3 VRL = 600 ΩCL = 600 pFTA = 25°C

–20

–40 –90°

–45°

0°

45°

90°

135°

180°

AV

D –

Lar

ge-

Sig

nal

Dif

fere

nti

al

ÁÁÁÁÁÁ

AV

D Vo

ltag

e A

mp

lific

atio

n –

dB

mφ

– P

has

e M

arg

in

Figure 19





LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE MARGIN

vsFREQUENCY

60

40

20

0

–20

–4010 k 100 k 1 M 10 M


VDD = 5 VRL = 600 ΩCL = 600 pFTA = 25°C

80 180°

135°

90°

45°

0°

–45°

–90°

mφ

– P

has

e M

arg

in

AV

D –

Lar

ge-

Sig

nal

Dif

fere

nti

al

ÁÁÁÁÁÁ

AV

D Vo

ltag

e A

mp

lific

atio

n –

dB

Figure 20

Figure 21

10

1

0.1

1000

100

–75 –25 25 75 125

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION

vsFREE-AIR TEMPERATURE

VDD = 3 V VIC = 2.5 VVO = 1 V to 4 V

RL = 1 MΩ

RL = 600 Ω

–50 0 50 100

AV

D –

Lar

ge-

Sig

nal

Dif

fere

nti

al

ÁÁÁÁÁÁ

AV

D


Vo

ltag

e A

mp

lific

atio

n –

V/m

V

Figure 22

10

1

0.1

1000

100

–75 –25 25 75 125

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION

vsFREE-AIR TEMPERATURE

VDD = 5 V VIC = 2.5 VVO = 1 V to 4 V

RL = 1 MΩ

RL = 600 Ω

–50 0 50 100

AV

D –

Lar

ge-

Sig

nal

Dif

fere

nti

al

ÁÁÁÁÁÁ

AV

D


Vo

ltag

e A

mp

lific

atio

n –

V/m

V




Figure 23

10

1

0.1

1000

100

100 1 k 10 k 100 k 1 M

zo –

Ou

tpu

t Im

ped

ance

– O


Ωz o

OUTPUT IMPEDANCEvs

FREQUENCY

VDD = 3 VTA = 25°C

AV = 100

AV = 10

AV = 1

Figure 24

10

1

0.1

100

100 1 k 10 k 100 k 1 M

zo –

Ou

tpu

t Im

ped

ance

– O


Ωz o

OUTPUT IMPEDANCEvs

FREQUENCY

VDD = 5 VTA = 25°C

AV = 100

AV = 10

AV = 1

Figure 25

60

40

20

010 100 1 k 10 k

CM

RR

– C

om

mo

n-M

od

e R

ejec

tio

n R

atio

– d

B

80

100

100 k 1 M

COMMON-MODE REJECTION RATIOvs

FREQUENCY


10 M

VDD = 5 VVIC = 2.5 V

VDD = 3 VVIC = 1.5 V

TA = 25°C

Figure 26


CM

RR

– C

om

mo

n-M

od

e R

ejec

tio

n R

atio

– d

B

COMMON-MODE REJECTION RATIOvs


90

80

70

60

100

–75 –50 –25 0 25 50 75 100 125

VDD = 5 V

VDD = 3 V





Figure 27

40

20

010 100 1 k

kSV

R –

Su

pp

ly-V

olt

age

Rej

ecti

on

Rat

io –

dB

60

80


100

10 k 100 k 1 M 10 M

SUPPLY-VOLTAGE REJECTION RATIOvs

FREQUENCY

kS

VR

VDD = 3 VTA = 25°C

kSVR+

kSVR–

Figure 28

40

20

010 100 1 k

kSV

R –

Su

pp

ly-V

olt

age

Rej

ecti

on

Rat

io –

dB

60

80


100

10 k 100 k 1 M 10 M


FREQUENCY

kS

VR

VDD = 5 VTA = 25°C

kSVR+

kSVR–

Figure 29




96

94

92

90

100

–75 –50 –25 0 25 50 75 100 125

VDD = 2.5 V to 8 V

98

kSV

R –

Su

pp

ly-V

olt

age

Rej

ecti

on

Rat

io –

dB

kS

VR

Figure 30

0 2 4 6 80

0.5

1

1.5

2

2.5

IDD

– S

up

ply

Cu

rren

t –

mA

DD

I

VDD – Supply Voltage – V

SUPPLY CURRENTvs

SUPPLY VOLTAGE

TA = 25°C

TA = 85°C

TA = –40°C

10




Figure 31

µs

SR

– S

lew

Rat

e –

V/

0

1

1.5

2

CL – Load Capacitance – pF

SLEW RATEvs

LOAD CAPACITANCE

100 k1 k10010

2.5

3

10 k

SR +

VDD = 5 VAV = –1TA = 25°C

SR –

0.5

Figure 32

1.5

1

0.5

2

µsS

R –

Sle

w R

ate

– V

/

–75 –50 –25 0 25 50 75 100 125


SLEW RATEvs


SR +

SR –

0

2.5

3VDD = 5 VRL = 600 ΩCL = 100 pFAV = 1

Figure 33

2

1

01 2 3 4 5

3

6 7 8 9

VO

– O

utp

ut

Vo

ltag

e –

VV

O

t – Time – µs

INVERTING LARGE-SIGNAL PULSE RESPONSE

0

VDD = 3 VRL = 2 kΩCL = 100 pFAV = –1TA = 25°C

10

Figure 34

0

4

1 2 3 4 5

2

1

3

5

6 7 8 9

VO

– O

utp

ut

Vo

ltag

e –

VV

O

t – Time – µs

VDD = 5 VRL = 2 kΩCL = 100 pFAV = –1TA = 25°C

INVERTING LARGE-SIGNAL PULSE RESPONSE

0 10





Figure 35

3

2

1

01 2 3 4 5 6 7 8 9

VO

– O

utp

ut

Vo

ltag

e –

VV

O

t – Time – µs

VDD = 3 VRL = 600 ΩCL = 100 pFAV = 1TA = 25°C

VOLTAGE-FOLLOWERLARGE-SIGNAL PULSE RESPONSE

0 10

Figure 36

VOLTAGE-FOLLOWERLARGE-SIGNAL PULSE RESPONSE

4

0.5 1 1.5 2 2.5

2

1

3

5

3 3.5 4 4.5

t – Time – µs

VDD = 5 VRL = 600 ΩCL = 100 pFAV = 1TA = 25°C

00

5V

O –

Ou

tpu

t V

olt

age

– V

VO

Figure 37

1.48

1.46

1.441 2 3 4 5

1.52

1.56

1.58

7 9 10

VO

– O

utp

ut

Vo

ltag

e –

VV

O

t – Time – µs

VDD = 3 VRL = 600 ΩCL = 100 pFAV = –1TA = 25°C

INVERTING SMALL-SIGNAL PULSE RESPONSE

0 6 8

1.5

1.54

Figure 38

0 1 2 3 4 5 6 7 8

t – Time – µs

INVERTING SMALL-SIGNAL PULSE RESPONSE


2.44

2.46

2.48

2.5

2.52

2.54

2.56

2.58

9 10

VO

– O

utp

ut

Vo

ltag

e –

VV

O




Figure 39

VOLTAGE-FOLLOWERSMALL-SIGNAL PULSE RESPONSE

1.440 0.5 1 1.5

VO

– O

utp

ut

Vo

ltag

e –

VV

O

t – Time – µs


1.46

1.48

1.5

1.52

1.54

1.56

1.58

2 2.5 3 3.5 4 4.5 5

Figure 40

VOLTAGE-FOLLOWERSMALL-SIGNAL PULSE RESPONSE

2.440 0.5 1 1.5

t – Time – µs


2.46

2.48

2.5

2.52

2.54

2.56

2.58

2 2.5 3 3.5 4 4.5 5

VO

– O

utp

ut

Vo

ltag

e –

VV

O

Figure 41

100

80

40

0

160

180

200

10 100 1 k

Vn

– E

qu

ival

ent

Inp

ut

No

ise

Vo

ltag

e –

nV

Hz

f – Frequency – Hz10 k

EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY

Vn

nV

/H

z

140

120

60

20

VDD = 3 VRS = 20 ΩTA = 25°C

Figure 42

60

40

010 100 1 k

Vn

– E

qu

ival

ent

Inp

ut

No

ise

Vo

ltag

e –

nV

Hz

80


100

10 k

EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY

120

140

Vn

nV

/H

z

VDD = 5 V RS = 20 ΩTA = 25°C

20





Figure 43

–1500

–20002 4 6

0

500

8 10

No

ise

Vo

ltag

e –

nV

t – Time – s

NOISE VOLTAGEOVER A 10-SECOND PERIOD

0

VDD = 5 Vf = 0.1 Hz to 10Hz TA = 25°C

1000

1500

2000

–500

–1000

1 3 5 7 9

Figure 44

10 1 k 10 k 100 kT

HD

+ N

– T

ota

l Har

mo

nic

Dis

tort

ion

Plu

s N

ois

e –

%


TOTAL HARMONIC DISTORTION PLUS NOISEvs

FREQUENCY

0.01

0.1

10VDD = 3 VRL = 600 ΩTA = 25°C

AV = 100

AV = 10

AV = 1

1

100

Figure 45

10 1 k 10 k 100 k

TH

D +

N –

To

tal H

arm

on

ic D

isto

rtio

n P

lus

No

ise

– %


TOTAL HARMONIC DISTORTION PLUS NOISEvs

FREQUENCY

0.01

0.1

10VDD = 5 VRL = 600 ΩTA = 25°C

AV = 100

AV = 10

AV = 1

1

100

Figure 46

–50 –25 0 25 50 75 100 125


Gai

n-B

and

wid

th P

rod

uct

– M

Hz

GAIN-BANDWIDTH PRODUCTvs


1.5

1

2

2.5

3RL = 600 ΩCL = 100 pFf = 10 kHz




Figure 47

Gai

n-B

and

wid

th P

rod

uct

– M

Hz

1.6

1.50 1 2 3 4 5

1.7

1.8

6 7 8|VDD±| – Supply Voltage – V

1.9

2

GAIN-BANDWIDTH PRODUCTvs

SUPPLY VOLTAGE

RL = 600 ΩCL = 100 pFf = 10 kHzTA = 25°C

Figure 48

10

om

– P

has

e M

arg

in

100 kCL – Load Capacitance – pF

φm

PHASE MARGINvs

LOAD CAPACITANCE

1 k100

RL = 600 ΩTA = 25°C

75°

60°

45°

30°

15°

0°

Rnull = 0

Rnull = 100 Ω

Rnull = 50 Ω

Rnull = 20 Ω

10 k

Figure 49

5

010

Gai

n M

arg

in –

dB

10

15

100 KCL – Load Capacitance – pF

20

25

GAIN MARGINvs

LOAD CAPACITANCE

1 K100

RL = 600 ΩTA = 25°C

10 K

Rnull = 100 Ω

Rnull = 50 Ω

Rnull = 20 Ω

Rnull = 0

Figure 50

0.5

010

1

100 kCL – Load Capacitance – pF

1.5

2

UNITY-GAIN BANDWIDTHvs

LOAD CAPACITANCE

1 k100

RL = 600 ΩTA = 25°C

10 k

– U

nit

y-G

ain

Ban

dw

idth

– k

Hz

ÁÁÁÁ

B1




APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using PSpice Parts model generation software. The Boylemacromodel (see Note 5) and subcircuit in Figure 51 were generated using the TLV244x typical electrical andoperating characteristics at TA = 25°C. Using this information, output simulations of the following key parameterscan be generated to a tolerance of 20% (in most cases):

Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification

Unity gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit

NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journalof Solid-State Circuits, SC-9, 353 (1974).

OUT

+

–

+

–

+

–

+

–

+–

+

–

+

– +

–

+–

.SUBCKT TLV2442 1 2 3 4 5C1 11 12 14E–12C2 6 7 60.00E–12DC 5 53 DXDE 54 5 DXDLP 90 91 DXDLN 92 90 DXDP 4 3 DXEGND 99 0 POLY (2) (3,0) (4,) 0 .5 .5FB 7 99 POLY (5) VB VC VE VLP VLN 0+ 984.9E3 –1E6 1E6 1E6 –1E6GA 6 0 11 12 377.0E–6GCM 0 6 10 99 134E–9ISS 3 10 DC 216.0E–6HLIM 90 0 VLIM 1KJ1 11 2 10 JXJ2 12 1 10 JXR2 6 9 100.OE3

RD1 60 11 2.653E3RD2 60 12 2.653E3R01 8 5 50R02 7 99 50RP 3 4 4.310E3RSS 10 99 925.9E3VAD 60 4 –.5VB 9 0 DC 0VC 3 53 DC .78VE 54 4 DC .78VLIM 7 8 DC 0VLP 91 0 DC 1.9VLN 0 92 DC 9.4.MODEL DX D (IS=800.0E–18).MODEL JX PJF (IS=1.500E–12BETA=1.316E-3+ VTO=–.270).ENDS

VCC+

RP

IN –2

IN+1

VCC–

VAD

RD1

11

J1 J2

10

RSS ISS

3

12

RD2

60

VE

54DE

DP

VC

DC

4

C1

53

R2

6

9

EGND

VB

FB

C2

GCM GA VLIM

8

5

RO1

RO2

HLIM

90

DLP

91

DLN

92

VLNVLP

99

7

Figure 51. Boyle Macromodel and Subcircuit

PSpice and Parts are registered trademarks of MicroSim Corporation.



MECHANICAL DATAD (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)0.244 (6,20)

0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)

1

14

0.014 (0,35)0.020 (0,51)

A

0.157 (4,00)0.150 (3,81)

7

8

0.044 (1,12)0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189(4,80)

(5,00)0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394(10,00)

0.386

0.004 (0,10)

M0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).D. Falls within JEDEC MS-012




MECHANICAL DATAFK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/D 10/96

28 TERMINAL SHOWN

B

0.358(9,09)

MAX

(11,63)

0.560(14,22)

0.560

0.458

0.858(21,8)

1.063(27,0)

(14,22)

ANO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342(8,69)

MIN

(11,23)

(16,26)0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)0.938

(28,99)1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)0.064 (1,63)

(7,80)0.307

(10,31)0.406

(12,58)0.495

(12,58)0.495

(21,6)0.850

(26,6)1.047

0.045 (1,14)

0.045 (1,14)0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

121314151618 17

11

10

8

9

7

5

432

0.020 (0,51)0.010 (0,25)

6

12826 27

19

21B SQ

A SQ22

23

24

25

20

0.055 (1,40)0.045 (1,14)

0.028 (0,71)0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a metal lid.D. The terminals are gold plated.E. Falls within JEDEC MS-004



MECHANICAL DATAJG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE

0.310 (7,87)0.290 (7,37)

0.014 (0,36)0.008 (0,20)

Seating Plane

4040107/C 08/96

5

40.065 (1,65)0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,20)0.355 (9,00)

0.015 (0,38)0.023 (0,58)

0.063 (1,60)0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification on press ceramic glass frit seal only.E. Falls within MIL-STD-1835 GDIP1-T8




MECHANICAL DATAPW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/E 08/96

14 PIN SHOWN

Seating Plane

1,20 MAX

1

A

7

14

0,19

4,504,30

8

6,206,60

0,30

0,750,50

0,25

Gage Plane

0,15 NOM

0,65 M0,10

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,10

8

4,90

5,10

14

6,60

6,404,90

5,10

16

7,70

20

7,90

24

9,60

9,80

28

0,150,05

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-153



MECHANICAL DATAU (S-GDFP-F10) CERAMIC DUAL FLATPACK

4040179/B 03/95

1.000 (25,40)

0.080 (2,03)

0.250 (6,35)

0.250 (6,35)

0.019 (0,48)

0.025 (0,64)

0.300 (7,62)

0.045 (1,14)

0.006 (0,15)

0.050 (1,27)

0.015 (0,38)

0.005 (0,13)

0.026 (0,66)

0.004 (0,10)

0.246 (6,10)

0.750 (19,05)

1 10

5 6

0.250 (6,35)0.350 (8,89)0.350 (8,89)

0.250 (6,35)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification only.E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA

PACKAGE OPTION ADDENDUM

www.ti.com 7-May-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

5962-9751101QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI -55 to 125 9751101QPATLV2442M

5962-9751102QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI -55 to 125 9751102QPATLV2442AM

TLV2442AID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2442AI

TLV2442AIDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)


TLV2442AIDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


TLV2442AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


TLV2442AIPW ACTIVE TSSOP PW 8 150 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TV2442

TLV2442AIPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TV2442

TLV2442AIPWR ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)


TLV2442AIPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)


TLV2442AMJGB ACTIVE CDIP JG 8 1 TBD Call TI Call TI -55 to 125 9751102QPATLV2442AM

TLV2442AQD ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2442A

TLV2442AQDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM V2442A

TLV2442AQPW ACTIVE TSSOP PW 8 150 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 2442AQ

TLV2442AQPWR ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 2442AQ

TLV2442CD ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 2442C

TLV2442CDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)


http://www.ti.com/product/TLV2442M?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/TLV2442AM?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/TLV2442A?CMP=conv-poasamples#samplebuy








http://www.ti.com/product/TLV2442AM?CMP=conv-poasamples#samplebuy





http://www.ti.com/product/TLV2442?CMP=conv-poasamples#samplebuy




Addendum-Page 2



Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)


Samples

TLV2442CDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


TLV2442CPW ACTIVE TSSOP PW 8 150 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV2442

TLV2442CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV2442

TLV2442ID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2442I

TLV2442IDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)


TLV2442IDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


TLV2442MJGB ACTIVE CDIP JG 8 1 TBD Call TI Call TI -55 to 125 9751101QPATLV2442M

TLV2442QPW ACTIVE TSSOP PW 8 150 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 2442Q

TLV2442QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 2442Q

TLV2442QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 2442Q

TLV2444AID ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)


TLV2444AIDG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)


TLV2444AIPW ACTIVE TSSOP PW 14 90 Green (RoHS& no Sb/Br)


TLV2444AIPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS& no Sb/Br)


TLV2444AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)


TLV2444AIPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)


TLV2444CD ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)


TLV2444CDG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)








http://www.ti.com/product/TLV2442M?CMP=conv-poasamples#samplebuy














Addendum-Page 3



Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)


Samples

TLV2444CDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)


TLV2444CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)


TLV2444CPW ACTIVE TSSOP PW 14 90 Green (RoHS& no Sb/Br)


TLV2444CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS& no Sb/Br)


TLV2444CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)


TLV2444CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)


TLV2444ID ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)


TLV2444IDG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)


TLV2444IDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)


TLV2444IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.













Addendum-Page 4

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV2442, TLV2442A, TLV2442AM, TLV2442M, TLV2444A :

• Catalog: TLV2442A, TLV2442

• Automotive: TLV2442-Q1, TLV2442A-Q1, TLV2442A-Q1, TLV2442-Q1, TLV2444A-Q1

• Military: TLV2442M, TLV2442AM

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

• Military - QML certified for Military and Defense Applications

http://focus.ti.com/docs/prod/folders/print/tlv2442a.html

http://focus.ti.com/docs/prod/folders/print/tlv2442.html

http://focus.ti.com/docs/prod/folders/print/tlv2442-q1.html

http://focus.ti.com/docs/prod/folders/print/tlv2442a-q1.html


http://focus.ti.com/docs/prod/folders/print/tlv2442-q1.html


http://focus.ti.com/docs/prod/folders/print/tlv2442m.html

http://focus.ti.com/docs/prod/folders/print/tlv2442am.html

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TLV2442AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV2442AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TLV2442AQPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TLV2442CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV2442IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV2442IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV2442QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TLV2442QPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TLV2444AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TLV2444CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TLV2444CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TLV2444IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TLV2444IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Apr-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV2442AIDR SOIC D 8 2500 340.5 338.1 20.6

TLV2442AIPWR TSSOP PW 8 2000 367.0 367.0 35.0

TLV2442AQPWR TSSOP PW 8 2000 367.0 367.0 35.0

TLV2442CDR SOIC D 8 2500 340.5 338.1 20.6

TLV2442IDR SOIC D 8 2500 340.5 338.1 20.6

TLV2442IDR SOIC D 8 2500 367.0 367.0 38.0

TLV2442QPWR TSSOP PW 8 2000 367.0 367.0 35.0

TLV2442QPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0

TLV2444AIPWR TSSOP PW 14 2000 367.0 367.0 35.0

TLV2444CDR SOIC D 14 2500 367.0 367.0 38.0

TLV2444CPWR TSSOP PW 14 2000 367.0 367.0 35.0

TLV2444IDR SOIC D 14 2500 367.0 367.0 38.0

TLV2444IPWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Apr-2016

Pack Materials-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.310 (7,87)0.290 (7,37)

0.014 (0,36)0.008 (0,20)

Seating Plane

4040107/C 08/96

5

40.065 (1,65)0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,16)0.355 (9,00)

0.015 (0,38)0.023 (0,58)

0.063 (1,60)0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification.E. Falls within MIL STD 1835 GDIP1-T8

www.ti.com

PACKAGE OUTLINE

C

TYP6.66.2

1.2 MAX

6X 0.65

8X 0.300.19

2X1.95

0.150.05

(0.15) TYP

0 - 8

0.25GAGE PLANE

0.750.50

A

NOTE 3

3.12.9

BNOTE 4

4.54.3

4221848/A 02/2015

TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGE

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153, variation AA.

18

0.1 C A B

54

PIN 1 IDAREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

(5.8)

0.05 MAXALL AROUND

0.05 MINALL AROUND

8X (1.5)8X (0.45)

6X (0.65)

(R )TYP

0.05

4221848/A 02/2015


SYMM

SYMM

LAND PATTERN EXAMPLESCALE:10X

1

45

8

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILSNOT TO SCALE

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(5.8)

6X (0.65)

8X (0.45)8X (1.5)

(R ) TYP0.05

4221848/A 02/2015


NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SYMM

SYMM

1

45

8

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:10X

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statementsdifferent from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for theassociated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designersremain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers havefull and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI productsused in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, withrespect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerousconsequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm andtake appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer willthoroughly test such applications and the functionality of such TI products as used in such applications.TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended toassist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in anyway, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resourcesolely for this purpose and subject to the terms of this Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specificallydescribed in the published documentation for a particular TI Resource.Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications thatinclude the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISETO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OFPRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated

http://www.ti.com/sc/docs/stdterms.htm

Rail-to-Rail Output Wide-Input-Voltage Dual … amplifiers from Texas Instruments. The common-mode...

Documents

Transcript of Rail-to-Rail Output Wide-Input-Voltage Dual … amplifiers from Texas Instruments. The common-mode...