Raggedstone4 User Manual Issue 1 - Intel · af5 0v 3.3v u9 27 ag13 0v 3.3v ag14 af6 0v 3.3v t8 28...

© Enterpoint Ltd. – Raggedstone4 Manual – Issue 1.1c 11.04.2014

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Raggedstone4 User Manual

Issue – 1.1c


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Kit Contents

You should receive the following items with your Raggedstone4 development kit:

1 - Raggedstone4 Board

2 - 4 Digit, 7 Segment LED display (fitted)

3 – PC mounting bracket

You will also need a Programming Cable – either Enterpoint's PROG4 cable or an

Altera USB blaster (or equivalent) with a suitable adapter e.g. Enterpoint PROG4

adapter.


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Contents

Kit Contents 2 Foreword 4 Trademarks 4 INTRODUCTION 5 RAGGEDSTONE4 MAIN FEATURES 6 POWER INPUTS AND PICKUPS 7 POWER REGULATORS 8 DIL HEADERS 9 SIL HEADERS 11 FPGA 13 OSCILLATORS 13 LEDS 14 USB 15 ETHERNET 16 MAC ADDRESS DEVICE 17 REAL TIME CLOCK 17 PUSH BUTTON SWITCHES 18 BATTERY 18 DDR3 MEMORY 19 SATA 20 PCIE 21 SPI FLASH 22 MEMORY CARD HOLDER 23 HPS JUMPER SETTINGS 24 CONFIGURING RAGGEDSTONE4 27 MECHANICAL 30 Medical and Safety Critical Use 31 Warranty 31 Support 31


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Foreword

PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN

OR POWERING UP YOUR RAGGEDSTONE4 BOARD.

PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN

THIS MANUAL.

Trademarks

Cyclone

TMV, QuartusII, Altera are the registered trademarks of Altera Inc, San Jose, California,

US.

Raggedstone4 is a trademark of Enterpoint Ltd.

Figure 1 – Raggedstone4 Board


5

Introduction

Welcome to your Raggedstone4 board. Raggedstone4 is Enterpoint’s CycloneTMV SOC PCIE development board – a member of the very popular Raggedstone series of FPGA development

boards

The aim of this manual is to assist in using the main features of Raggedstone4.

There are features that are beyond the scope of the manual. Should you need to use these features

then please email [email protected] for detailed instructions.

Raggedstone4 comes in a single variant based on a 5CSXF6C6C6U23C8N CycloneTM

V. Should

you need a more powerful or industrial or automotive grade FPGA fitted please contact Enterpoint

sales for a quote.

In addition Raggedstone4 is supported by a wide range of add-on modules. Some examples of

these include:

ADC 7927 MODULE

LED DOT MATRIX MODULE

BUTTONS/SWITCHES/SATA/MEMORY MODULE

RS232 AND RS485 HEADER MODULES

DP83816 ETHERNET MODULE

SD CARD MODULE

IDE/5V TOLERANT CPLD MODULE

USB MODULE

D/A CONVERTER MODULE

ADV7202 MODULE

LTC2248 ADC MODULE

MICTOR CONNECTOR MODULE

IDT5V19EE901 CLOCK MODULE

OPTOISOLATOR MODULE

NAND FLASH MODULE

OVM 7690 CAMERA MODULE

KSZ9021RLGIGABIT PHY MODULE

We can also offer custom DIL Header modules should you require a function not covered by our

current range of modules. Typical turn around for this service is 6-8 weeks depending upon quantity

ordered and availability of components.

mailto:[email protected]


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Raggedstone4 Main Features

Figure 2 – Raggedstone4 MAIN FEATURES


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Power Inputs and Pick-ups

Raggedstone4 is powered either from the PCIe edge connector, or from a 12V power supply via the

jack socket or the disk drive connector.

The 12V input to Raggedstone4 is regulated for the supplies to the FPGA and Peripherals. These

regulators produce 0.675V, 1.1V,1.2V, 1.35V, 2.5V, 3.3V and 5V. These voltages can be monitored

on test points as shown in fig.3 below.

On Raggedstone4 there are 34 header pins with 3.3V and 0V available on each side of the board for

users to access power for their own add-on circuitry. These pins are arranged on a 0.1inch grid to

enable users to plug in their own stripboard designs.

The maximum current that can be delivered into Raggedstone4 from the PCIE connector has been

limited by a resettable fuse to a maximum current of 2.6A at 12v. This limit should be considered

when adding user circuitry onto the header pins. If more current is drawn the resettable fuse will cut

the supply to the board, if this happens the power supply must be switched off and time given for

the fuse to reset, which occurs when the fuse has cooled and reconnected its internal contacts. This

typically takes 1-2 seconds. If more than 2.6A is required you should connect 12v using the disk

drive connector J13 or the Jack socket J9. The current drawn through J13 or J9 is limited by a 7A

fast blow fuse (Littlefuse series 154).

Figure 3 – Raggedstone4 Power Supply Features


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Power Regulators

Raggedstone4 has a power backbone based on nine predominately switching regulators.

The structure of the regulator circuitry has been designed to comply with the CycloneV power

sequencing requirements and includes two power switches (U21 and U25).

U27 is a Micrel MIC26950 regulator which provides 12A maximum at 3.3V.

U22 is an ON Semiconductor MC78M05CDTX which provides 5V for U27.

U2 is a Texas Instruments TPS54240 which provides 5V for the USB Host option.

U8 is a Diodes Inc AP2171 Power switch controlling 5V for the USB Host option.

U21 is a Texas Instruments TPS22965DSGT power switch which switches 3.3V to the

CycloneTMV IO.

U24 is an Enpirion EN6347QI which provides a maximum of 4A at 2.5V for the CycloneTMV

VCCAUX, VCCPLL_HPS, VCCA_PLL, and VCCH_GXBL rails.

U26 is an Enpirion EN6347QI which supplies 1.35V to the DDR3 and associates CycloneTMV IO.

U25 is a Texas Instruments TPS22965DSGT power switch which switches the 1.35V to the DDR3

and associated CycloneTMV IO

U6 is an Enpirion EP5388QI regulator supplying 1.2V to the Ethernet Phy device.

U1 is An Enpirion EN6360QI which provides the 1.1V core voltage to the CycloneTMV.

U18 is a Diodes Inc AP7173 linear regulator supplying 1.1V for the CycloneTMV transceiver

GXBL rail.

U17 is a Texas Instruments TPS51200 push-pull regulator that supplies 0.675V to the DDR3 for its

reference voltage.

WARNING – THE REGULATORS MAY BECOME HOT IN NORMAL

OPERATION ALONG WITH THE BOARDS THERMAL RELIEF. PLEASE

DO NOT TOUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR

THESE DEVICES WHILST THE RAGGEDSTONE4 BOARD IS IN

OPERATION.

Figure 4 – Raggedstone4 Power Regulators and Power Switches


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DIL Headers

The DIL Headers provide a simple mechanical and electrical interface for add-on modules. The

connectors on this header are on a 0.1inch, 2.54mm, pitch and allow either custom modules or strip

board to be fitted. The headers have a row of permanent positive power sockets (3.3V) to the left of

JL2 and JR2 and a row of permanent GND (0V) sockets to the right of the JL1 and JR1.

Voltages outside the range 0V to 3.3V must not be applied to the DIL headers. The CycloneTM

V

has an absolute maximum IO input voltage of 3.7V. The connections between the DIL the

headers and the FPGA are shown below:

LEFT DIL HEADER RIGHT DIL HEADER

JL1 JL2 PIN JR1 JR2

AA19 0V 3.3V W21 1 Y24 0V 3.3V AA24

AA18 0V 3.3V W20 2 W24 0V 3.3V AA23

Y17 0V 3.3V AA20 3 AB26 0V 3.3V AC22

Y18 0V 3.3V Y19 4 AA26 0V 3.3V AC23

Y15 0V 3.3V V16 5 AE24 0V 3.3V AF27

AA15 0V 3.3V V15 6 AE23 0V 3.3V AF28

V12 0V 3.3V W14 7 AG23 0V 3.3V AG28

W12 0V 3.3V V13 8 AF23 0V 3.3V AH27

D12 0V 3.3V U14 9 AF22 0V 3.3V AF25

C12 0V 3.3V U13 10 AF21 0V 3.3V AG25

E11 0V 3.3V Y13 11 AF20 0V 3.3V AG24

D11 0V 3.3V AA13 12 AG20 0V 3.3V AH24

E8 0V 3.3V Y11 13 AG19 0V 3.3V AF17

D8 0V 3.3V AA11 14 AH19 0V 3.3V AG16

T11 0V 3.3V AD5 15 AH17 0V 3.3V AE20

U11 0V 3.3V AE6 16 AH16 0V 3.3V AD20

W8 0V 3.3V AF7 17 AD23 0V 3.3V AG18

Y8 0V 3.3V AG6 18 AE22 0V 3.3V AH18

AA4 0V 3.3V AG8 19 AH23 0V 3.3V AD17

AB4 0V 3.3V AH7 20 AH22 0V 3.3V AE17

AC4 0V 3.3V AG9 21 AE19 0V 3.3V AD11

AD4 0V 3.3V AH8 22 AD19 0V 3.3V AE11

AE4 0V 3.3V T13 23 AF11 0V 3.3V AG15

AF4 0V 3.3V T12 24 AF10 0V 3.3V AH14

AH3 0V 3.3V AG5 25 AF15 0V 3.3V AE12

AH2 0V 3.3V AH4 26 AE15 0V 3.3V AD12

AF5 0V 3.3V U9 27 AG13 0V 3.3V AG14

AF6 0V 3.3V T8 28 AF13 0V 3.3V AH13

AH6 0V 3.3V V11 29 AD10 0V 3.3V AG11

AH5 0V 3.3V W11 30 AE9 0V 3.3V AH11

AE7 0V 3.3V Y5 31 AG10 0V 3.3V AF26

AF8 0V 3.3V Y4 32 AH9 0V 3.3V AH26

AE8 0V 3.3V V10 33 AH12 0V 3.3V AG21

AF9 0V 3.3V Y16 34 AB25 0V 3.3V AH21


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Except for the signals shown in yellow above, the signals on the DIL headers are arranged in

LVDS pairs and routed such that the trace lengths approximately match and skew is minimised

within pair. Adjacent LVDS_P and LVDS_N form the matched pair at the DIL Header and the

CycloneTM

V FPGA. For example AA19 and AA18 form one pair.

All LVDS pairs can be used as general inputs/outputs from the CycloneTM

V.

Figure 5 – Raggedstone4 DIL Headers


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SIL Headers

Figure 6 – Raggedstone4 SIL Headers

The two 8-pin SIL headers on Raggedstone4 are arranged as a pair. They usually support the LTC-

4627JR 4-digit 7-segment display (U13); however the display can be removed to make these pins

available to the user. Voltages outside the range 0V to 3.3V must not be applied to the SIL headers.

The CycloneTM

V has an absolute maximum IO input voltage of 3.7V. The vertical distance

between the upper and lower pins is 0.4inch (10.2mm), and the horizontal pitch is 0.1inch

(2.54mm).

The headers have 13 connections to an I2C IO expander type NXP PCAL9555AHF (U15). For

more information see http://www.nxp.com. The IO expander has 16 IO which are connected to the

7-segment display and 3 LEDs. Eight of the 13 connections to the display have series 470ohm

current-limiting resistors. This should be taken into account if this header is used for other

purposes. The connections between U13 and the IO expander are shown below:

SIGNAL NAME PCAL9555 PIN 7-SEGMENT

DISPLAY PIN

LED7SEG1 10 1

LED7SEG2 11 2

LED7SEG3* 5 3

LED7SEG4 12 4

LED7SEG5* 6 5

LED7SEG6 13 6

LED7SEG7* 7 7

LED7SEG8 14 8

http://www.nxp.com/


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LED7SEG9* 4 16

LED7SEG10* 3 15

LED7SEG11* 2 14

LED7SEG12* 1 13

LED7SEG14* 8 11

* connection via series 470ohm resistor.

The IO expander connects to the CycloneTM

V HPS on the pins shown below:

PCAL9555 PIN SIGNAL NAME CycloneTM

V PIN

19 I2C1_SCL C18

20 I2C1_SDA A19

22 EXPANDER_INT_N J18


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FPGA

Raggedstone4 supports CycloneTM

V devices in the UBGA672 package. Raggedstone4 is normally

available with the 5CSXF6C6C6U23C8N fitted, which has the following features:

110,000 logic elements

112 Variable-precision DSP Blocks

5140 10K BlockRAM

Dual ARMCortex-A9MPCore Processor

2 PCIe Hard IP Blocks

6 3 Gbps Transceivers

1 FPGA Hard Memory Controller

1 HPS Hard Memory Controller

Should you have an application that needs an alternative device fitted please contact sales for a

quote at [email protected]

Oscillators

Raggedstone4 has four fixed frequency ASEM oscillators:

1. A 25MHz oscillator X4 connects to the CLKUSR pin (U10) and controls the configuration rate.

2. A 25MHz oscillator X2 connects to the HPS_CLK1 pin (E20) and the HPS_CLK2 pin (D20).

3. A 25MHz oscillator X3 connects to the Ethernet PHY on pin 60.

4. A 24MHz oscillator X1 connects to the USB OTG Controller on pin 28.

The CycloneTM

V has Digital Clock Multipliers (DCMs) to produce multiples, divisions and phases

of clock signals. Please consult the CycloneTM

V datasheet available from the Altera website at

http://www.Altera.com if multiple clock signals are required.

Figure 7 – Raggedstone4 Oscillators

http://www.xilinx.com/


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LEDs

On Raggedstone4 there are 5 LEDS. LED1 (Green) is situated on the top left corner of the board

and indicates the presence of the 3.3v power rail. It is not available for other uses. LEDs 2 to 5,

which are situated the top of the board immediately to the right of the SATA connector and above

JR1, are user LEDs.

LED5 (Red) is connected (via a 470ohm resistor) to the FPGA on pin AG26.

LEDs 2 to 4 are connected to an I2C IO expander type NXP PCAL9555AHF (U15):

LED2 LED3 LED4

PCAL9555AHF PIN 17 16 15

COLOUR BLUE GREEN YELLOW

Figure 8 – Raggedstone4 LEDs

PCAL9555 PIN SIGNAL NAME CycloneTM

V PIN

19 I2C1_SCL C18

20 I2C1_SDA A19

22 EXPANDER_INT_N J18


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USB

Figure 9 – Raggedstone4 USB

The USB interface on the Raggedstone4 is achieved using a USB3300 OTG PHY. The datasheet

and drivers for this device are available from http://www.smsc.com. This device can operate as a

USB2.0 Host, Device or OTG PHY.

The USB3300 is connected to the CycloneTM

V HPS. The connections between the USB device and

the CycloneTM

V are shown below:

USB3300 PIN SIGNAL

FUNCTION

SIGNAL

NAME

CYCLONEV

PIN

24 DATA0 USB0 C10

23 DATA1 USB1 F5

22 DATA2 USB2 C9

21 DATA3 USB3 C4

20 DATA4 USB4 C8

19 DATA5 USB5 D4

18 DATA6 USB6 C7

17 DATA7 USB7 F4

13 STP USB8 C5

11 NXT USB9 D5

12 DIR USB10 E5

14 CLKOUT USB11 G4

9 RESET USB12 AE26*

*The USB Reset pin is connected to the CycloneTM

V via jumper J2 and an STM6719 reset

supervisor U3. A 2mm jumper should be fitted to the left of J2 for the USB to be reset from the

CycloneTM

V (normal jumper setting) and to the right of J2 to achieve a manual USB Reset.

http://www.smsc.com/


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Ethernet

Raggedstone4 has one Micrel KSZ9021RL 10/100/1000Mbps Ethernet PHY fitted with an RJ45

Magnetically isolated socket. For further information and the component datasheet please refer to

www.micrel.com. The connections between the KSZ9021RL devices and the CycloneTM

V are

shown in the table below. They are arranged as four transmit and four receive signals and a 6 signal

support bus, and connect to the HPS side of the CycloneTM

V. The KSZ9021RL supports RGMII

Ethernet signalling.

FUNCTION(SIGNAL NAME)

KSZ9021RL PIN

PORT1

CycloneTM

V PIN

RXD0 (ETH_RX0) 42 A14


RXD2 (ETH_RX2) 38 C15


TXD0 (ETH_TX0) 24 A16

TXD1 (ETH_TX1) 25 J14

TXD2 (ETH_TX2) 26 A15

TXD3 (ETH_TX3) 27 D17

TX_EN (ETH_SUPP1) 33 A12

GTX_CLK (ETH_SUPP2) 32* J15

RX_DV (ETH_SUPP3) 43 J13

RX_CLK (ETH_SUPP4) 46* J12

MDC (ETH_SUPP5) 48 A13

MDIO (ETH_SUPP6) 49 E16

http://www.micrel.com/


17

MAC address device

Raggedstone4 has an I2C MAC address device U5, type 24AA035E64T-I/OT. Further information

about this device can be obtained from http://www.microchip.com. It connects to the I2C0 bus

which is accessed by the CycloneTM


Further information about this device can be obtained from http://www.microchip.com.

Real time clock Raggedstone4 has a PCF8523TK real time clock device which connects to the I2C1 bus to the

CycloneTM


PCF8523TK PIN SIGNAL NAME CycloneTM

V PIN

6 I2C1_SCL K18

5 I2C1_SDA A21

Further information about this device can be obtained from http://www.nxp.com.

It is necessary for a battery to be fitted to the board for the Real Time Clock to retain its

setting when the board is powered down.

24AA035E64T PIN SIGNAL NAME CycloneTM

V PIN

1 I2C0_SCL C18

3 I2C0_SDA A19

http://www.microchip.com/http://www.microchip.com/http://www.nxp.com/


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Push Button Switches Raggedstone4 has three tactile push-button switches.

SW4 is used to reset the CycloneTM

V HPS. It connects to the CycloneTM

V pin A23 via an

STM6719 reset supervisor U17.

SW5 and SW4 connect to GPIO on the CycloneTM

V HPS. To use these switches it is necessary to

set the IO pins connected to the switches to have a pull up resistor setting in the constraints file.

Any switch pressed, or made, will then give a LOW signal at the FPGA otherwise a HIGH is seen.

The two push button switches are connected to the following IO pins.

SW6 (PB2) SW5 (PB3)

A19 A4

Raggedstone4 also has 3 user switches which are elements 1 to 3 of the 4-element DIP switch SW1.

These connect to CycloneTM

V HPS GPIO as shown below:

SW1 ELEMENT1 SW1 ELEMENT2 SW1 ELEMENT3

Y28 (GPIO8) P26 (GPIO5) R28 (GPIO4)

Battery

The Raggedstone4 has a battery holder which is available to provide battery backup to the

CycloneTM

V. It is connected to the CycloneTM

V on pin D7. The battery holder accepts a 3V Lithium

battery size CR1220 or equivalent. A jumper must be fitted to J5 to allow the CycloneTM

V to Exit

Reset. If a battery is present the 2mm jumper should be fitted to the left of J5. If a battery is not

fitted the jumper should be fitted to the right of J5. The battery needs to be fitted if the Real-time

clock is to maintain its time when the board is powered down.

Figure 10 – Raggedstone4 Switches and Battery Holder


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DDR3

Raggedstone4 has two 4GBIT DDR3 Micron MT41J64M256LA devices as standard. These devices

are organised a a single 32 bit wide memory interface with a common address bus. This device is

supported by the hard core memory controller that is in the CycloneTM

V HPS.

The DDR3 has 15 address lines and 32 data lines to address all the available memory, which can be

accessed at speeds of 1.87ns. More details of the DDR3 can be found in

http://download.micron.com/pdf/datasheets/dram/ddr3/1Gb_DDR3_SDRAM.pdf.

The DDR3 has the following connections to the CycloneTM

V:

DDR3

FUNCTION HPS PIN

DDR3

FUNCTION HPS PIN

DDR3

FUNCTION HPS PIN

DDR3_A0 C28 DDR3_CKE L28 DDR3_DQ21 N27

DDR3_A1 B28 DDR3_CK# N20 DDR3_DQ22 R27

DDR3_A2 E26 DDR3_CK N21 DDR3_DQ23 V27

DDR3_A3 D26 DDR3_DQ0 J25 DDR3_DQ24 R26

DDR3_A4 J21 DDR3_DQ1 J24 DDR3_DQ25 R25

DDR3_A5 J20 DDR3_DQ2 E28 DDR3_DQ26 AA28

DDR3_A6 C26 DDR3_DQ3 D27 DDR3_DQ27 W26

DDR3_A7 B26 DDR3_DQ4 J26 DDR3_DQ28 R24

DDR3_A8 F26 DDR3_DQ5 K26 DDR3_DQ29 T24

DDR3_A9 F25 DDR3_DQ6 G27 DDR3_DQ30 Y27

DDR3_A10 A24 DDR3_DQ7 F28 DDR3_DQ31 AA27

DDR3_A11 B24 DDR3_DQ8 K25 DDR3_DM0 G28

DDR3_A12 D24 DDR3_DQ9 L25 DDR3_DM1 P28

DDR3_A13 C24 DDR3_DQ10 J27 DDR3_DM2 W28

DDR3_A14 G23 DDR3_DQ11 J28 DDR3_DM3 AB28

DDR3_BA0 A27 DDR3_DQ12 M27 DDR3_DQS0 R17

DDR3_BA1 H25 DDR3_DQ13 M26 DDR3_DQS0# R16

DDR3_BA2 G25 DDR3_DQ14 M28 DDR3_DQS1 R19

DDR3_ODT D28 DDR3_DQ15 N28 DDR3_DQS1# R18

DDR3_CS0# L21 DDR3_DQ16 N24 DDR3_DQS2 T19

DDR3_RAS# A25 DDR3_DQ17 N25 DDR3_DQS2# T18

DDR3_WE# E25 DDR3_DQ18 T28 DDR3_DQS3 U19

DDR3_CAS# A26 DDR3_DQ19 U28 DDR3_DQS3# T20

DDR3_RST# V28 DDR3_DQ20 N26

The signals shown shaded in yellow are terminated using suitable arrangements of resistors.

http://download.micron.com/pdf/datasheets/dram/ddr3/1Gb_DDR3_SDRAM.pdf


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SATA

Raggedstone4 has a SATA connector, J12, which is connected to a high-speed transceiver on the

CycloneTM

V. A DSC1123AI1-150.0000T device, X5, is used to provide the SATA Clock. The

connections between the SATA Clock, the SATA connector and the CycloneTM

V are shown below

(omitting series capacitors):

SATA CONNECTOR

J12 PIN

CycloneTM

V PIN

J12 PIN 2 F2

J12 PIN 3 F1

J12 PIN 5 D1

J12 PIN 6 D2

CLOCK+ P8

CLOCK- N8

Figure 11 – Raggedstone4 DDR3 and SATA


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PCIe

The Raggedstone4 has a x4 PCIe Interface. The pin out of the CycloneTM

V FPGA has been chosen

such that the PCI interface follows the pinout for the Altera CycloneTM

V hard core for PCIe which

can be generated automatically by the Altera Megafunction Wizard. The connections between the

PCIe connector and the FPGA are shown below.

SIGNAL

NAME

PCIE CONNECTOR

PIN

FPGA PIN

PCIE_CLK_P A13 V5

PCIE_CLK_N A14 V4

PCIE_L0_TX_P A16 AD2

PCIE_L0_TX_N A17 AD1

PCIE_L0_RX_P B14 AF2

PCIE_L0_RX_N B15 AF1

PCIE_L1_TX_P A21 Y2

PCIE_L1_TX_N A22 Y1

PCIE_L1_RX_P B19 AB2

PCIE_L1_RX_N B20 AB1

PCIE_L2_TX_P A25 V2

PCIE_L2_TX_N A26 V1

PCIE_L2_RX_P B23 T2

PCIE_L2_RX_N B24 T1

PCIE_L3_TX_P A29 M2

PCIE_L3_TX_N A30 M1

PCIE_L3_RX_P B27 P2

PCIE_L3_RX_N B28 P1

PCIE_PRESENT#1 A1 *

PCIE_PRESENT#2 B17 *

PCIE_PRESENT#4 B31 *

*PCIE presence signals 1 and 4 are connected together. Presence signal2 is not connected.


22

SPI Flash Memory

The Micron N25Q256A13EF840E SPI flash memory device configures the FPGA when it is

powered providing a suitable bitstream is programmed into the device. The N25Q256A has a

capacity of 256Mbits with a single configuration bitstream for Raggedstone4 taking 56.1Mbits .

Any remaining space can be used for alternative configurations or code and data storage. After

configuration the SPI Flash can be accessed via the following pins of the FPGA:

N25Q256A FUNCTION N25Q256A PIN SIGNAL CYCLONEV PIN

CCLK 6 QUAD1 C14*

Q/MISO1 2 QUAD4 A6

D/MISO0 5 QUAD3 A8

WP#/MISO2 3 QUAD5 A7

HOLD/MISO3 7 QUAD6 J16

CS# 1 QUAD2 A6

*via series 22ohm resistor

Figure 12 – Raggedstone4 PCIE and SPI Flash Memory


23

Memory card holder

The primary purpose of the MICRO SDCARD Holder on Raggedstone4 is to hold the operating

system (e.g. Linux, Android) from which the ARM processor will run. It is connected to HPS inputs

of the CycloneTM

V. Alternatively the SDCARD can be used for data storage. To use this socket in

a design you may need to obtain a license from the SD Association at http://www.sdcard.org/home/.

The connections between the Memory Card Holder J16 and the CycloneTM

V are shown below:

FUNCTION SIGNAL PIN

DATA 0 SDCARD2 C13

DATA 1 SDCARD1 B6

DATA 2 SDCARD3 B11

DATA 3 SDCARD4 B9

CMD SDCARD5 D14

CLK SDCARD6 B8

POWER_ON_N SDCARD7 A5

CARD PRESENT SDCARD8 B12

The POWER_ON_N pin must be set LOW for power to be supplied to the Memory Card Socket.

Figure 13 – Raggedstone4 PCIE and SPI Flash Memory

http://www.sdcard.org/home/


24

HPS Configuration Switch and Jumper Settings

There are 3 jumper headers and two 4-element switches on Raggedstone4 which control functions

of the CycloneTM

V HPS.

Figure 14 – Raggedstone4 Jumper Headers

1. Power-on Reset Jumper J7 is a 3 pin header which is connected between pin K18 of the Cyclone

TMV HPS (a GPIO) and the

HPS nPOR pin H19 of the CycloneTM

V HPS via an STM6719 Reset Supervisor. The purpose of

this arrangement is to allow the HPS to initiate its own reset. The default setting of the 2mm jumper

on J7 is to the left. Fitting the jumper to the right of J7 will initiate a manual Power-on reset. If this

jumper setting is left fitted the HPS will never exit RESET.

2. CSEL (Clock select) switch

Switch SW3 is used to set CSEL0 and CSEL1 to select the range of the clock provided to the HPS

on the CLK1 pin:

CSEL0 CSEL1 OSC1_CLK RANGE PLL MODE

0 0 10-50MHz BYPASSED

1 0 10-12.5MHz LOCKED

0 1 12.5-25MHz LOCKED

1 1 25-50MHz LOCKED

The frequency of the oscillator connected to the HPS clock on Raggedstone4 is 25MHz, so any

setting of CSEL(0:1) except for 10 should be acceptable.


25

Figure 15 Raggedstone 4 Configuration switches.

CSEL0 is set by the lower 2 elements of SW3. If element 1 is ON CSEL0 will be ‘1’. If element 2

is ON CSEL0 will be ‘0’.

CSEL1 is set by the upper 2 elements of SW3. If element 3 is ON CSEL0 will be ‘1’. If element 4

is ON CSEL0 will be ‘0’.

With the switches set as shown in Figure 15 above CSEL(0:1) is set to 11.

3. BSEL (Boot source select) switch

There are three BSEL (Boot Select) inputs to the HPS. BSEL0 is fixed at '1' since Raggedstone4 has

no 1.8V devices. Switch SW2 is used to set BSEL2 and BSEL1.

BSEL0 BSEL1 BSEL2 BOOT DEVICE

0 0 0 RESERVED

1 0 0 FPGA (HPS TO FPGA BRIDGE)

0 1 0 1.8V NAND FLASH MEMORY

1 1 0 3.3V NAND FLASH MEMORY

0 0 1 1.8V SD/MMC FLASH MEMORY WITH EXTERNAL TRANSCEIVER

1 0 1 3.3V SD/MMC FLASH MEMORY WITH INTERNAL TRANSCEIVER

0 1 1 1.8V SPI OR QUAD SPI FLASH MEMORY

1 1 1 3.3V SPI OR QUAD SPI FLASH MEMORY

BSEL1 is set by the lower 2 elements of SW3. If element 1 is ON BSEL1 will be ‘1’. If element 2

is ON BSEL1 will be ‘0’.

BSEL2 is set by the upper 2 elements of SW3. If element 3 is ON BSEL2 will be ‘1’. If element 4

is ON BSEL2 will be ‘0’.

SW3

SW2

Element 1

Element 1

SW1

Element 4


26

The default setting for BSEL2 and BSEL1 is with SW2 elements 1 and 3 ON and elements 2 and 4

OFF so that the HPS boots from the 3.3V Quad SPI flash memory.

4. Battery jumper J5.

A jumper must be fitted to J5 to allow the CycloneTM

V to Exit Reset. If a battery is present the 2mm

jumper should be fitted to the left of J5. If a battery is not fitted the jumper should be fitted to the

right of J5.

Figure 16 Detail of J5

5. MSEL0 switch SW1 Element 4

The configuration pins MSEL(4:0) control the configuration scheme for the Cyclone V device.

Raggedstone4 uses the Active Serial (AS) configuration scheme, for which the MSEL(4:0) settings

are 10010 (Fast) or 10011 (Standard). Raggedstone4 is normally shipped with MSEL0 hard wired

to ‘1’ via a 240 ohm resistor R13, in which case SW1 element4 must be OFF. If a user requires

MSEL0 =’0’ then SW1 element 4 should be set ON.


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Configuring Raggedstone4

The configuration of the FPGA, HPS and SPI Flash on Raggedstone4 is achieved using the JTAG

connections. There are two JTAG connectors on Raggedstone4. An adapter will be required if you

use the Altera USB Blaster.

Figure 17 Raggedstone4 JTAG connectors (left) and adapter (right)

Each JTAG connector has a layout as follows:

Top edge of board

GND GND GND GND GND GND GND

NC NC TDI TDO TCK TMS 3V3

The JTAG TRST signal for the CycloneTM

V HPS is available on a test point between the two JTAG

connectors:

Figure 18 Location of testpoint for TRST signal

In order to configure the 5CSXF6C6C6U23C8N CycloneTM

V you will need QuartusII version

13.1 or later.

Open the QuartusII programmer (found under the Tools Menu of QuartusII). Select your

programming cable using the Hardware Setup feature. The Enterpoint PROG4 cable is detected as

an Altera USB Blaster. Use an adapter if necessary to convert from the 10 Pin Altera connector to

the RS4 14 Pin connector. See below for correct orientation of adapter:

1. Configuring the HPS.

Raggedstone4 will be shipped with a default configuration in the HPS which will enable the

peripherals connected to the HPS on Raggedstone4 to be accessed. It is necessary to load a minimal

configuration into the HPS before the FPGA can be configured. If you wish to change the default

configuration you will need use the Altera SoC EDS Command shell, found in your Altera

Directory:

HPS TRST SIGNAL


28

Figure 19 Locating the Altera SoC EDS Command Shell

Open the command shell and change directory to the location of your files.

The following files will be required (your file names may differ) :

Preloader-mkpimage.bin, Uboot.bin

From the command prompt program the 2 files as follows: quartus_hps –c usb-blaster –o p –a0x00000 preloader-mkpimage.bin

You should verify the file as follows: quartus_hps –c usb-blaster –o v –a0x00000 preloader-mkpimage.bin

Program the second file as follows: quartus_hps –c usb-blaster –o p –a0x60000 uboot.bin

And verify it: quartus_hps –c usb-blaster –o v –a0x60000 uboot.bin

It should now be possible to boot the Raggedstone4 to Linux.

2. Configuring the FPGA and the SPI Flash memory

It is necessary to configure the FPGA before the SPI flash memory device can be detected. Plug

your programming cable into the upper JTAG connector marked ‘FPGA JTAG’. Open the

QuartusII programmer, check that your programming cable has been detected correctly, then choose

Autodetect. The screen below should appear:

Figure 20 Quartus II programmer screen showing CycloneV


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Double click the FPGA File and select your .sof file. Tick the Program/Configure check box to

enable the Start Button and press Start to program the FPGA.

Once Complete (Should only take a few seconds) press the Auto Detect button.

The SPI flash device should now be shown attached to the FPGA:

Figure 21 Quartus II programmer screen showing CycloneVand flash memory.

Double click on the EPCQ256 File and select your programming file (.jic). Tick the box in the

'Program/Configure' column for the Flash memory. Select the icon representing the flash memory

and choose ‘Start’ to load your program into the device. A green bar in the top left of the

programmer screen shows the progress. The programming operation will take some time (at least 3

or 4 minutes).


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Mechanical Information

All dimensions are shown in millimetres.

Figure 22– Raggedstone4 Dimensions

Figure 23– Raggedstone4 top edge view (3D model)

The maximum height of the components on Raggedstone4 is approximately 11.3mm (height of

Ethernet connector). The PCB thickness is 1.6mm.

All measurements shown above are approximate and subject to manufacturing tolerances.

If you need any further mechanical information please contact us. Contact information is shown on

page 25 of this manual.


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Medical and Safety Critical Use

Raggedstone4 boards are not authorised for the use in, or use in the design of, medical or other

safety critical systems without the express written person of the Board of Enterpoint. If such use is

allowed the said use will be entirely the responsibility of the user. Enterpoint Ltd will accepts no

liability for any failure or defect of the Raggedstone4 board, or its design, when it is used in any

medical or safety critical application.

Warranty

Raggedstone4 comes with a 90 day return to base warranty. Do not attempt to solder connections

to the Raggedstone4. Enterpoint reserves the right not honour a warranty if the failure is due to

soldering or other maltreatment of the Raggedstone4 board.

Outside warranty Enterpoint offers a fixed price repair or replacement service. We reserve the

right not to offer this service where a Raggedstone4 has been maltreated or otherwise deliberately

damaged. Please contact support if need to use this service.

Other specialised warranty programs can be offered to users of multiple Enterpoint products.

Please contact sales on [email protected] if you are interested in these types of warranty,

Support

Enterpoint offers support during normal United Kingdom working hours 9.00am to 5.00pm. Please

examine our Raggedstone4 FAQ web page and the contents of this manual before raising a support

query. We can be contacted as follows:

Telephone - ++44 (0) 121 288 3945 Email - [email protected]
mailto:[email protected]:[email protected]

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