r09-12
1
|''||||'|''||'''|''| Subject Code:C3802 M. Tech- I Semester [R09] Regular/Supplementary Examinations, April -2013 VLSI TECHNOLOGY & DESIGN (Com to DECS,DIP,DSCE,ECE,ES,SSP,VLSI&ES,ES&VLSI,VLSID&VLSD,VLSI and C&SP) Time: 3 Hours Max Marks: 60 Answer any FIVE questions All questions carry EQUAL marks 1. (a) With neat sketches explain the formation of the inversion layer in P-channel Enhancement MOSFET. (b) An NMOS Transistor is operated in the triode region with the following parameters VGS = 4V ; V tn = 1V ; V DS = 2V ; W/L = 100; nCox = 90 A/V. Find its drain current and drain source resistance. 2. (a) Determine the Pull-up to Pull-down ratio for an nMOS inverter driven through one or more pass transistors. (b) Draw a simple BiCMOS inverter circuit diagram and explain its operation 3. (a) What are the different scalable design rules? Explain any one of them. (b) Design and draw a stick diagram for two input n-MOS NAND and NOR gates. 4. (a) What is meant by switch logic? Discuss about alternative gate circuits. (b) Explain how to determine resistive and inductive interconnect delays of logic circuits. 5. (a) What are the various simulators used for combinational logic design? Explain their need. (b) Explain how the gate placement effects load capacitance in fan-out of combinational logic. 6. (a) Explain the technology independent and technology dependant strategies of power optimization used in sequential systems. (b) Write notes on clocking disciplines. 7. (a) Explain the design validations in the floor planning methods. (b) Describe the Placement and routing techniques used in floor planning. 8. Write short notes on the following: (a) Layout Synthesis. (b) Hardware/Software Co-Design. ******
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Su
bje
ct C
od
e:C
38
02
M.
Tec
h-
I S
em
este
r [R
09
] R
egu
lar/
Su
pp
lem
enta
ry E
xa
min
ati
on
s, A
pri
l -2
01
3
VL
SI
TE
CH
NO
LO
GY
& D
ES
IGN
(C
om
to
DE
CS
,DIP
,DS
CE
,EC
E,E
S,S
SP
,VL
SI&
ES
,ES
&V
LS
I,V
LS
ID&
VL
SD
,VL
SI
and
C&
SP
)
Tim
e: 3
Ho
urs
Ma
x M
ark
s: 6
0
An
swer
an
y F
IVE
qu
esti
on
s
All
qu
esti
on
s ca
rry
EQ
UA
L m
ark
s
����
1.
(a)
W
ith
nea
t sk
etch
es e
xp
lain
th
e fo
rmat
ion
of
the
inv
ersi
on
layer
in
P-c
han
nel
En
han
cem
ent
MO
SF
ET
.
(b)
An
NM
OS
Tra
nsi
sto
r is
op
erat
ed i
n t
he
trio
de
regio
n w
ith
th
e fo
llo
win
g p
aram
eter
s V
GS
=
4V
; V
tn =
1V
; V
DS =
2V
; W
/L =
10
0; �
nC
ox
= 9
0 �
A/V
. F
ind
its
dra
in c
urr
ent
and
dra
in
so
urc
e re
sist
ance
.
2.
(a)
Det
erm
ine
the
Pu
ll-u
p t
o P
ull
-do
wn
rat
io f
or
an n
MO
S i
nv
erte
r d
riv
en t
hro
ugh
on
e o
r m
ore
p
ass
tran
sist
ors
.
(b
) D
raw
a s
imp
le B
iCM
OS
in
ver
ter
circ
uit
dia
gra
m a
nd
ex
pla
in i
ts o
per
atio
n
3.
(a)
W
hat
are
th
e d
iffe
ren
t sc
alab
le d
esig
n r
ule
s? E
xp
lain
an
y o
ne
of
them
.
(b
) D
esig
n a
nd
dra
w a
sti
ck d
iag
ram
fo
r tw
o i
np
ut
n-M
OS
NA
ND
an
d N
OR
gat
es.
4.
(a)
Wh
at i
s m
ean
t b
y s
wit
ch l
ogic
? D
iscu
ss a
bo
ut
alte
rnat
ive
gat
e ci
rcu
its.
(b
) E
xp
lain
ho
w t
o d
eter
min
e re
sist
ive
and
in
du
ctiv
e in
terc
on
nec
t d
elays
of
logic
cir
cuit
s.
5.
(a)
W
hat
are
th
e v
ario
us
sim
ula
tors
use
d f
or
com
bin
atio
nal
lo
gic
des
ign? E
xp
lain
th
eir
nee
d.
(b
) E
xp
lain
ho
w t
he
gat
e p
lace
men
t ef
fect
s lo
ad c
apac
itan
ce i
n f
an-o
ut
of
com
bin
atio
nal
lo
gic
.
6.
(a)
Ex
pla
in t
he
tech
no
log
y i
nd
epen
den
t an
d t
ech
no
log
y d
epen
dan
t st
rate
gie
s o
f p
ow
er
op
tim
izat
ion
use
d i
n s
equ
enti
al s
yst
ems.
(b)
Wri
te n
ote
s o
n c
lock
ing d
isci
pli
nes
.
7.
(a)
Ex
pla
in t
he
des
ign
val
idat
ion
s in
th
e fl
oo
r p
lan
nin
g m
eth
od
s.
(b)
Des
crib
e th
e P
lace
men
t an
d r
ou
tin
g t
ech
niq
ues
use
d i
n f
loo
r p
lan
nin
g.
8.
Wri
te s
ho
rt n
ote
s o
n t
he
foll
ow
ing:
(a
) L
ayo
ut
Syn
thes
is.
(b
) H
ard
war
e/S
oft
war
e C
o-D
esig
n.
**
**
**
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