Quiz1% - cseweb.ucsd.edu

Quiz 1

QUIZ – NO TALKING – NO NOTES

Q1: The AND gate is equivalent to which of the following Boolean operaGons?

A.  MulGplicaGon B.  AddiGon C.  IntersecGon D.  Union E.  Complement


Q2: Which of the following is the SOP canonical form of the funcGon f(X,Y) expressed by the given truth table?

A.  f(X,Y)= XY’ +X’Y B.  f(X,Y)= (X+Y’)(X+Y) C.  f(X,Y)= ΣM(2,3) D.  f(X,Y)= Σm(2,3)

X Y f(X,Y)

0 0 0 0 1 0 1 0 1 1 1 1


Q3: If f(X,Y)= XY’ +X’Y, what is f(0,Y)?

A.  X’ B.  0 C.  1 D.  Y


Q4: Given the same truth table as before, when does the minterm XY’ evaluate to 1?

A.  Whenever the funcGon f(X,Y) evaluates to 1. B.  Only when the input combinaGon is X=1 and Y= 0 C.  Either when the input is: X=1 and Y=0 OR when the input is: X=1 and Y=1 D. Only when the input is: X=1 and Y= 1

X Y f(X,Y)

0 0 0 0 1 0 1 0 1 1 1 1


Q5: Transform the circuit below using bubble pushing

A.  f(X,Y, Z)= X’+Y+Z B.  f(X,Y, Z)= X’(Y+Z) C.  f(X,Y, Z)= X(Y+Z) D.  f(X,Y, Z)= X

X Y Z

f

Which of the following is the switching funcGon for the transformed circuit?


Q6: Use consensus theorem to reduce the following Boolean expression:

A.  XY+Y’Z B.  XZ C.  X(Y+Z)

XY+Y’Z+XZ+XZ

Quiz 2


Q7: What does the red group in the following K-‐Map represent?

A.  The reduced term obtained by combining minterms XY’ and XY

B.  The minterms that should not be included in the switching funcGon

C.  The Boolean expression XY’XY

X = 0 X = 1

Y = 0 Y = 1

0 2

1 3

0 1 1 1


Q1: What does the ‘X’ symbol in the following truth table mean?

A.  The function F(A,B) can be reduced by combining min terms 1 and 2 B.  The implicant Σm(1) is prime C.  F(0, 1) can be designed to evaluate to a one or zero D.  We don’t care about reducing F(A, B) E.  F(0,1) is the result of multiplying the value of A and B

Id A B F(A,B)

0 0 0 0

1 0 1 X

2 1 0 1

3 1 1 0


Q2: Which of the following functions does the above K-map represent? A.  f(a,b,c)= Σm(0,3,4,5) B.  f(a,b,c)= Σm(3,5) C.  f(a,b,c) =ΠM(1,2,6,7) ΠD(0,4) D.  All of the above

0 2 6 4

1 3 7 5

X 0 0 X

0 1 0 1

ab c 00 01 11 10

0

1


Q3: Which of the following is true about the implicant Σm(0,8)? A.  It is a non-essential prime B.  It is an essential prime C.  It reduces to a product term in 3 literals D.  It reduces to a product term in 2 literals

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

1 1 0 1

0 0 X 0

1 0 0 0

X 0 1 X

ab cd

00

01

00 01 11 10

11

10


Q4: Which of the following is true about the implicate ΠM(5,13,7,15)? A.  It is an essential prime B.  It is a non-essential prime C.  It reduces to the sum term: (b+d) D.  It reduces to the product term: bd

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

1 1 0 1

X 0 X 0

1 0 0 0

X 0 1 X

ab cd

00

01

00 01 11 10

11

10


Q5: We used trees in the context of logic minimization with K-maps to identify which of the following?

A.  Essential primes B.  Non-essential primes C.  Multiple solutions to the K-map reduction D.  Multiple canonical expressions


Q6: When using trees to determine all reductions to POS for the above K-map, which of the following are valid children of the root (13,9,15,11)? A.  {(5,1) , (5,13), (5,7)}

B.  {(5,1), (7,6)} C.  {(0,4), (0, 8, 2, 10)} D.  {(1,5,13,9), (5,7,13,15)}

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

1 1 0 1

X 0 X 0

1 0 0 0

X 0 1 X

ab cd

00

01

00 01 11 10

11

10

Quiz 3


Q1: True or False: Can the operation of a NAND gate be implemented using ONLY the following function? Assume you can modify the function by fixing one or more inputs as (1 or 0).

A.  True B.  No

f(a,b,c)= ab+a’b’ +c


Q2: Which of the following functionalities is achieved by the given circuit for the input combination S’R’=(1,0)?

A.  Memory: Outputs (Q, Q’) remain unchanged B.  Set to zero: (Q, Q’)= (0,1) C.  Set to one: (Q, Q’)= (1,0) D.  None of the above


Q3: The following timing diagram corresponds to which of the following latch or flip-flops? (Assume the output is initially 1)

CLK

Input

Output

A.  D-latch B.  D-flip flop C.  T- flip flop D.  JK- flip flop


Q4: Which of the following is true about the given FSM?

A.  It is a Moore machine B.  It is a Mealy machine with two outputs C.  It is a Mealy machine that detects the input pattern 0001 in the

input sequence by setting the output to 1 D.  It is a Mealy machine that detects the input pattern 1101 in the

input sequence by setting the output to 1 E.  None of the above


Q5: For the given Mealy circuit, which of the following is true if x(t) transitions from 1 to 0 at t1 as shown in the following timing diagram ?

A.  Only the state: S(t) can change at t1 B.  Only the output: y(t) can change at t1 C.  y(t) will change at t1 only if S(t) also changes at t1 D.  S(t) and y(t) can only change at the next rising edge of the clock

after t1

C1 C2

CLK

x(t)

y(t)

Mealy Machine

S(t) t1

x(t)

Quiz 4


Q1: Consider the following FSM, that has one input x.

If 1 bit (Q) is used to represent the state, what is the assumed state encoding for the given state table: A.  S0: 0, S1: 1 B.  S0: 1, S1: 0 C.  Both of the above are correct D.  Neither is correct

S0 S1 x

x’

Q\x 0 1

0 1 1

1 0 1

State table


Q2: If a JK flip flop is used to implement the given state table, what is the most reduced expression for J(t) in terms of the Q(t) and x(t)?

A.  J(t)=1 B.  J(t)=Q(t) C.  J(t)=Q(t)’ D.  J(t)=Q(t)x(t) E.  Neither is correct

Q\x 0 1

0 1 1

1 0 1

State table


Q3: A unique FSM (diagram) can be obtained from a given sequential circuit for a fixed choice of: A.  Flip-flops (e.g. D, T, JK) B.  State encoding C.  Inputs D.  Outputs E.  None of the above


Q4: Which of the following is the correct state equation for the given sequential circuit?

A.  Q1(t)=Q0(t)’ , Q0(t)=Q0(t)+Q1(t) B.  Q1(t+1)=Q0(t)’ , Q0(t+1)=Q0(t)+Q1(t) C.  Q1(t+1)=Q1(t)’ , Q0(t+1)=Q0(t)+Q1(t) D.  None of the above

D Q

Q’

D Q

Q’

CLK

Q0(t)

Q1(t)


Q5: If tsetup is the setup time of a flip flop then a “setup time violation” is said to occur for the flip-flop if:

A.  The output of the flip flop does not remain stable for at least tsetup time after the rising edge of the clock

B.  The output of the flip flop does not remain stable for at least tsetup time before the rising edge of the clock

C.  The input to the flip flop does not remain stable for at least tsetup time after the rising edge of the clock

D.  The input to the flip flop does not remain stable for at least tsetup time before the rising edge of the clock

Quiz 5


Consider the given sequential circuit. Assume that the hold time constraint is satisfied for R2, if there is no clock skew.

A.  CLK1 is delayed compared to CLK2 by 0.1*Tc B.  CLK1 is advanced compared to CLK2 by 0.1*Tc C.  The clock period is doubled D.  None of the above

Q1: If skew is introduced, under which of the following conditions is the hold time constraint likely to be violated (for R2).


Q2: The given tree of 1:2 decoders implements which of the following functions?

A.  f (x, y, z)=Σm(1, 2, 6) B.  f (x, y, z)=Σm(1, 5, 6) C.  f (x, y, z)=Σm(2, 4, 3) D.  f (x, y, z)=Σm(1, 2)+ d(6)

I0

I0

01

01

I0

I0

01

01

f(x,y,z)

x

x

x

x

I0

I0

01

01

y

y

I0 01

z E

E

E

E

E

E

E

1


Q3: What is the output of the circuit for the input z = 1? A.  1 B.  0 C.  x D.  xy

En

En 1 0

1

z

y

f(x,y,z)

0

1

0

x

Output


Q4: Which of the following statements is true?

A.  HLSMs can have infinite states, while FSMs have finite states B.  HLSMs specify local storage of data elements and arithmetic

operations on data, while FSMs do not. C.  HLSMs specify the control signals that must be transmitted

between the controller and the datapath D.  HLSMs are special cases of FSMs


Q5: What is the output of the register ‘tot’ in clock cycle 4 for the following sequence of inputs to the datapath

A.  Output of register tot in clock cycle 4 is 0 B.  Output of register tot in clock cycle 4 is 25 C.  Output of register tot in clock cycle 4 is 50 D.  The output of the register cannot be determined

8

8

8

s

8

a

Datapath

tot_ld tot_clr

tot_lt_s

ld clr tot

8-bit <

8-bit adder

a

Clock Cycle 1: a=25, s = 50, tot_ld=0, tot_clr=1 Clock Cycle 2: a =25, s = 50, tot_ld=1, tot_clr=0 Clock Cycle 3: a =25, s = 50, tot_ld=0, tot_clr=0

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