Quick Start Nlint

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Quick Start

Quick Start: an nLint TutorialIn this tutorial, we will use a simple design as an example to guide you through themajor features in nLint. Steps we will go through are as follows:

z Specify the rules to be checked.z Specify the UDR scripts.z Specify the design file (using a run.ffile).z Invoke the nLint checking process.z View and edit errors.

View source code in the built-in editor- J ump to the source code that causes the errors.- Edit the source code to correct the error.- Save the file and re-run nLint to verify that the error has been corrected.View source code in Debussy- Set source code display to nTrace/nSchema automatically.- Double-click a violation and nTrace will display the relevant source code.

- Double-click a violation and nSchema will display the relevant path.1. Invoke nLint Graphical User Interface (GUI)

Before we start, we need to get a fresh copy of the sample source code, and makesure that you have write privilege on those files. Please go to the directories:

/ demo/ ver i l og

And issue the following commands:

> cp - r f or i gi nal / * . > chmod 777 * > cd r t l

Now, let's start nLint GUI by typing the following command at the shell prompt:

> nLi nt - gui

The main frame will be shown on the screen:

Figure: nLint Main Frame

There are three sub-windows in the main frame of nLint: Project Window, EditorWindow and Output Window.


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command. After the command is issued, a dialog box pops up showing two tabs,From Library and From File. For this tutorial, we will use the From File method.Click on the From File tab, an Import Design form appears as shown below. Youcan use this to browse the directories and files on the disk. Please change thedirectory to /demo/verilog/rtl and select the run.ffile, as shown below:

Figure: File->Import Design->From File

Click the OK button to import the design. Then, the file names of the design file wbe listed in the project window as shown. Notice that the first file is automaticallyshown in the integrated editor window.


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Figure: Show File Content in Editor Window

3. Edit more than one file at the same time

When you double-click on a file, the file contents will be shown in the editorwindow. Clicking the right mouse button on a file displays a shortcut menu with anOpen command and Suppress File Comman. Select the Open command, theselected file will be shown in another editor window, as illustrated below.

Figure: Show File in Another Window

4. Configure to suppress or unsuppress some files

Select a file and click on the Suppress button. An unchecked icon will be attache

on the file if the status of the command is unchecked.


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Go to the Hierarchy tab, the design hierarchy tree is shown. Select a node andclick-right to choose the Lint from here command, which specifies the checkingprocess to lint the sub-design from system.i_cpu.

Figure: Lint from system.i_cpu

6. Invoke Rule Organizer

Then, we need to start the rule organizer by issuing the Tools->Rule Organizer

command. There are two major windows in Rule Organizer: the one to the leftdisplays a list of groups, and the one to the right displays a list of rules under theselected group.

Figure: Rule Organizer

There are three top groups Compilation & Elaboration nLint and RMM


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The nLint group includes the following ten sub-groups, namely, Simulation,Synthesis, ERC, DFT , Design Style , Language Construct , HDL Translation ,Naming Convention , Coding Style , VITAL Compliant , Clock and BlockInterconnect. By default, the Naming Convention, Coding Style and VITALCompliant sub-groups are disabled, i.e., rules in those three sub-groups are notchecked by default. This is indicated by a red X marked on the icon of these threesub-groups. (If for some reasons the default setting has been changed in yourenvironment, you can use the Groups->Enable command to disable these three

sub-groups.)The RMM group includes the groups and rules that are named by the ReuseMethodology Manual For System-On-Chip Designs, a book on IP re-use.

In the above figure, the active top group is nLint, which is marked with blue color.The Compilation & Elaboration group will always be included in checkingregardless of which is the top group.

You can get help on a rule by selecting that rule in Rule Organizer and pressing

the F1 key (Note that the rules in Compilation & Elaboration group are notsupported currently). After that, if you select a different rule in Rule Organizer, youwill need to press F1 again in order to make the online help to jump to that rule.

7. UDR Scripts

By default, under the demo directory of, there is an udrdirectory, inwhich there are two files, udr.ini and action.tcl, for UDR scripts. If you usenLint -gui-udr /demo/udrto invoke nLint, the UDR scripts from this

directory will be loaded. The user-definable rules (UDR) specified in the udr.ini fileare categorized in a User Defined group and these rules will be added into theactive top group and be shown in the Rule Organizer, as illustrated below.


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Figure: UDR in Rule Organizer

There is one rule in the udr.ini file. Rule 30002 is to check if the instance nameshould have a prefix (u_) plus the name of the defined module.

8. Start Checking

In the main frame, select Run->Lint to start the checking process. While runningthe process, a progress window appears, as shown below.

Figure: Show Checking Progress

The progress bar shows approximately how much work has been done, and howmuch more to go. You can click the Stop button to stop the checking process atany time.


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Figure: Report Viewer is Displayed After Checking Process

The reported violations are sorted first by groups and then by rules; they are showin a tree structure at the upper part of the review viewer. You can click on the plus(+) icon to expand the rule, thus showing more details, or click on the minus (-) icoto collapse, thus hiding the details.

When left-clicking on a rule message, the detailed information will be shown in thedetail window, the lower part of the report viewer, with three sections: the firstsection is the violation itself; the second is the source code in quick view, enclose

with a rectangular box; and the third section (See Also) lists the related violations.

For this tutorial, please expand the Simulation rule group, and double-click on thefirst rule under that group. Reported messages under that rule is shown asfollowing.


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Figure: Report Viewer - Simulation Rule Group is Expanded

When clicking on the violation 22283, the detailed information is shown in the detawindow, in which you can find the module definition with port declaration, noticethat there is a port addr_error. You can also find the module instance i_maprom,notice that there is no port instance to the port addr_error.

In the tree window of report viewer, double-click on the violation, CCU.v(78), theeditor window in the main frame will open the source file and jump to the related

source code line and highlight it as follows:

Figure: Show Related Source Code in Editor Window

You can see that the error is about the open connection on the addr_errorinstancport. Let's just assume that we can ignore that for now.

Next, let's expand the Language Construct rule group. You will see that the firstviolation is about clock driven by expression.


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Figure: Report Viewer - Language Construct Rule Group Is Expanded

Double click on the violation message, CCU.v(99), and you will see the followingfigure in the editor window:

Figure: Show Related Source Code in Editor Window

This is about the assignment (next_MA = MA + 1'b1). The carry bit of an addition possible to get lost in assignment. Let''s use the editor to modify the code byadding a carry signal, such as a value: MA_carry, in the left hand side of theassignment. See following figure for explanation.

Figure: Modify Source Code with nLint Editor

In addition, you may also need to modify the declaration ofMA_car r y, as shown

below:


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Figure: Modify Declaration of MA_carry

10. Save Edited Source File and Re-run the Checking Process

Now, we can save the edited source code, and re-run the checking (by re-issuingthe Run->Lint command) to verify that the error has indeed been fixed.

11. Set Source Display to nTrace/nSchema

If you are a Debussy user, you can link nLint to nTrace/nSchema. This integrationbetween nLint and nTrace/nSchema is very useful since many types of errors

reported by nLint involve multiple parts of the source code. To analyze these typeof errors, you need Debussy's powerful tracing and viewing capabilities.

To set up, you need to use the Tools->Preferences command in nLint. APreferences dialog box pops up, as shown below:

Figure: Preferences Dialog Box

In the Report->General tab, there are four options under Double click error wil lshow source on: Default Editor, nTrace, nTrace/nSchema automatically andDefault Editor/nSchema automatically. The Default Editor option is enabled by


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suitable to show source code in nTrace, while the information of some violations,i.e. 22011, combinational loop, is suitable to show source code in nSchema.

When the preferences are set, click OK to close the dialog box. nLint will save thenew settings in the nLint.rc file in your working directory. The next time you launchnLint, it will use the last settings saved in this nLint.rc file.

Next, let's go back to the report viewer in nLint and expand the DFT rule group.There is violation of rule 22053, which is a gated clock. Double-click on the

violation reported at ALUB.v(97), you will see that nSchema window is invoked,and the path from the gate output to the clock port of the register is shown in thenSchema window. Following is the figure.

Figure: Gated Clock Error is Shown in nSchema Window

At this point, we can invoke the nTrace window to display the source code of thegate inferred and the register inferred, and drag the orgate over (from nSchemawindow). In the nTrace window, we can see clearly about the inferred orgate.


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Then you can drag the register over. The source code inferred by the register willbe shown in nTrace window as below:

Figure: Inferred Flip-Flop Register is Shown in nTrace Window

If you want to change back to the nLint editor window for source code display, youneed to follow the same steps starting from Tools->Preferences->Report->General, and click on the Default Editorbutton.

12. The UDR Violations

After linting the above design, we can also see that there are violations in the UseDefined rule group. Click on the first violation under rule 30002, you will see thereport viewer as follows.


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NOVAS Softwarewww.no

Phone: 1-888-6Fax: 408-4

NOVAS


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lock AnalysisT utorial

Clock Analysis Tutorial

Overview

In this tutorial, we will guide you through major features of clock

analysis with a simple design as an example. The step goes asfollowing:

Extract clock source tree

Specify design under analysis

Load Clock DB into Debussy

Extract mix-clock domain paths

Specify virtual clock source and primary ports Structural proving the mix-clock domain paths with template

Export information into ASCII file

Command line options

Prepare the demo cases

Create a working directory and copy the demo files gate.f, top.v

and process_gate.v to the working directory. The three demo

files are located in /demo/tutorial/. Please go to the

working directory to apply the following steps. Before you begin,

please set environment variable as:

setenv TURBO_LIBS lsi10k_u

le:///C |/N ovas/nLint2.2v24/doc/html/user/clock_analysis_tutorial.html 1 21 2007-9-20 9:33:02
http://c%7C/Novas/nLint2.2v24/doc/html/user/22userIX.htmlhttp://c%7C/Novas/nLint2.2v24/doc/html/user/gui.htmlhttp://c%7C/Novas/nLint2.2v24/doc/html/user/quickstart.htmlhttp://c%7C/Novas/nLint2.2v24/doc/html/user/22userTOC.html


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And invoke nLint with GUI mode by:

nLint -gui -f gate.f

Extract Clock Source Tree

After import the design file "gate.f" into nLint by File->Import,invoke command Run->Create Domain.

Figure: Result of Extracted Clock Source Tree

In above result, there are two clock source trees. One is driven

by top.clock, which is un-resolved. The other is top.

clk_rec, which is also un-resolved.

Invoke Debussy by command nLint Main Frame->Tools-



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>Debussy. Please set the correct path of Debussy in Tools-

>Preference->Debussy/Verdi.

Debussy will load the same design. Invoke nSchema on the top

module, you can see there is no port and there are initial

statements in it. The clock sources come from the initial

statements. So they are all un-resolved.

Specify Design Under Analysis

Most design files include test-bench. It is not convenient to load

a separate design files exceptional for nLint. Under such

situation, you can set the Design Under Analysis in nLint.

Click the Hierarchy Tab in nLint main frame. Use right-mouse-

button command on top.u_proc to set Lint From Here as

following figure shows.

Figure: Invoke Lint from Here

It will invoke a window as following for you to confirm to the



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setting ofLint From Here, orDesign Under Analysis.

Figure: Design Under Analysis

Click OK to confirm to set the top.u_proc as the design for

analysis.

By this setting, the boundary of the design will be changed to

top.u_proc. It means:

Design out of scope top.u_proc will not be analyzed.

The ports oftop.u_proc are primary ports of the design.

But any full scope string will still start from top.

Repeat the command Run->Create Domain in nLint main

frame menu. The result ofClock Source Tree extraction isbecoming as following figure.



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Figure: Clock Source Tree Extraction after Design Under

Analysis is set

The two clock sources become resolved to primary input.

Load Clock DB into Debussy

Invoke Report Viewermenu command File->Save, to save the

clock db. You can load the clock db in Debussy by invoking

nSchema->File->Load Clock Domain Results. Choose theclock db saved from nLint to load. Then the clock source tree

will be listed in Debussy as following.



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Figure: Clock Source Tree in Debussy

Then you can put the clock source tree, internal clock source or

the clock domain interested into nSchema. Following is

nSchema view of clock source top.u_proc.clock.



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Figure: nSchema view of clock source tree top.u_proc.

clock

Extract mix-clock domain paths

Then we can continue to analyze the crossing paths between

clock domains. Invoke Report Viewermenu command Domain-

>Mix Clock Domain Extraction. A wiindow as following will be

popped up.



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Figure: Set Mix Domain

Add the two clock source trees to both of the Clock Source

(From) and Clock Source (To) boxes. It directs nLint to check

the crossing path from clock source tree top.u_proc.clock

to clock source tree top.u_proc.clk_rec and vice verse.

Click OK to extract the crossing path. The result is shown in

following.



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Figure: The result of Crossing Path

In the result, the crossing paths are grouped by domain pairs.From beginning to the end, there is one crossing path from

domain positive triggered by top.u_proc.clk_rec to the

domain positive triggered by top.u_proc.clock; there is

one crossing path from domain positive triggered by top.

u_proc.u_ctrl.clk_send to domain positive triggered by

top.u_proc.clk_rec; there are 8 crossing paths from

domain positive triggered by top.u_proc.clock to domain

positive triggered by top.u_proc.clk_rec.

If you expand the folder of the domain pair, you can find the

registers information of the crossing path. Also in detail window,

the path information is listed from the start register to the end



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register.

If double clicking the register pair, nLint will show the path of

register pair in nSchema. Following is the result if you double

click the highlighted register pair in above figure.

Figure: Crossing Path shown in nSchema

Specify virtual clock source and primary ports

In above crossing path extraction, we do not consider the

primary ports. For example, the primary input port top.

u_proc.cmd_data comes from outside block and sampled by

another clock clock_ram. We can consider such primary ports

as sequential elements in extracting crossing path.



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In nLint main frame, invoke Run->Project Setting->Clock

Analyiss->Virtual Clock Source, you can specify a virtual

clock named clock_ram as following.

Figure: Specify virtual clock source clock_ram

Click Apply to enable the setting.

After that, you can specify the primary ports as virtual clock

source. Choose the clock_ram in Clock Source field. Select

pos-edge box as the trigger edge. Highlight the primary port

top.u_proc.cmd_data and apply the clock source on it.



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Figure: Specify primary port for virtual clock source

Click Apply to let the setting take effect.

After that, repeat the clock source tree extraction by Run-

>Create Domain. The clock source tree with virtual clock

source clock_ram as root will be listed as following.



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Figure: Virtual Clock Source Tree

The primary port cmd_data is listed under the virtual clock

source tree like registers.

Repeat the crossing path extraction command Domain->Mix

Clock Domain Extract. And add the virtual clock source tree

into both the From Domain and To Domain lists.



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Figure: Add Virtual Clock Source Tree in Mix-Clock Domain

Extraction

After click OK, additional crossing path from the primary input

port cmd_data will be extracted as following.



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Figure: Crossing Path from Primary Input Port

There are 18 crossing paths from primary input port cmd_data

to registers of domain positive triggered by top.u_proc.

clock.

Structural proving the mix-clock domain paths with template

Generally, there is design rule to force crossing path pass

through a number of synchronizer flip-flops. In nLint structure

synchronizer template is provided to prove the design rule.



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Invoke the command Domain->Synchronizer Proving in

Report Viewer, the following box will be popped up.

Figure: Synchronizer Proving Box

Choose proving crossing path from "All" clock domains to "All"

clock domains. It means all crossing paths found will be applied

on such proving. Choose template nl_sync2. It is a default

template. Click Help button will show the detail informationabout the template as following.



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Figure: Help Information for template nl_sync2

Click Verify to start the proving process. The result is shown as

following.



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Figure: Synchronizer proving result

For satisfied path, for example, the path from top.u_proc.

u_ctrl.send_reg to top.u_proc.u_rec.send_1_reg,

which is expanded in above figure, will be expanded with the

synchronizer flip-flops. Double click the expanded path, it will be

shown into nSchema as following.



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Figure: Satisfied Crossing Path

From nSchema, it is clear that the signal send passing through

2 synchronizer flip-flops before goes into destination clockdomain.

Another expanded path is an unsatisfied path, from top.

u_proc.u_ctrl.\data_reg[0] to top.u_proc.u_rec.

\rec_data_reg[0] . The failsure reasons are printed out as

a message under the path. It says "the cross path does not

have enough number of FFs, the least is 2". It means the signal

does not pass through 2 synchronizer flip-flops before goes into

destination clock domain.

Export information into ASCII file



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All above result shown in Report Viewercould be exported into

an ASCII file. Invoke Report Viewer menu command File-

>Export Clock Domain, a form as following will be prompted.

Figure: Export Clock Domains

Choose to export all registers information under clock source

tree by check the checked box Include registers. Click OK to

export the information. The result is in clock.rep.

Command line options

All above actions can be run quickly by applying the followingcommand line options.

-lintTop top.u_proc

-vclk_source clock_ram



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-io_clk top.u_proc.cmd_data clock_ram_posedge

-ex_clk

-clk_from_domains All

-clk_to_domains All

-sync_p All:All:nl_sync2

-clk_export clock.rep

-clk_export_reg

You can write it into a file clock.opt and use following command

to invoke nLint.

nLint -gui -f gate.f -opt clock.opt

Then you can get the final result directly.

N O V A S Software, www.novas

Phone: 1-888-668-

Fax: 408-467-

N O V A S Sup
http://c%7C/Novas/nLint2.2v24/doc/html/user/22userIX.htmlhttp://c%7C/Novas/nLint2.2v24/doc/html/user/gui.htmlhttp://c%7C/Novas/nLint2.2v24/doc/html/user/quickstart.htmlhttp://c%7C/Novas/nLint2.2v24/doc/html/user/22userTOC.html

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