Queuing System (Plate No. 1)

Submitted to ENGR. RODRIGO S. PANGANTIHON, JR., MIT

Professor in CPE 443/L

Submitted by Marc A. Bacus BSCoE

Student

June 23, 2014

Plate Analysis

This plate is an up counter that counts up from 0-99 with reset and a window number

display. This plate uses JK flip-flops with binary outputs. The outputs are tied to a decoder IC

(7448) then the outputs of the decoder are tied to the inputs of the seven segment displays.

Clock Input Analysis

The JK flip-flops has a pin for the clock. Buttons are used to feed signals to the clock of

the flip-flop. Since we’re using buttons, a button debouncer is required. The debouncer

eliminates the initial contact when using the button. Without the debouncer, the counting

can jump many times and that is not the required output. I’ve used an RC debouncer in this

plate since the internet says it’s the most reliable debouncer when using buttons. I’ve added

a NOT gate on the output of the debouncer because the output of the debouncer is zero. The

tweak will be explained more using images. Because we’re required to have 3 buttons, 3

debouncers are needed. The output of the debouncers are then tied to the inputs of a 3-input

AND gate. The output of the gate is tied to the clock pin of the flip-flop. The initial high feed

will not trigger the clock. When a button is pushed, the output of the AND gate will be low

and then the clock will be triggered.

0-9 Counter Analysis

The counter requires 4 JK flip-flops. The J and K are tied together and are both high,

the Q is then fed to the next clock and so on. The flip-flops create 4-bit outputs Q0-Q3. Since

the outputs would have outputs 0000-1111, I’ve created a condition that resets the counting

when the output reaches 1010. Using a NAND gate, Q1 and Q3 are tied to the NAND inputs,

then the NAND output is tied to all the reset legs of the flip-flops. When the NAND inputs are

high or 1, the zero output triggers the reset function of the flip-flop.

0-99 Counter Analysis

Since I’ve finished the 0-9 counter, I’ve duplicated it with the same logic and tied Q3

to the clock of the duplicate 0-9 counter. The first initial input to the clock of the second flip-

flop is low or zero. When the first counter reaches 1010, Q3 is high or 1, thus triggering the

clock of the second counter.

Window Number Analysis

When one of the 3 buttons is pressed, there must be a corresponding number display.

I’ve used an SR latch IC (74279) to do the job. Button 1 output is tied to pins 2 and 10, button

2 output is tied to pins 3 and 12, and button 3 output is tied to pins 1 and 11. Output pin 4 of

the latch IC is tied to pin 7 of the cathode decoder (7448) and output pin 9 is tied to pin 1 of

the decoder. Since this is a latch or a flip-flop, the inputs are registered and so is the display.

Reset Analysis

The reset is just a button that is connected directly to the reset pins of the flip-flop.

When pressed, the reset is triggered and the counting is back to zero.

Findings and Recommendations

Through this plate, I’ve found some few things that must be remembered. First is, flip-

flops are very useful when storing data that was fed by the inputs, without flip-flops, the data

that was fed to the input would be gone when the button in released. Second, Gate

manipulation is very important in creating conditions. Without the knowledge of the gate

inputs and outputs, you cannot create a condition. Example is the condition above that resets

the flip-flops when the binary counter reaches 1010.

Sche

matic D

iagram