QB63xx Datasheet Datasheet... · 2020. 10. 1. · QB63xx Datasheet Revision 1.04 Introduction 4...

QB63xx Datasheet Revision 1.04 Document History

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QB63xx Datasheet Revision 1.04

QBit Proprietary and Confidential

Copyright © QBit Semiconductor LTD. All rights reserved.

QBit is a trademark of QBit Semiconductor LTD. Other product and brand names may be trademarks or registered

trademarks of their respective owners.

While care has been taken to ensure the accuracy of this document, QBit cannot accept responsibility for any errors.

QBit reserves the right to make modifications to its products and documentation.

QB63xx Datasheet Revision 1.04 Document History

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Document History

Revision Date Change Summary

1.0 2018-11-02 Initial Release

1.01 2020-02-28 Updated

1.02 2020-06-29 Screener Section Update

1.03 2020-08-04 I2C and Serial Port Overview Section Update

1.04 2020-09-30

Updated DDR and Max Power in the Feature Summary Table, Added New Table

“Summary of QB63xx Feature Differences by Package”, Updated DDR Interface

section Table 2-1, Removed DDR4 14L and 14P Ball Map Diagrams, Updated

DDR3 14L and 14P Ball Map Diagrams, Key Features in USDR section, Both Tables

in Signal Description section, and Scanner Interface section

QB63xx Datasheet Revision 1.04 Contents

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Contents

Document History ................................................................................................................................................ 2

Contents .............................................................................................................................................................. 3

1 Introduction ................................................................................................................................................. 4

Block Diagram .................................................................................................................................................... 4 Feature Summary ............................................................................................................................................... 5 QB63xx Series ..................................................................................................................................................... 7 Evaluation Board ................................................................................................................................................ 7 Architecture ....................................................................................................................................................... 8 Power Islands ..................................................................................................................................................... 9 Power Control .................................................................................................................................................. 10 Image Processing Overview ............................................................................................................................. 11

2 SOC Cores ................................................................................................................................................... 13

CPU Cores ......................................................................................................................................................... 13 Memory Cores.................................................................................................................................................. 14 System Control Cores ....................................................................................................................................... 17 Scanner and Printer Control Cores................................................................................................................... 19 Image Processing Cores ................................................................................................................................... 22 Connectivity Cores ........................................................................................................................................... 29 System Interface Cores .................................................................................................................................... 30

3 Signal Description ....................................................................................................................................... 37

4 Electrical Specifications ............................................................................................................................... 39

Absolute Maximum Ratings ............................................................................................................................. 39 Recommended Operating Conditions .............................................................................................................. 40 Operational Conditions – LVCMOS IO .............................................................................................................. 41 Operation Conditions – LVDS TX IO ................................................................................................................. 41 Operation Conditions – Oscillator IO ............................................................................................................... 42 IO Operation Conditions – Oscillator IO (RTC) ................................................................................................. 42 AC Parameters and Controls – LVCMOS IO ...................................................................................................... 43 DC Characteristics – LVDS TX IO ....................................................................................................................... 43

5 Package Information ................................................................................................................................... 44

Overview .......................................................................................................................................................... 44 Mechanical Package Information ..................................................................................................................... 44 Package Ballout Information ............................................................................................................................ 47

QB63xx Datasheet Revision 1.04 Introduction

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This datasheet provides basic technical information on the QB63xx SOC Series. For complete technical information,

please see the QB63xx User Guide.

1 Introduction

The QB63xx is a highly integrated system-on-chip (SOC) designed specifically for print and scan devices including:

Laser/LED single-function and multi-function printers

Inkjet single-function and multi-function printers

Dye-sub printers

Thermal printers

Label printers

POS receipt printers

3D printers

Document scanners

Check scanners

Block Diagram

Figure 1-1: QB63xx Block Diagram


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Feature Summary

Category Feature Specification Units

CPU

Processor Cortex-A7 up to 1.125 GHz 1-2

L1 I/D Caches 32KB/32KB 1-2

L2 Cache 512KB 1

Cache Coherency CCI-400 1

Floating Point VFPv4 1-2

SIMD Extensions NEON 1-2

Image Processing

Scan Front End

Shading Correction 1D Lookup Vertical Fringe Correction White Point Tracking

2

Scan Back End

White Point Calibration Gamma Correction RGB-to-YCC Color Conversion Segmentation

2

Other Image Processing Units

FIR Filter Tetrahedral Color Converter Scaler Screener

2 1 1 2

Currency Detector 1

Imaging DSP Up to 480 MHz 4

JBIG 2

JPEG 2

Memory

DDR 8-bit DDR3L-2133 1GBx2 or DDR4-2133 2GBx2 1

On-Chip SRAM

1MB main scratchpad

256KB scan scratchpad

128KB print scratchpad

1

1

1

Serial Flash (Boot Option) 1/2/4-bit SPI NOR/NAND 1

eMMC Flash (Boot Option) 1/4/8-bit, up to HS200 (ports shared with SDIO) 2

Display LCD Interface 18/24-bit LCD LVDS 3/4 ch, Vx1 1 ch, 8-bit SRGB

1

Printer Output & Control

Processor Cortex-M3 up to 400 MHz 1

Processor L1 I/D Caches 16KB/16KB caches with locking 1

Output Channels LVDS 1 ch, LVCMOS 1/2/4/8 pins (32 pins total) 8

Subpixel PLL Up to 2.56 GHz 1

VSYNC Synchronization 1

HSYNC Synchronization 8

Laser Modulation 8 to 32 bits 8

Laser Angle Compensation 0-7 stretch subpixels per pixel at 1200 dpi 8

Laser Dot Counter 8

Inkjet Formatter 1

Thermal Profile Generator 1

Scanner Input & Control

Processor Cortex-M3 up to 400 MHz 1

Processor L1 I/D Caches 16KB/16KB caches with locking 1

External AFE Interface LVDS 3/4/5 ch, LVCMOS 4/5/6/7/8/10 pins 2

DataPort Interface LVCMOS 4/5/6/7/8/10 pins 2

Data Rearrangement Multi-segment deinterleaving, up to 9 segments 2


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Timing Generators

Signal Inputs & Generators

Multi-purpose TGEN units PWM outputs: timer, clock, PWM, modulated PWM

I/Os with buffer: ring buffer, FIFO

Event inputs: single input, dual input, speed

monitor, phase comparator

96

USB USB Dual Role USB 3.2 Gen 1x1 SS (5 Gbps) Dual Role 1

USB Host USB 2.0 HS Host 2

Ethernet Ethernet MAC 10/100/1000 1

PCIe PCIe Gen 2, dual mode, 1 lane 1

Serial Interfaces

SPI 2

Serial Port (UART) 8

I2C 6

SDIO/eMMC SDSC/SDHC/SDXC, 1/4/8-bit, DS/HS/UHS-I 3

ADC/DAC ADC 15 ch, 12 bits, A0: 6.65 MSPS, B0: 13.3 MSPS, 3.6V 1

DAC 4 ch, 8 bits, 0.5 MSPS, 3.3V 1

Real Time Clock RTC 32.768 kHz, <=2uA standby current 1

GPIO GPIO Pins selectable as GPIO (including TGEN IO) 168

Boot OTP 2 kbits 1

Boot ROM Secure boot: RSA, AES 1

Debug Debug Trace CoreSight with ETM 1

Power Max Power See QB63xx Power Modes Table document

Sleep Power 65 mW with Ethernet connection

Package Package Options FBGA 289 14x14 0.8 FBGA 432 19x19 0.8

Table 1-1: QB63xx Feature Summary

Note: Only a subset of units may be available in a particular configuration based on package pinout, pin overlay

settings, and power island settings.

Feature 19U Package 14L Package 14P Package

DDR

DDR3L-1866

DDR3L-2133

DDR4-1866

DDR4-2133

DDR3L-1866 DDR3L-1866

USB Dual Role Port USB 3.2 Gen 1x1 SS (5 Gbps) USB 2.0 HS USB 2.0 HS

Scanner Interfaces 2 1 1

Print LVDS 8 ch 8 ch 4 ch

PCIe Yes - -

SDIO/eMMC Ports 3 2 2

ADC 15 ch 9 ch 15 ch

DAC 4 ch 4 ch -

GPIO & TGEN IO Signals 168 108 118

Table 1-2: Summary of QB63xx Feature Differences by Package


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QB63xx Series

The QB63xx is available in several speed grades and packages/pinouts to cover a wide range of cost, functionality and

performance.

QBit Part Number A7 Configuration A7 Max Speed Package Pinout

QB6310-14L/500 Single Core 500 MHz 14 = FBGA 14x14 L = Laser/LED

QB6310-14L/667 Single Core 667 MHz 14 = FBGA 14x14 L = Laser/LED

QB6310-14P/500 Single Core 500 MHz 14 = FBGA 14x14 P = Photo

QB6310-14P/667 Single Core 667 MHz 14 = FBGA 14x14 P = Photo

QB6310-19U/833 Single Core 833 MHz 19 = FBGA 19x19 U = Universal

QB6320-19U/833 Dual Core 833 MHz 19 = FBGA 19x19 U = Universal

QB6320-19U/1000 Dual Core 1.0 GHz 19 = FBGA 19x19 U = Universal

QB6320-19U/1125 Dual Core 1.125 GHz 19 = FBGA 19x19 U = Universal

Table 1-3: QB63xx Series

Note: Some A7 speeds and DDR speeds require overdrive (OD) core voltage.

Evaluation Board

The QB63xx Evaluation Module (EVM) is a board available from QBit for doing development on QB63xx.

Figure 1-2: QB63xx EVM


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Architecture

The QB63xx architecture is comprised of blocks, cores, buses, and bridges. The diagram below shows the high-level

architecture for the QB63xx B0.

DDR

BLOCK: DDR CLOCK: DDR_CLK

CORES: GPF, DDROVL, DDRPIO, QBIO, SDIO, FCSPI, TIMER, RSTGEN,

CLKGEN, RTC, QBMC, I2C, DDRPHY

Customer IP

BLOCK:

CIP

CLOCK:

CIP_CLK

CORES:

GPF

C1

C2

PCIe IF

BLOCK:

PCI

CLOCK:

PCIE_CLK

CORES:

GPF

PCIe

System

BLOCK:

SYS

CLOCK:

SYS_CLK

CORES:

CIP_UI

EFUSE

GMAC

GPF

I2C

LLDMA

OTP

QBDMA

(2) SDIO

SCAOVL

SCAPIO

SPI

SYSOVL

SYSPIO

(2) UART

(2) USBH

USBD

TGEN3

Dual ARM

A7

BLOCK:

A7

CLOCK: A7

A7_CLK

CORES:

GPF

GIC

(2) Cortex A7

L2 Cache

Image

Processing 1

BLOCK:

IPM1

CLOCK:

IPM1_CLK

CORES:

GPF

(2) JBIG

(2) JPEG

LLDMA

QBDMA

TCC

Image

Processing 2

BLOCK:

IPM2

CLOCK:

IPM2_CLK

CORES:

CD

(2) FIR

GPF

(2) SBE

SCAL

(2) SCREEN

(2) SEG

DSP

BLOCK:

DSP

CLOCK:

DSP_CLK

CORES:

GPF

(4) DSP

Scanner IF

BLOCK:

SCA

CLOCK:

SCA_CLK

CORES:

GPF

(2) LVDS

M3_0

(2) SCAN

(2) SCALVDS

SPI

TGEN

(2) UART

Printer IF

BLOCK:

PRT

CLOCK:

PRT_CLK

CORES:

ADC

DAC

CoreSight

GPF

GVIF

(4) I2C

LCD

LLDMA

M3_1

PRI

PRTOVL

PRTPIO

(2) TGEN

(3) UART

VIDPLL

(2) Vx1

Cache Coherency Interconnect

CCI400

Figure 1-3: B0 High-level SoC Architecture

There are ten blocks in the QB63xx:

SYS – System functions including many of the peripheral interfaces (USB, I2C, etc.)

A7 – Dual Cortex A7 processors including L1 and L2 cache

PCIe – Single lane PCIe controller plus PHY


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IPM1, IPM2 – Hardware image processing cores

SCA – Scanner interface and front end image processing logic

PRI – Printer interface logic

DSP – Quad DSP processors

CIP – Customer IP

DDR – Contains QBMC DDR controller, DDR PHY plus other system-level cores

Buses and bridges make up the fabric of the SOC. The QB63xx uses various flavors of AXI buses throughout the

design. Bridges are used in all of the blocks to link buses of different speeds, widths, and protocol. Bridges can also

include various amounts of buffering.

All blocks connect to the DDR block either directly or via the cache coherency interconnect. In general, there is a

main clock associate with each specific block (i.e., sys_clk, ipm1_clk, etc.) however, there are many different clocks

used in the design.

Power Islands

Power islands are used throughout the QB63xx architecture. Each power island has separate controls that can be manipulated by SW. A power island is comprised of isolation cells and power switches. The isolation cells are used to cut off the signal outputs of the powered down island so they do not adversely affect the powered logic they connect to. The power switch turns the power on/off to a specific island.

There are 17 separate power islands in the QB63xx B0.

QB63xx BO

Power Islands Blocks/Cores in Power Islands

Always_On SYS, BootROM, USBMEM, DDR, AO_CIP, A7_GPF, PRT M3, PSP, QBCS, PROVL

A7 A7 cache A7_CPU0 CPU0 A7_CPU1 CPU1 IPM1 LLDMA1, QBDMA1 SW1_IPM1 JBIG0, JBIG1, TCC0 SW2_IPM1 QBJPG0, QBJPG1 IPM2 MSP0, FIR0, SCL0, SCRN0, CD SW1_IPM2 SBE0, SEG0 SW2_IPM2 SBE1, SEG1, FIR1, SCRN1 DSP DSP0, DSP1 SW1_DSP DSP2, DSP3 SCA SCA SW_PRT PRT minus PRT M3, PSP, QBCS,

PROVL PCI PCI SW_DDR SW_DDR CIP CIP

Table 1-4: Power Islands


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Figure 1-4: B0 Power Islands

Power Control

The QB63xx supports power control for lowering power during operation.

Typical uses:

Reducing power consumption during idle periods for Energy Star compliance

Complete shutdown of blocks that are not used in a particular application Key features:

Ability to monitor for wake-up events: USB, Ethernet, WiFi connected via SDIO, and UI button press

Very granular control to power up/down blocks


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Low power operation:

Most blocks are powered off; selected blocks such as the USB Dual Role interface, Ethernet MAC, SDIO interface, and Printer Interface M3 are kept powered on

Printer Interface M3 is running at a reduced clock rate

Ethernet MAC is configured to filter packets

OS running on A7 is suspended to DDR

A7 is powered off

DDR goes into self-refresh power down after a certain period of inactivity

USB Dual Role interface is put into suspend state after a certain period of inactivity or by a host request

M3 in Printer Interface receives interrupts, monitors activity and determines when to wake up A7 and resume OS

M3 may handle certain events, such as simple Ethernet queries and USB mass storage queries, without waking A7

Image Processing Overview

The QB63xx provides customizable, high-throughput image processing for print and scan devices.

Image Processing Hardware

The QB63xx provides customizable, high-throughput image processing for print and scan devices.

The QB63xx contains a complete hardware image processing pipeline for copy, scan, and print functions. The QB63xx

also contains 4 DSPs for implementing custom image processing.

Pipeline Design

There are unique image processing requirements to achieve good image quality when inputting scan image data from

a contone RGB linear CIS or CCD scanner and outputting print image data to a bitonal CMYK laser, LED or inkjet

printer or contone CMY thermal printer. The following diagram describes the QB63xx image processing pipeline and

its features for achieving good image quality.


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Step Summary

Scan Front End

1D Lookup Compensates for non-linear scan sensor response.

Shading Correction Compensates for uneven illumination across the width of scan sensor.

Vertical Fringe Correction Compensates for color fringes that result from vertical misalignment of R, G and B during scanning.

White Point Tracking Determines the white point of the scanned image, i.e. the level closest to white.

Data Packer Packs the data before writing to DDR.

Scan Back End

White Point Calibration Adjusts colors so that non-white background is printed as white.

Gamma Correction Compensates for non-linear scan sensor response.

RGB-to-YCC Color

Conversion

Converts from RGB to YCrCb color space in preparation for segmentation and FIR filtering.

Segmentation Categorizes each pixel so that it may be processed differently.

FIR Filter Filtering to sharpen and/or smooth.

Scaler Downscaling or upscaling.

Tetrahedral

Color Converter Converts YCrCb to CMYK with high accuracy.

Screener Halftones CMYK image data in preparation for output to print head (via modulator for laser printer).

Figure 1-5: Image Processing Pipeline

QB63xx Datasheet Revision 1.04 SOC Cores

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2 SOC Cores

CPU Cores

2.1.1 Cortex-A7 CPU 2.1.2 Cache Coherency Interconnect (CCI)

Cortex-A7 CPU

The ARM Cortex-A7 is a powerful, efficient CPU.

Typical uses:

Running system software including device drivers, connectivity stacks and users interface

Running print language software and scan processing software

Key features:

Single or dual CPU cores

32 kB L1 instruction cache per A7 core 32 kB L1 data cache per A7 core

512 kB L2 cache (shared by both A7 cores)

VFPv4 floating point

NEON SIMD extensions MMU with LPAE (Large Physical Address Extension)

Integrated Generic Interrupt Controller (GIC)

Additional features:

Optional secure mode

Ability to power-down one or both A7 cores

JTAG debug with CoreSight Embedded Trace Macro (ETM)

192 Interrupts

Cache Coherency Interconnect (CCI)

The QB63xx incorporates the ARM CoreLink CCI-400 to provide cache coherency. The CCI allows blocks accessing DDR

memory that has been cached in the A7 cache to access data directly in the A7 caches, while ensuring that the cache

contents and DDR contents remain coherent.

Typical uses:

Image buffers when image processing is performed on both hardware blocks and the A7

Data shared between the A7 and the M3

Key features:

Data coherency between the A7 caches and DDR accesses by other blocks

Performance Monitoring Unit (PMU) allows SW tracking of performance-related events


Secure access of configuration

Provides snoop transactions into A7 caches and other masters, thereby avoiding DDR accesses


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Memory Cores

2.2.1 Boot Read-Only Memory (ROM) 2.2.2 One-time Programmable ROM (OTP) 2.2.3 DDR Interface (DDRIF) 2.2.4 QOS and Arbitration 2.2.5 Main Scratchpad (MSP) 2.2.6 Scan Scratchpad (SSP) 2.2.7 Print Scratchpad (PSP)

Boot Read-Only Memory (ROM)

The boot ROM is an on-chip ROM inside QB63xx. This is the first level bootstrap loader to initialize necessary H/W

blocks, and then load the second level of boot code (boot2) from external flash memory. Depending on the sampled

pins and configuration bits in internal one-time-programmable memory (OTP), bootstrap configurations are

determined. Following is the QB63xx built-in boot procedure. The QB63xx B0 supports level 2 boot code from serial

NAND flash.

Power-on / reset:

o Please refer to RSTGEN for more detail.

Level 1 Boot:

o Boot code in internal boot ROM is executed by A7 CPU.

o Depending on the configuration, boot code will load level 2 boot code (boot2 code) from either SPI

NOR/NAND flash or eMMC flash with QB63xx B0.

o Sets up selected flash memory.

o Load the boot2 code from selected flash memory to internal main scratchpad memory.

o Decrypt the boot2 code if necessary (depending on the setting in OTP)

o Transfers execution to boot2 code.

Level 2 Boot: this is rewritable software for the second level of boot code.

o Copies other contents of the flash memory to DDR

o Sets up the A7 CPU to begin executing application level of code including operating system if there is.

One-time Programmable ROM (OTP)

The QB63xx contains a one-time programmable (OTP) memory.

Typical uses:

Storage of system configuration information (bootstrap settings)

Storage of cryptographic keys

User-defined parameters

Key features:

4096 bits (128X32) one-time programmable electrical fuses

Double bits redundancy for improved reliability

Support for secure boot


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DDR Interface (DDRIF)

The DDR SDRAM Interface (DDRIF) provides configurable control and access to external DDR3L or DDR4 for all internal

masters of the SOC.

Key features:

Support for DDR3L and DDR4 JEDEC SDRAM standards

Maximum 2133 MHz DDR (data rate), 1066.5 MHz clock rate

8-bit wide DDR interface

Up to 8Gb DDR3L devices with 2 ranks (16Gb total), or 16Gb DDR4 devices with 2 ranks (32Gb total)


Up to 2 ranks, 17-bits of row addressing, 11-bits of column addressing (for DDR3L 8Gb devices), three bank

addresses (DDR3L) or two bank addresses with two bank groups (DDR4)

Programmable system-to-DRAM address map for flexible RANK placement with up to 36-bit addressability

QOS transaction priority with aging, originating at the start point (master) of each transaction to achieve high

DRAM utilization/performance

All DRAM training supports hardware (HW) training algorithms for reduced software (SW) overhead

Dedicated PLL generates DDR base frequencies independent of system clocks

Additional PLL near the DRAM I/O generates the DRAM clock output directly for improved JEDEC jitter and

duty-cycle performance

Self-Refresh Powerdown (SRPD) mode with HW generated self-refresh entry (SRE) and self-refresh exit (SRX)

with limited to no SW overhead requirements

Impedance measurements for PVT compensated off-chip drive (OCD) and on-die termination (ODT) settings

Independent OCD for address, data, and clock groups

HW analyzer trace (unit) for debugging and performance tuning of DRAM accesses

Refresh interval generation independent for each RANK provides staggered (hidden) refresh

Two exclusive-access monitors

Support for Secure Memory Regions

Supported speeds:

QB63xx Package 14L/14P 19U

Supported DDR3L Speeds 1866 1866

2133

Supported DDR4 Speeds NA 1866

2133

Table 2-1: Supported DDR Speeds

QOS and Arbitration

QOS is the mechanism for prioritizing and arbitrating DDR transactions. It utilizes a system-wide priority

encoding/decoding that is generated for all bus transactions to DDR. This priority is supported by all masters (clients)

generating transactions to DDR.

Typical uses:

Ensure that real-time clients such as the LCD interface, scanner interface, and printer interface and other

clients that require high DDR bandwidth get the DDR bandwidth that they need


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Key features:

Priority level set in client and tracked across busses to the DDR scheduler

Special priority levels for real-time clients

Dynamic allocation of DDR bandwidth by tracking aging/latency of pending transactions

Configurable priority and aging presets and limits


All clients age with an atomic (system-wide) reference

Busses and DDR controller use the same priority scheme

Latency of a transaction across busses, clock-domains, and at the DDR is deterministic

Main Scratchpad (MSP)

The Main Scratchpad (MSP) is a high bandwidth, low latency memory that can be used by numerous processing units.

Typical uses:

Store image data (typically one or more lines) that is used more than once by a processing unit

Store intermediate data calculations for a processing unit

Store image data (typically one or more lines) that is transferred between processing units using the inline

monitor transfer feature (see Inline Monitor section for more details)

Key features:

1 MB total memory

high bandwidth

low latency


Programmable high or low priority per client

Round robin arbitration amongst equal priority clients

Scan Scratchpad (SSP)

The Scan Scratchpad (SSP) is a high bandwidth, low latency memory that can be used by numerous processing units.

Typical uses:

On-chip storage of shading correction table (see Scan Front End section) to minimize DDR traffic

Intermediate buffering of one or two lines of image data for 2-line or 3-line fringe correction (see Scan Front End section) to minimize DDR traffic

Key features:

256 KB total memory

high bandwidth

Low latency when accessed from scanner interface and scan front end (SFE) unit





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Print Scratchpad (PSP)

The Print Scratchpad (PSP) is a high bandwidth, low latency memory that can be used by numerous processing units.

Typical uses:

Intermediate buffering for on-the-fly formatting of print data

On-chip memory for print M3 during low power sleep operation

Key features:

128 KB total memory

high bandwidth

Low latency when accessed from printer interface




System Control Cores

2.3.1 General Purpose DMA (QBDMA) 2.3.2 Linked List DMA (LLDMA) 2.3.3 Reset Generator (RSTGEN) 2.3.4 Clock Generator (CLKGEN) 2.3.5 Timer Unit (TIM)

General Purpose DMA (QBDMA)

The General Purpose DMA (QBDMA) moves data blocks around the SOC.

Typical uses:

Copying data between one buffer in DDR and another buffer in DDR

Copying data between a buffer in DDR and an on-chip memory such as Main Scratchpad

Initializing a buffer or table in DDR or on-chip memory

Key features:

2 QBDMA units

o QBDMA0 has 32-bit data transfers (max 32 bits per clock cycle)

o QBDMA1 has 128-bit data transfers (max 128 bits per clock cycle)

Separate read and write channels that operate concurrently

DMA bursts may be triggered by external interrupts

DMAs may be chained using LLDMA


Data reordering modes

Address repetition mode

Data pattern generation


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Linked List DMA (LLDMA)

The Linked List DMA (LLDMA) is a programmable, instruction based sequencer.

Typical uses:

Program and monitor a DMA controller and corresponding image processing core (IPC)

Key features:

Generates chained DMA transfers decoupled from CPU intervention

CPU can place RegisterBus commands in the LLDMA instruction queue and move on to other tasks while the

LLDMA executes them

CPU can add to the LLDMA instruction queue at any time


Interrupt generation allowed at any point in instruction sequence

Reset Generator (RSTGEN)

The Reset Generator unit (RSTGEN) is the central resource that generates resets for all the units in the QB63xx.

Typical uses:

Generates resets for QB63xx

Key features:

Handles reset inputs:

o Power on reset (POR)

o External reset pin o Chip Watchdog timeout input o Software chip reset

Generates external reset pin output

Distributes reset to QB63xx units

Captures bootstrap settings from pins and OTP


Provides software-controlled reset for each QB63xx unit

Provides software-controlled power and isolation control for QB63xx power islands

Clock Generator (CLKGEN)

The Clock Generator function (CLKGEN) determines the internal clock frequencies for all blocks in the QB63xx.

Typical uses:

Generates the internal clocks for the QB63xx


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Key features:

Three high-frequency PLLs

o SYSPLL up to 2550 MHz, clock source for most blocks

o DDRPLL up to 2400 MHz, clock source for DDR; may also be used for other blocks

o VIDPLL up to 2560 MHz, clock source for laser print sub-pixel clock

Programmable switches, muxes and dividers used to create clocks from PLL sources

Programmable gating for disabling clocks


SYSPLL/DDRPLL/VIDPLL frequency modulation to mitigate electromagnetic emissions

SYSPLL/DDRPLL/VIDPLL low power mode

Timer Unit (TIM)

The timer unit (TIM) provides several kinds of programmable timers.

Typical uses:

Provides periodic interrupt events for operating system

Key features:

System timers

High resolution timers

Watchdog timeout

Scanner and Printer Control Cores

2.4.1 Cortex-M3 2.4.2 Timing Generator (TGEN) 2.4.3 Scanner Interface 2.4.4 Printer Interface (PRI)

Cortex-M3

The QB63xx contains two Cortex-M3 processors, one paired with the Printer Interface and one paired with the

Scanner Interface.

Typical uses:

Printer and scanner mechanism control in conjunction with TGEN

Monitoring activity during low-power operation when the A7 is powered down

Key features:

Two M3 processors: one paired with the Printer Interface and one paired with the Scanner Interface

Custom 16kB 4-way set associative instruction cache and data cache with programmable locking

Page table that provides access to 4 128MB regions of DDR

Optional use of A7 cache coherency (memory accesses from M3 are checked in A7 caches)


20


Mailbox registers to communication with other processors, such as the A7

Debug with trace and cross-trigger

Timing Generator (TGEN)

TGEN is group of configurable timing generator function units that can be used to handle input signals and generate output signals, both external to the SOC and internal to the SOC. There are 3 full-function TGEN modules (TG0, TG1,

and TG2) and 1 small TGEN module (TG3) in 63xx.

The core of the TGEN is the function units, which can be started/stopped by selected events from firmware or other function units. With flexible trigger matrix, TGEN can generate complex waveforms.

Typical uses:

Motor control

Print head control

Key features:

3 full-function TGEN modules TG0, TG1, TG2 each with 32 multi-purpose function units (total 96)

Versatile multi-purpose function units, including:

o PWM outputs: Timer, PWM, Clock, Modulated-PWM

o IO with buffer: Ring-buffer, Fifo

o Event inputs: Single-input, Dual-input, Speed-monitor, Phase-comparator

o GPIO

1 small TGEN module TG3 with 32 limited-function units:

o PWM, GPIO

Flexible trigger control

o Complete trigger source selection from all TGEN units or external events

o Sample/skip control for trigger events

Tightly integration with Cortex-M3 with interrupts from trigger outputs of function units, fast software

coordination. Each Cortex-M3 has a private TGEN.


Selectable logic functions between TGEN unit pairs and signal overlay

Interconnections between TGEN modules, scan interfaces, and print interface to do cross triggering

Scanner Interface

The Scanner Interfaces are designed to control a scanner mechanism and bring in scan image data. Figure 2-1 shows a

typical one-pass 2-side scan system implemented with dual Scanner Interfaces.

Key features:

2 Scanner Interfaces to support 2-side scanning

Support various AFE interfaces:

o LVDS interface with 5 data lanes and 1 clock lane

o 10 bits LVCMOS input with AFE mode and DataPort mode supported

Integration with Scan Front End (SFE) image processing units for on-the-fly image processing


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Support for CCD and CIS sensors, with 9 DMA channels for reassembling data from multi-segment sensors up

to 9 segments

Clock, pulse and PWM generators to create control signals for CCD/CIS, light source and AFE

Integrated with TGEN timing generator and Cortex-M3 processor for motor control


Flexible Switchbox and Capturers to control clocking of input signals and arrange bits into scan data

Color/DMA Tagger to keep track of each pixel’s color and sensor segment

Internal debug data source for development

Scanner Interface 0

Switchbox Capturers Scan Front End

QB63xx SoC

Clock Generators

Scan Device

DMA

TGEN0

AFE

Image SensorLight

SourceImage Source

Motor

Scanner Interface 1

Switchbox Capturers Scan Front End

Clock Generators

DMA

AFE Cortex M3Register

BusScan

ScratchpadMain

Scratchpad

Figure 2-1: Typical Scan System with Scanner Interfaces

Printer Interface (PRI)

The Printer Interface (PRI) takes in image data and synchronization signals to generate data and control signals for

controlling a print mechanism.

Typical uses:

Driving a laser engine, LED engine, inkjet print head or thermal print head

Key features:

8 output channels

o LVDS 1 channel or LVCMOS 1/2/4/8 pins per output channel (max 32 pins total)

o Supports dual-beam color print engines

DMA controllers to read image data into Pixel Data Controller


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Subpixel Processor for laser modulation

o Subpixel clock (quantization clock) from max 2560 MHz video PLL (VPLL)

o Modulator applies a per-channel lookup table to convert 4-bit image data into 8-32 subpixel pulses

o Stretch Unit inserts 0-7 stretch subpixels for laser angle compensation

o Internal beam detect (BD) synchronization to nearest subpixel

o Separate horizontal margin per mirror facet

Heating profile generator for thermal heads

Trapezoidal module for inkjet heads

Switchboard module to select control inputs and combine data with serial video output


Dual Beam module to handle vertical registration for dual beam engines

Dot Counter to estimate toner consumption

Inline monitor support with DSP and JBIG

Image Processing Cores

2.5.1 Image Processing DMA (IPDMA) 2.5.2 Inline Monitor 2.5.3 Scan Front End (SFE) 2.5.4 Scan Back End (SBE) 2.5.5 Segmentation (SEG) 2.5.6 FIR Filter 2.5.7 Scaler (SCL) 2.5.8 Tetrahedral Color Converter (TCC) 2.5.9 Screener 2.5.10 QBit DSP 2.5.11 JPEG Unit (QBJPG) 2.5.12 JBIG Module

Image Processing DMA (IPDMA)

The Image Processing DMA (IPDMA) is a multi-channel DMA controller that provides the DMA transfer capability for

several Image Processing Cores (IPC). For the QB63xx there is an IPDMA in the following units: FIR, SCALER,

SCREENER, and SBE.

Typical uses:

Transfer input image data from DDR or MSP to an IPC

Transfer intermediate data between an IPC and MSP

Transfer output image data from an IPC to DDR or MSP

Key features:

Up to 10 DMA read channels

Up to 4 DMA write channels

Up to 1 embedded LLDMA for virtually unlimited DMA chaining support

Circular buffer mode to optimize use of MSP for reference lines and intermediate calculations

Inline monitor support to reduce DDR accesses and CPU intervention for image transfers

Left to right (L2R) and right to left (R2L) direction support on a line by line basis

Simple val/ack data interface to/from IPC


23


Endian conversion

Channel splitting

Channel throttling

Inline Monitor

Inline Monitor Transfer Support (IMTS) efficiently manages the transfer of image data between image processing blocks. IMTS allows a buffer, typically in Main Scratchpad (MSP), to be managed as a circular buffer. IMTS is useful to help minimize image data transfers to/from DDR by keeping data in on-chip MSP. Note, the processing units perform the transfer via their DMA engines.

Typical uses:

Manage image data in MSP in the flow of an image processing pipeline, such as a copy pipeline, to save DDR

bandwidth

Key features:

IMTS is available for the following units: FIR, TCC, SCRN, DSP, GVIF

IMTS added in B0 for the following units: JBIG, PRI

Manages a circular buffer in memory, typically MSP

Scan Front End (SFE)

The Scan Front End performs several on-fly image correction processes on the pixel data received from the Scanner Interface Capturers. Figure 2-2 shows the architecture of Scanner Front End.

Fringe

Correction Unit

Shading

Correction Unit

1-D

Lookup Unit

Current Line

WriteGain/Offset

Read

Buffer Management Controller

Scanner

Scratchpad

Main

Scratchpad

Corrected

DataPixel

Data

1-D LUT(24k + 256) byte

PVCI Target

White Point

Tracking Unit

PVCI Target

Previous Lines

Read

SCARB SCARB

Figure 2-2: Scanner Front End Architecture

Key features:

2 SFE units to support 2-side scanning

On-fly image processing of scan input in Scan Scratchpad (SSP) memory to minimize DDR bandwidth usage


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Image processing steps:

o 1-D Lookup: compensates for non-linear scan sensor response

o Shading correction: compensates for uneven illumination across the width of scan sensor by applying

an independent offset and gain to each R, G and B pixel in a horizontal scan line

o Vertical color fringe correction: compensates for color fringes that result from slight vertical

misalignment of R, G and B during scanning (R, G and B scanned at slightly different times as scan bar

or paper is moving) by recalculating each R, G and B pixel as a weighted average of itself and the

pixels on the previous two scan lines

o White point tracking: determines the white point of the scanned image, i.e. the level closest to

white, by accumulating histograms for R, G and B; pixel values are averaged with the preceding pixels

horizontally, then the average is counted in the histogram


The order of 1-D Lookup, Shading and Fringe can be programmed in any order

The pipeline design allows operation at 2 cycles per pixel

Support larger scan width with part of the shading or fringe memory located in Main Scratchpad (MSP)

memory

Scan Back End (SBE)

The Scanner Back End (SBE) applies further processing steps to the image from the Scan Front End (SFE). Specifically,

it adjusts the white background level, compensates for non-linear scan sensor response and converts from RGB to YCrCb

color space in preparation for segmentation and FIR filtering.

Typical uses:

During Copy Image processing

During Scan Image processing

Key features:

Two SBE Units (SBE0, SBE1)

White Point Calibration using a programmable 3x4 matrix multiply

Gamma Correction using 3 lookup tables (1 each for R, G and B) of up to 4K x 16-bit entries

RGB to YUV conversion using a selectable matrix multiply with optional square and/or linear combination terms

(3x4, 3x7, 3x8 or 3x11)

Processing speed of up to 1 pixel/4 clocks


Local memory for tables

DMA engines for inputting and outputting image data

Single or Double-Buffered operation

Interface with Segmentation Unit

Segmentation (SEG)

The Segmentation (SEG) unit categorizes each pixel in image data so that it may be processed differently in

subsequent image processing steps. SEG calculates several statistics on each YCC pixel and its neighbors, then

generates a segmentation tag for each pixel as one of four types: 1) gray edge, 2) color edge, 3) transition, 4) photo.


25

Tags may be used by subsequent image processing units including Filter (FIR), Tetrahedral Color Conversion (TCC), and

Screener (SCRN) to apply different parameters to each pixel according to its segmentation tag.

Typical uses:

During copy image processing

Key features:

Two SEG Units (SEG0 used by SBE0, SEG1 used by SBE1)

Generates a segmentation tag for each pixel as one of four types: 1) gray edge, 2) color edge, 3) transition, 4)

photo

Processing speed of up to 1 pixel/4 clocks (same as SBE)

FIR Filter

The FIR filter unit applies a finite impulse response filter (FIR) to image data using a 5x5, 7x7 or 9x9 symmetric filter. The unit can be programmed with different coefficients and configurations for each color plane of image data. The FIR includes programmable DMA engines to transfer image data from/to external DDR memory or internal Main Scratchpad (MSP) memory.

Typical uses:

During Copy Image processing to smooth and/or sharpen image data During Scan Image processing to smooth and/or sharpen image data

Used as a programmable image processing module (IPM) in conjunction with other IPM cores

Key features:

Two FIR units (FIR0, FIR1) Three modes of operation:

o 5x5 filtering for up to 4 color planes, with different coefficients for each plane o 7x7 filtering for 1 color plane plus 5x5 filtering of up to 2 other color planes, with different

coefficients for each plane o 9x9 filtering for 1 color plane

Up to two sets of coefficients per plane selected by segmentation tag plane on a pixel-by-pixel basis Performance of a single FIR unit:

o 5x5 filtering produces one 8-bit output for a given color plane every 4 clocks o 7x7 filtering produces one 8-bit output for a given color plane every 5 clocks o 9x9 filtering produces one 8-bit output for a given color plane every 6 clocks


Min/Max sharpening output filter with programmable min undershoot and max overshoot offsets

Programmable fractional binary point for coefficients

Programmable DMA engines for transferring data from/to DDR or Main Scratchpad

Inline monitor transfer support


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Scaler (SCL)

The scaler module performs upscaling and downscaling of image data.

Typical uses:

Scaling during copy function

Key features:

Horizontal (H) scaling is independent of vertical (V) scaling Upscale range is from 100% to 800% Downscale range is from 6.25% to 100% Upscale uses replication and linear interpolation Downscale uses averaging 8-bit per pixel input and output result


Intermediate results are stored in main scratch pad (MSP) memory with 16-bit per pixel precision 32-bit accumulator Horizontal and vertical cutoff of remainders to avoid rounding errors over a long line Supports preset of vertical remainder for partial scaling of an image (e.g. a full image divided into bands) Integrates an IPDMA/LLDMA unit for managing all I/O to/from DDR and MSP

Tetrahedral Color Converter (TCC)

The Tetrahedral Color Converter (TCC) performs high-quality color space conversion on image data using tetrahedral

interpolation.

Typical uses:

Copy image processing: Convert scanned image data in RGB color space to CMYK for output to a printer

Print processing: Convert RGB image data generated by print interpreter software to CMYK for output to a

printer

For such uses, table coefficients should be generated by doing offline profiles of the printer and scanner

Key features:

Tetrahedral interpolation with 17x17x17 table

Optionally uses image segmentation tag data to select from up to 4 different tables on a pixel-by-pixel basis


Local memory for tables

DMA engines for inputting and outputting image data. Multiple input and output formats supported.

Optional matrix multiply (allows image data already converted from RGB to YCC to be converted back to RGB

before applying tetrahedral conversion)

Single or Double-Buffered Operation

Circular Buffer support for input and output paths. Receive and send data directly from/to other clients


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Screener

The Screener is a programmable unit that implements various screening and error diffusion algorithms on image data for thresholding/halftoning applications. The Screener includes programmable DMA engines to transfer image data to/from external DDR memory and internal Main Scratchpad (MSP) memory.

Typical uses:

During Copy Image processing or Print image processing to halftone image data before printing

Used as a programmable image processing module (IPM) in conjunction with other IPM cores

Key features:

Two Screener units (SCRN0, SCRN1) Eight halftoning algorithms:

o Breadth screening with 1-bit, 2-bit or 4-bit output and low output bit screened o Breadth screening with 1-bit, 2-bit or 4-bit output with all output bits screened o Conventional screening with 2-bit output o Custom screening with 1D output LUT and 2-bit or 4-bit output o Standard error diffusion with 1-bit output o Cluster dot error diffusion (8 error terms) with 1-bit, 2-bit and 4-bit output o Cluster dot error diffusion (10 error terms) with 1-bit, 2-bit and 4-bit output o Custom 5-5-3 error diffusion with 1-bit, 2-bit and 4-bit output

Up to two sets of halftoning parameters selectable by the segmentation tag plane on a pixel-by-pixel basis Integer up-scaling for increasing image resolution before output


Programmable 1D input LUT and 1D output LUT for compensating for non-linear response of printer Support for screen sizes up to 128 x 128 8-bit values Supports left-to-right and right-to-left line scan with programmable direction change interval for error

diffusion algorithms to reduce artifacts Programmable DMA engines for transferring data from/to DDR or Main Scratchpad Inline monitor transfer support

QBit DSP

The QBit DSP is designed specifically for image processing.

Typical uses:

Implement custom image processing such as custom halftoning

Key features:

SIMD architecture – four data paths

Data path designed specifically for image processing with concurrent bit-field extract, multiply, accumulation,

and bit-field insertion within a single instruction

Rich instruction set including exclusive-OR, quad-compare, quad multiply-accumulate, conditional execution,

and dual-extract

DMA tasks or instruction set accesses external-memory resources


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8KB instruction cache

32KB of local memory (LMEM) accessed with 4 32-bit wide concurrent data paths

DMA with:

o formatting features to reduce software overhead for fringe and stride handling

o synchronization features to manage scheduling of input and output data within local-memory

Hardware interrupt capability

Debug features (halt and single step)

JPEG Unit (QBJPG)

The QBJPG unit is a configurable JPEG codec unit that decodes/encodes compressed JPEG image data. The JPEG decoder/encoder transfers data from/to external DDR memory. For more details on the JPEG standard, see the ISO/IEC 10918-1 specification.

Typical uses:

Decode of a JPEG compressed image into color plane data buffers in memory

Encode of color plane data into JPEG compressed image data

Up-sampling of decoded image data after decompression

Down-sampling of source image data prior to compression

Key features:

Two QBJPG units (JPEG0, JPEG1) Decode/encode modes: baseline sequential Subsampling modes: 4:4:4, 4:2:2 horizontal, 4:2:2 vertical, 4:2:0, grayscale Source image with 8-bit samples within each color component Discrete cosine transform (DCT) based compression process Huffman coding with 2 DC and 2 AC tables Quantization with up to three 64-entry tables of 8-bit quantization values


Decoder supports optional up-sampling of decoded color plane data from 4:2:0, 4:2:2 horizontal, or 4:2:2 vertical decoded data to 4:4:4 format for output

Encoder supports optional down-sampling from 4:4:4 input color plane data to 4:2:2 horizontal, 4:2:2 vertical, or 4:2:0 formats prior to encoding

Note: 4:2:0 mode was named 4:1:1 in previous revisions of the User Guide. The functionality has not changed, just

the name.

JBIG Module

The JBIG module provides bitonal compression and decompression functionality for image data.

Typical uses:

Decompressing images from a host

Compressing image data in memory before printing


29

Key features:

Several template-based image compression methods

DMA channel which feeds and drains the JBIG data compression/decompression unit


Unconstrained widths within extreme limits (minimum 1, maximum 65530)

Auxiliary functions to manage its adapter memory array

Connectivity Cores

2.6.1 GMAC 2.6.2 USB Dual Role 1 Port Interface (USDR) 2.6.3 USB Host 2 Port Interface (UH2P)

GMAC

The GMAC interface connects to an external Ethernet PHY to provide wired Ethernet communications.

Typical uses:

Ethernet communications port

Key features:

Supports multiple PHY types

o RGMII (10/100/1000 Mbit/sec)

o RMII (10/100 Mbit/sec)

Enhanced descriptor format

Serial Management Interface (SMI) for communication to PHY

Energy Efficient Ethernet (EEE)


10 unique MAC addresses, useful in filtering

4KB receive and transmit buffers

Packet Filtering

o 4 - Level3 (Network Layer)/ Level 4(Transport layer) filters

o VLAN perfect, and VLAN hash

o Magic Packet

o Remote Wakeup, 4 filters

Monitor and status counters

USB Dual Role 1 Port Interface (USDR)

The Universal Serial Bus (USB) Dual Role 1 Port Interface Unit (USDR) provides 1 USB port that can be configured as a

host or device port, and is used to communicate with a USB external device or host.

Typical uses:

Command and data channel between printer/scanner/MFP and host computer


30

Key features:

1 Dual Role port (host or device)

o USB 3.2 Gen 1x1 SuperSpeed (5 Gbit/s) in 19U package

o USB 2.0 Hi-Speed (480 Mbit/s) in 14L & 19U packages

Host configuration is compliant with the eXtensible Host Controller Interface (xHCI) specification

Supports up to 12 bidirectional endpoints

USB Host 2 Port Interface (UH2P)

The Universal Serial Bus (USB) Host 2 Port Interface Unit (UH2P) provides 2 USB Host ports that are used to

communicate with USB external devices.

Typical uses:

Connect with a USB mass-storage device to provide additional storage space

Connect with a WiFi USB dongle to provide connectivity

Key features:

2 USB 2.0 hi-speed (480 Mbps) host ports

Compliant with the eXtensible Host Controller Interface (xHCI) specification

System Interface Cores

2.7.1 LCD Interface 2.7.2 PCI Express Interface (QBPCIE) 2.7.3 SDIO 2.7.4 Flash Controller SPI Interface (FCSPI) 2.7.5 Extended SPI (SPI) 2.7.6 Inter-Integrated Circuit (I2C) 2.7.7 Serial Port (UART) 2.7.8 General Video Interface (GVIF) 2.7.9 A/D Converter (ADC) 2.7.10 D/A Converter (DAC) 2.7.11 Real-Time Clock (RTC) 2.7.12 General Purpose I/O (GPIO) 2.7.13 JTAG Boundary SCAN (JTAG BS) 2.7.14 Overlay Unit (OVL)

LCD Interface

The QB63xx LCD Interface drives several types of TFT LCD panels, including Serial RGB, LVDS and VX1 type panels.

Typical uses:

Displaying a graphical user interface on an LCD panel

Key features:

Multiple types of LCD panels supported:

o LVDS

o VX1

o Serial RGB (SRGB)


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Up to two overlay windows with Alpha Blending

Frame Sequencing for animation support


LCD panels support

o Serial RGB interface modes

5, 6 or 8-bits/color

o LVDS RGB interface mode

3-channel LVDS (5 or 6-bits/color)

4-channel LVDS (8-bits/color)

o VX1 RGB interface modes

5, 6 or 8-bit/color

3, 4, 5-byte modes

Pixel Duplicating mode

Programmable frame buffer Bits Per Pixel (BPP) color depth

o 1, 2, 4, 8 BPP mapped through color palette

o 16, 18 or 24 BPP direct drive from Frame Buffer

Color palette RAM for reduced frame buffer memory and bus bandwidth

Programmable horizontal and vertical timing parameters

Brightness and Power control for LCD Panel

Power up and down sequencing support

PCI Express Interface (QBPCIE)

The PCI Express (PCIe) Interface Unit (QBPCIE) is used to communicate with a PCIe external unit.

Typical uses:

Transfer data between the QB63xx and an image coprocessor or application processor

Key features:

PCIe Base Specification Revision 2.0 compliant

Dual mode (operates as root complex or end point)

5.0 GB/s per lane

1 lane

Maps accesses from QB63xx internal units (CPU, DSP, etc.) to PCIe external address space

Maps accesses from PCIe external units to QB63xx internal address space (DDR, MSP, registers, etc.)


Built in DMA controllers

PCIe Message Signaled Interrupt Support

PCIe INTX Interrupt Support

SDIO

The SDIO interfaces connect to SD flash memory cards, eMMC flash memories, and SDIO devices.


32

Typical uses:

Connecting an eMMC flash memory as the system boot memory

Connecting a WiFi chip

Connecting an SD card slot

Key features:

3 SDIO ports

SDSC, SDHC, SDXC compatible

1, 4, 8 bit connections

SD transfer modes DS, HS, UHS-I up to SDR104

eMMC transfer modes up to HS200


Auto-tuning available to find optimal sampling window

Multiple boot and DMA modes available

Flash Controller SPI Interface (FCSPI)

The Flash Controller Serial Peripheral Interfaces (FCSPI) provides access to serial NOR and NAND Flash type devices. NAND Flash support is available in QB63xxB0.

Typical uses:

Connect to serial NOR and NAND Flash devices

Key features:

Wide support of industry standard 1-bit, 2-bit, and 4-bit serial NOR/NAND Flash devices

Automatic Device Identification

Communicates with up to two Flash devices

Random access Execute On-The-Fly; CPU can execute directly from Flash


Device-independent: o Supports non-standard Serial Flash devices with configurable memory features o Supports memories that have densities greater than 512 Mbits

Flexible Access Mode o DMA Engine: Efficient block move to/from Flash device

Deep Power-down Mode support to minimize power consumption

Extended SPI (SPI)

The Extended SPI (SPI) is a standard SPI interface with added DMA functionality.

Typical uses:

Communication with SPI devices such as motor drivers and EEPROMs

Key features:

Simple 4-pin interface (1 bit per clock cycle)

Custom command sequences


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4 ports (2 controllers, 2 ports each)


Multiple command modes available

Multiple DMA modes available

2 programmable clocks available for each controller

Inter-Integrated Circuit (I2C)

The I2C is a synchronous and programmable two-wire control bus that provides support for the communications link

between integrated circuits in a system.

Typical uses:

Communication between other I2C modules outside the QB63xx

Key features:

6 I2C ports

Simple two-wire serial interface consisting of only a serial data line (SDA) and a serial clock line (SCL)

Master or slave operation

Software controlled interface


Clock synchronization – pclk (programming clock) and ic_clk (used to create serial clock) are identical; no

meta-stability flops used for data passing between clock domains

7 or 10-bit addressing

Programmable bit for controlling Master commands

Serial Port (UART)

The Serial Port, 16550 UART, serially receives and transmits data to a peripheral, modem or data set. The Serial Port

module is configured through registers to control the word size, baud rate, parity generation/checking and interrupt

generation.

Typical uses:

Data is written from a master (CPU) over the APB bus to the UART, and it is converted to serial form and

transmitted to the destination device

Serial data is also received by the UART and stored for the master (CPU) to read back

Key features:

8 serial ports

Each port can be programmed to either transmit or receive

Optional register-accessed RTS/CTS signals

Software controlled interface

9-bit serial data support

Programmable serial data baud rate

16-byte FIFOs – one each for receiver and transmitter


34


Use of two clocks:

o Asynchronous SCLK – used to generate the serial clock

o PCLK – programming clock

Programmable fractional baud rate support

General Video Interface (GVIF)

The General Video Interface (GVIF) provides a video-style data interface to external logic.

Typical uses:

Transfer data from QB63xx memory to external logic

Key features:

Programmable page sync and line sync output

Video data output 7:0


Programmable edge select for clocking out page sync, line sync and data

Programmable line gap

Programmable mask mode

DMA chaining support using 2 sets of DMA setup registers

Inline monitor transfer support

A/D Converter (ADC)

The A/D Converter (ADC) has 16 multiplexed input channels and a queue controller to program the sampling

sequence of the input channels.

Typical uses:

Analog position for DC motor control

Fuser temperature sensor

Thermal head temperature sensor

Paper type sensor

Key features:

12 bits resolution

16 multiplexed input channels:

o 4 high speed channels, ACH0-ACH3, with sampling rate at 1 cycle per sample

o 11 low speed channels, ACH4-ACH14, with sampling rate of 10 cycles per sample

o ACH15 is an internal channel for on-chip core supply voltage monitoring

Input range:

o ACH0-ACH14: min 0V to max 3.6V

o ACH15: min 0V to max VAVDH

Maximum conversion rate 13.3 MSPS shared among all channels

o Max. conversion rate per channel ACH0-ACH3: 6.65MSPS

o Max. conversion rate per channel ACH4-ACH15: 1.33 MSPS

Queue controller facilitates different samples rates for each input channel


35

Programmable gain (6 bit resolution)

o PGA gain: 0.5 (-6 dB) to 4.0 (12 dB)

Programmable offset adjust (8-bit resolution)

o Offset: -300 mV to +297.66 mV


A single channel may be declared as a critical channel, with upper and lower boundary values. Anytime this

critical channel is sampled and the value is outside the specified range, an interrupt is asserted.

D/A Converter (DAC)

The D/A converter (DAC) provide analog outputs to control external devices that require analog signals.

Typical uses:

Reference voltage for motor driver

Reference voltage for laser scanning unit

Key features:

4 DACs in QB63xx

8-bits resolution

Sample rate at 0.5 Ms/s

3.3V supply operation

Analog output range 0V to DACAVDD33, nominally 3.3V

Output is linear from 0.3V to 3.0V (input range 23 to 232, with DACVRH=1.8V, DACAVD33=3.3V)

INL ±0.75 LSB

DNL ±0.35 LSB

Real-Time Clock (RTC)

The Real-Time Clock (RTC) maintains date, time, alarm and status settings, independent of SOC power state.

Typical uses:

Maintaining the system date and time set by the user

Triggering a task at a specific date/time (alarm)

Store status information for next boot to use

Key features:

External 32.768 KHz crystal

Date/time can be maintained during SOC power-down state using an external battery

TBD uA standby current when powered by the battery


Time can be set as second, minute, and hour

Date can be set as day, month, and year, as well as day of week

Alarm can be set as minute, hour, and day, as well as day of week

1 Hz and 1.024 KHz clocks (divided from 32.768 KHz crystal) can be used for operating system tick interrupt

Alarm clock (1 minute resolution) also available as an interrupt

32-bit general purpose register available for storing information during SOC power-down


36

General Purpose I/O (GPIO)

GPIO signals are under full software control and can be configured as input or output.

There are 30 GPIO signals available through the SYS overlay, 12 GPIO signals available through the DDR overlay, 15

GPIO signal available through the PRT overlay, and 32 GPIO signals available through the SCA overlay. These overlays

can invert signals in either direction and provide glitch filtering as inputs.

When a GPIO is configured as an input, it can generate several interrupts.

Note: TGEN IOs may also be utilized as GPIOs. See Timing Generator (TGEN) section.

JTAG Boundary SCAN (JTAG BS)

JTAG Boundary SCAN in the SOC implements a complete JTAG standard interface used for boundary scan testing in

Test mode.

Typical uses:

Board level testing

Key features:

IEEE 1149.1-compliant JTAG interface

Overlay Unit (OVL)

There are 4 OVL units to connect device pins to any internal core’s signal.

PRT OVL unit handles mostly printer related signals. SCA OVL unit handles mostly scanner related signals. SYS OVL unit routes other system interfaces such as memory, network, and display devices. DDR OVL unit handles some general IO functions.

QB63xx Datasheet Revision 1.04 Signal Description

37

3 Signal Description

The QB63xx contains many peripheral Interfaces. In order to reduce the package size and ball count while maximizing

functionality, many of the QB63xx balls can multiplex up to eight signal functions. This multiplexing is referred to as

“Overlays” in the QB63xx. Below is a summary of the QB63xx interfaces in each package.

Signal Group 19U Balls

14L

Balls

14P Balls

Dual Voltage

Other Functions Notes

DDR3L/4 44 42 42 14L/14P DDR3L only

GPIO (DDR) 8 4 8 1.8, 3.3 SDIO2, UART2, UART5, I2C1

LCD 13 12 12 1.8, 3.3 TGEN1, GVIF, Printer IF Two pins are analog

Print Vx1 8 8 0 Print LVDS

GPIO (PRI) 16 12 16 TGEN2, CIP LED, GVIF, Printer IF, Print LVDS

GPIO (PRI) 8 8 8 TGEN1, TGEN2, Printer IF, CIP LED

Scan LVDS 24 12 12 TGEN0, TGEN1, TGEN2, XSPI1, UART3, UART4, Scan IF

GPIO (SCA) 8 5 5 TGEN0, TGEN1, TGEN2, XSPI1, UART3, UART4, Scan IF

Motor Control 8 2 2 TGEN0, TGEN1, TGEN2, UART3, UART4, Scan IF

USB Dual Role 7 7 7

USB Hosts 4 4 4 14P: One USB Host

RGMII 15 15 15 1.8, 3.3 UART0, UART1, SYSPIO, SPI, SDIO0, I2C0, TGEN2/TGEN3(10pins)*

PCIe 6 0 0

SPI 5 4 4 1.8, 3.3 TGEN0, SCAPIO 14L/14P: One SPI Chip Select

QSPI 7 6 6 1.8, 3.3 DDRPIO, UART2, I2C1 14L/14P: One QSPI Chip Select

SDIO0 6 0 0 1.8, 3.3 SYSPIO, UART0, UART1, SPI

SDIO1 6 6 6 1.8, 3.3 SYSPIO, UART0, UART1, SPI, I2C0, TGEN2/TGEN3*

SDIO2 6 6 6 1.8, 3.3 SCAPIO, SPI

GPIO (SYS) 8 0 0 1.8, 3.3 UART1, UART2, UART3, UART4, CIP UI, SPI

GPIO (SYS) 8 8 8 1.8, 3.3 UART0, UART1, XSPI, I2C0, SDIO1, SDIO2, CIP UI

GPIO (SYS) 8 0 0 1.8, 3.3 UART0, UART1, XSPI, I2C0, SDIO0

ADC 15 9 15 TGEN0, TGEN1, TGEN2, PRTPIO, UART5, UART6, UART7, Print IF

DAC 4 4 0 TGEN0, TGEN1, TGEN2, UART3, UART4, Scan IF

RTC 2 2 2

XIN 2 2 2

Test 8 8 8

Power/Ground 178 103 101

*63xxA0/63xxB0

Table 3-1: Interfaces in Each Package

QB63xx Datasheet Revision 1.04 Signal Description

38

Below lists the number of balls that can be used for GPIO or TGEN IO in each package.

Ball Function 19U Balls 14L Balls 14P Balls

GPIO 120 72 82

TGEN IO 115 82 88

GPIO or TGEN IO 168 108 118

Table 3-2: GPIOs and TGEN IOs in Each Package

QB63xx Datasheet Revision 1.04 Electrical Specifications

39

4 Electrical Specifications Absolute Maximum Ratings

For more information, see the specifications listed in the following table.

Parameter Description MIN MAX UNIT

VDDSD2 Supply voltage range for SDIO2 LVCMOS IO domain -0.5 3.63 V


VDDQSPI Supply voltage range for QSPI LVCMOS IO domain -0.5 3.63 V

VDDQ Supply voltage range for DDR SSTL IO domain DDR3L

DDR4

-0.4 1.98

-0.4 1.5 V

VDDBAT Supply voltage range for RTC core domain -0.5 1.50 V

VDDDP0 Supply voltage range for GPIO (DDR) LVCMOS IO domain -0.5 3.63 V

VDDLCD Supply voltage range for LCD LVCMOS/LVDS IO domain -0.5 3.63 V

VDDIO_PTX Supply voltage range for LCD and Print Vx1 IO domain -0.3 1.98 V

VDDPRI Supply voltage range for GPIO (PRI) LVCMOS/LVDS IO domain -0.5 3.63 V


VDDGP2 Supply voltage range for GPIO2 (SYS) LVCMOS IO domain -0.5 3.63 V

VDDUSBD Supply voltage range for USB Dual Role PHY -0.5 3.63 V


VDDUSBH Supply voltage range for USB Host PHY -0.5 3.63 V


VDDRGMI1 Supply voltage range for RGMI1 LVCMOS IO domain -0.5 3.63 V

VDDRGMI0 Supply voltage range for RGMI0 LVCMOS IO domain -0.5 3.63 V

VDDAM Supply voltage range for ACH Analog and MOT LVCMOS IO domain -0.5 3.63 V

AVDD18 Supply voltage range for PCIe PHY -0.5 1.98 V

VDDSCA Supply voltage range for GPIO (SCA) LVCMOS/LVDS IO domain -0.5 3.63 V

VDDSPI Supply voltage range for SPI LVCMOS IO domain -0.5 3.63 V

VDD18VPLL Supply voltage range for Video PLL -0.5 1.98 V

VDD1PVPLL Supply voltage range for DDR PLL -0.5 1.98 V

VDD18PLL Supply voltage range for SYS PLL -0.5 1.98 V

AVDD09 Supply voltage range for PCIe PHY logic domain -0.5 0.99 V

VDDIO18_E Supply voltage range for USB IO domain -0.5 1.98 V

VDDIO18_W Supply voltage range for LVDS TX IO domain -0.5 1.98 V

VDD09USB Supply voltage range for USB PHY logic domain -0.5 0.99 V

VDD18SR1 Supply voltage range for SCAN1 LVDS IO domain -0.5 1.98 V

VDD18SR0 Supply voltage range for SCAN0 LVDS IO domain -0.5 1.98 V

VDD09 Supply voltage range for core logic domain -0.5 0.99 V

DACAVD33 Supply voltage for DAC analog power -0.5 4.60 V

DACAVDH Supply voltage for DAC analog power -0.5 2.50 V

ADCAVDH Supply voltage for ADC analog power -0.5 2.50 V

CAVREF Supply voltage range for DDR VREF -0.3 1.1 V

ESD-HBM Electrostatic Discharge - Human Body Model Damage Immunity 2000 V

ESD-CDM Electrostatic Discharge - Charge Device Model Damage Immunity 500 V

Table 4-1: Absolute Maximum Ratings


40

Recommended Operating Conditions

Parameter Description MIN TYP MAX UNIT

VDDSD2 Supply voltage range for SDIO2 LVCMOS IO domain 3.3v

1.8v 3.135 3.3 3.465

1.71 1.8 1.89 V

VDDSD0 Supply voltage range for SDIO0 LVCMOS IO domain 3.3v 1.8v

3.135 3.3 3.465

1.71 1.8 1.89 V

VDDQSPI Supply voltage range for QSPI LVCMOS IO domain 3.3v

1.8v 3.135 3.3 3.465

1.71 1.8 1.89 V

VDDQ Supply voltage range for DDR SSTL IO domain DDR3L

DDR4

1.28 1.35 1.45

1.14 1.2 1.26 V

VDDBAT Supply voltage range for RTC core domain 0.9 1.5 V

VDDDP0 Supply voltage range for GPIO (DDR) LVCMOS IO domain 3.135 3.3 3.465 V

VDDLCD Supply voltage range for LCD LVCMOS/LVDS IO domain 3.135 3.3 3.465 V

VDDIO_PTX Supply voltage range for LCD and Print Vx1 IO domain 1.71 1.8 1.89 V

VDDPRI Supply voltage range for GPIO (PRI) LVCMOS/LVDS IO domain 3.135 3.3 3.465 V

VDDSD1 Supply voltage range for SDIO1 LVCMOS IO domain 3.3v

1.8v

3.135 3.3 3.465

1.71 1.8 1.89 V

VDDGP2 Supply voltage range for GPIO2 (SYS) LVCMOS IO domain 3.135 3.3 3.465 V

VDDUSBD Supply voltage range for USB Dual Role PHY 3.135 3.3 3.465 V


VDDUSBH Supply voltage range for USB Host PHY 3.135 3.3 3.465 V


VDDRGMI1 Supply voltage range for RGMI1 LVCMOS IO domain 3.3v

1.8v

3.135 3.3 3.465

1.71 1.8 1.89 V

VDDRGMI0 Supply voltage range for RGMI0 LVCMOS IO domain 3.3v

1.8v

3.135 3.3 3.465

1.71 1.8 1.89 V

VDDAM Supply voltage range for ACH Analog & MOT LVCMOS IO domain 3.135 3.3 3.465 V

AVDD18 Supply voltage range for PCIe PHY 1.71 1.8 1.89 V

VDDSCA Supply voltage range for GPIO (SCA) LVCMOS/LVDS IO domain 3.135 3.3 3.465 V

VDDSPI Supply voltage range for SPI LVCMOS IO domain 3.135 3.3 3.465 V

VDD18VPLL Supply voltage range for Video PLL 1.71 1.8 1.89 V

VDD1PVPLL Supply voltage range for DDR PLL 1.71 1.8 1.89 V

VDD18PLL Supply voltage range for SYS PLL 1.71 1.8 1.89 V

AVDD09 Supply voltage range for PCIe PHY logic domain 0.855 0.9 0.945 V

VDDIO18_E Supply voltage range for USB IO domain 1.71 1.8 1.89 V

VDDIO18_W Supply voltage range for LVDS TX IO domain 1.71 1.8 1.89 V

VDD09USB Supply voltage range for USB PHY logic domain 0.855 0.9 0.945 V

VDD18SR1 Supply voltage range for SCAN1 LVDS IO domain 1.71 1.8 1.89 V

VDD18SR0 Supply voltage range for SCAN0 LVDS IO domain 1.71 1.8 1.89 V

VDD09 Supply voltage range for core logic domain Normal

Overdrive

0.877 0.89 0.903

0.926 0.94 0.954 V

DACAVD33

Supply voltage for DAC analog power

Note: DACAVDD33 should be the same as VDDAM and must not

exceed VDDAM+0.3V at any time.

3.135 3.3 3.465 V

DACAVDH Supply voltage for DAC analog power 1.71 1.8 1.89 V

ADCAVDH Supply voltage for ADC analog power 1.71 1.8 1.89 V

Table 4-2: Recommended Operating Conditions


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Operational Conditions – LVCMOS IO

Parameter Description Value Units

VDVDD I/O supply voltage range -0.5 to 3.63 V

VPAD Voltage range at IO -0.5 to (VDVDD + 0.5) V


Parameter Description Min Typ Max Units

VDVDD I/O supply voltage 3.135 3.3 3.465 V

VPAD Voltage at IO -0.3 VDVDD + 0.3 V

VIH High-level input voltage at IO 2 VDVDD + 0.3 V

VIL Low-level input voltage at IO - 0.3 0.8 V

VHYS[1] Input Hysteresis Voltage 0.2 V

[1] When SMT = 1. Table 4-4: Recommended Operating Conditions [3.3V Logic]




VIH High-level input voltage at IO 0.65 * VDVDD VDVDD + 0.3 V

VIL Low-level input voltage at IO - 0.3 0.35 * VDVDD V

VHYS[1] Input Hysteresis Voltage 0.1 * VDVDD V

[1] When SMT = 1. Table 4-5: Recommended Operating Conditions [1.8V Logic]

Operation Conditions – LVDS TX IO



VPAD Voltage range at IO -0.5 to 3.63V V


Parameter Description Min Nom Max Units



VIH High-level input voltage at IO 0.7 * VDVDD VDVDD + 0.3 V

VIL Low-level input voltage at IO - 0.3 0.3 * VDVDD V



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Operation Conditions – Oscillator IO



VPAD Voltage range at IO -0.5 to (VDVDD + 0.5) V



VDVDD I/O supply voltage options 3.135 3.3 3.465 V

1.71 1.8 1.89 V

VPAD Voltage at XIN [1] 0 VDVDD V

[1] RTC_XI can be driven by an external clock for bypass operation. XO should never be driven or loaded by anything other than the oscillator crystal.


IO Operation Conditions – Oscillator IO (RTC)


VDDBAT I/O supply voltage range -0.5 to 1.50 V

VPAD Voltage range at IO -0.5 to (VDDBAT + 0.5) V



VDDBAT I/O supply voltage 0.9 1.50 V

VPAD Voltage at RTC_XI [1] 0 VDDBAT V

[1] RTC_XI can be driven by an external clock for bypass operation. XO should never be driven or loaded by anything other than the oscillator crystal.



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AC Parameters and Controls – LVCMOS IO

Inputs Output OEN P2 P1 I IO

0 - - 0 0 1 1

1

0 0 - Z (Normal operation)

0 1 - Weak 1 (Pull-up) 1 0 - Weak 0 (Pull-down)

1 1 - Repeater (Bus keeper)

Table 4-12: Transmit (OEN) and Driver Disable State Control (P2, P1) Truth Table

E2 E1 Rated Drive Strength 0 0 2mA

0 1 4mA 1 0 8mA 1 1 N/A

Table 4-13: Output Drive Strength Selection (E2, E1)

Parameter Condition E2 E1 Min Max Units

VOH

IOH= 2ma 0 0

VDVDD-0.4 V IOH= 4ma 0 1

IOH= 8ma 1 0 N/A 1 1

VOL

IOH= 2ma 0 0

0.4 V IOH= 4ma 0 1 IOH= 8ma 1 0

N/A 1 1

Table 4-14: Static Output Voltage

DC Characteristics – LVDS TX IO


VOH High-level output voltage 1220 1280 1380 V

VOL Low-level output voltage 890 920 1020 V

|VOD| Differential output voltage 250 345 446 V

QB63xx Datasheet Revision 1.04 Package Information

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5 Package Information Overview

The QB63xx is available in three packages/pinouts to fit the range of cost and functionality tradeoffs customers would

like to address in their products.

Package Code Package Pinout

14L 14 = FBGA 14mmx14mm, 0.8mm pitch L = Laser/LED (more pins as LVDS interfaces)

14P 14 = FBGA 14mmx14mm, 0.8mm pitch P = Photo (more pins as LVCMOS interfaces)

19U 19 = FBGA 19mmx19mm, 0.8mm pitch U = Universal

This chapter describes the mechanical parameters, ballouts and thermal parameters of the packages.

Mechanical Package Information

The drawings below show the mechanical dimensions and tolerances of the packages. The 14L and 14P package are

mechanically identical FBGAs with a 14mmx14mm footprint and the 19U package is a 19mmx19mm FBGA.


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Figure 5-1: 14L and 14P Package Mechanical Outline


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Figure 5-2: 19U Package Mechanical Outline


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Package Ballout Information

The diagrams below show the ball maps for the three packages.

The packages have two ball maps each, one for the support of DDR3L and one for the support of DDR4.

Figure 5-3: 14L Package DDR3L Ball Map (Top View through Package)


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Note: Balls H16, H17 were changed from GPIO08, GPIO09 on A0 to HDM1, HDP1 on B0.

Figure 5-4: 14P Package DDR3L Ball Map (Top View through Package)


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Figure 5-5: 19U Package DDR3L Ball Map (Top View through Package)


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Figure 5-6: 19U Package DDR4 Ball Map (Top View through Package)

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