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Copyright T-Buck DDI 2006

1

Power Distribution Basics

By

Tom Buck

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Overview

Current capacity and temperature rise

De-coupling and buried capacitance

Buried resistors

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PWB Power Distribution

Natural convection limit

Proper design is essential for proper operation as signalspeeds go in the GHz range

PWB power distribution must maintain a low impedancethrough a broad frequency spectrum to include harmonics

As circuit speeds increase the inductance of smaller andsmaller PWB elements become critical

Proper placement of bypass capacitance is critical

Above several hundred MHz internal distributed planecapacitance is essential to maintain low impedance

Design Considerations:

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DC Resistance Copper Traces

Base width (bw)

Top width (tw)

Thickness(tk)

R = Resistance in ohms

L = Length in inches

= Copper conductivity

6.787 x 10-7

= Temperature coefficient

0.0039 for copper

Temp = Temperature riseDegrees C

R =L x

(Bw - (bw - tw)/2) x tk(1 + (Temp - 20) x

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Copper Weight oz

= 0.5oz

= 1.0oz

= 2.0

oz

Etch factor accountedfor in trace width

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Copper Weight oz

= 0.5oz

= 1.0oz

= 2.0

oz


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Copper Weight oz

= 0.5oz

= 1.0oz

= 2.0

oz


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Copper Weight oz

= 0.5oz

= 1.0oz

= 2.0

oz


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Current Capacity & Density vsTemperature Rise

= 5C= 10C

= 15C

= 20C

= 25C

Temperature Rise

Degrees C

Data Based on DN 1968

0 1.27 (50) 2.54 (100) 3.81 (150) 5.08 (200)

Trace width in mm (mils)

0 1.27 (50) 2.54 (100) 3.81 (150) 5.08 (200)


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= 5C= 10

C

= 15C

= 20C

= 25C

Temperature RiseDegrees C

Data Based on IPC

(External Traces)

0 1.27 (50) 2.54 (100) 3.81 (150) 5.08 (200)


0 1.27 (50) 2.54 (100) 3.81 (150) 5.08 (200)


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= 5C= 10

C

= 15C

= 20C

= 25C

Temperature RiseDegrees C

Data Based on IPC

(Internal Traces)

0 1.27 (50) 2.54 (100) 3.81 (150) 5.08 (200)


0 1.27 (50) 2.54 (100) 3.81 (150) 5.08 (200)


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Cu Foil Power Dissipation vs CurrentDensity

= 2.0

oz

= 1.0oz

= 0.5oz

Copper Foil Weights


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Overview



Buried resistors

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PWB Power Distribution Elements


Off board power supply and associated wiring

(high inductance)

On board DC:DC converters

Board level bypass capacitors for low

frequency

Distributed bypass capacitors for bypass up to

a few hundred MHz

Distributed embedded plane capacitance forbypass to about 1 GHz

Advanced distributed embedded plane

capacitance materials for bypass to several

GHz

Supply Elements:

PWB Inductance: Trace inductance to bypass caps and components

Cu Plane sheet inductance

Via hole inductance

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PWB Power Distribution Impedance


Imped

anceinOhms

Discretewiring

inductance

Board levelde-coupling

DistributedbypassCaps

Power&

Groundplanes

Package levelinductance &Capacitance

Discrete wire inductance

Board level de-couplingcapacitance

Distributed de-couplingcapacitance

Parallel plane capacitance(power & Ground)

PWB Supplyimpedance

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Parallel Plane Impedance


Plane separation in mils

pF/in2 nH/Square

Inductance

Capacitance

Based on FR-4 r = 4.3

Inductance & Capacitance as a function of plane separation

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Bypass Capacitor Placement

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Bypass Capacitance Requirements

Minimum capacitance value per device I/O

Cmin =I

2 FRTV

Where:

Cmin

= Capacitance

I = Peek I/O drive current

V = Supply noise level

FRT = Spectral envelope

(Signal rise time)RT = Signal rise time*

FRT

=

0.35

RT10%-90% * Use slowest rated rise time of the devise tocalculate capacitance to allow proper bypasslower frequencies since the cap will pass higherfrequencies until it is limited by series inductance

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Maximum series inductance to the bypass capacitor

Lmax =

V

2 FRTI

Where:

Lmax = InductanceI = Peek I/O drive current

V = Supply noise level

FRT = Spectral envelope

(Signal rise time)

RT = Signal rise time*

Natural convection limitFRT

=

0.35

RT10%-90%* Use fastest rated rise time of the devise tocalculate inductance since the inductance willpass the lower frequencies

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Bypass Capacitor AC Impedance

Xac(F) =

Where:

Xac = Impedance in ohms

RESR= Effective Series Resistance

L = Series InductanceC = Capacitance

R2ES

R

+ 2FL -1

2F

C

3

OK

2

ohms

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Return Currents

+

-

Return current (I)

Signal current (I)

Ground Plane

Signal Trace

PWB Dielectric

CMOS DriverBypass Cap

ERS

L

C

I

on

off

+

-

Return current (I/2)

Signal current (I)

Ground Plane

Signal Trace

PWB Dielectric

CMOS DriverBypass Cap

ERS

L

C

I/2

on

off

Return current (I/2)Power Plane

Microstrip

Symmetric Stripline

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Return Path Considerations


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Increased inductance forhigh frequency currents

Increased radiation (EMI)

Higher crosstalk

Elevated noise levels inboth power and ground

Design Considerations

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Simple plane split

Plane return current path(100 MHz)

Signal

Path

Planesplit

Complex plane split

Signalpath

Plane return current path

Plane return current pathwith split removed

Data Source: Zuken

More complex plane splits result

in less intuitive return paths

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External plane fills are difficult to implementon fine pitch components due to the large

geometry required by through holes

Via-In-Pad allow easy external planefills reducing the return path loop area

and lowering signal path inductance

LoopArea

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Low inductancemicrovia (0.22 nH) Through hole signal via

Ground plane

Power plane

Single plypre-preg layer(106 or 1080)0.002 TO 0.003

Thin dielectric layers yield approximately 400-500 pf/in.^2

Reduced plane separation reduces sheet inductance

Laser drilled vias significantly reduce hole barrel inductance

Laser drilled vias reduce anti-pad plane voiding

External plane layers are Cu foil + electroplated Cu (0.002 thick)

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Planar Embedded CapacitanceTechnologies


BC 2000 (0.002 +/- .0005) 503 pF/in106E-glass - Isola, Polyclad, & MEM

BC 1000 (0.001) 1200 pF/in.2

3M C-Ply (0.0003) 10 nF/in.2 & (0.0008) 4

nf/in.2 Ceramic filled epoxy

MEM BC 2000 (.001 +/- .0002) 1200 pF/inUltra-m E-glass

Gould TCC (.002 +/- .0003) 740 pF/inPolyimide Film (0.0005 @ 1400 pF /in )

Oak-Mitsui Farad-Flex (0.00063) 1500 pF/in Dupont InterraTM HK4 Series polyimide (18/25

m) 800 pF/ 1100 pF

Dupont InterraTM HK9 Series ceramic filled

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Planar Embedded Capacitance Technologies


Capacitance per unit area is

proportional to K and inversely

proportional to d

Capacitance between planes in

PCBs is reduced by anti-pads

Copper Plane

Dielectric (r) Thickness (d)

Copper Plane

Simple Thin Film Capacitor

C =K 0 A

d

Where:

C = Capacitance (F/m2)K = Dielectric constant (r)

o = 8.85-12

A = Area (m2)

d = Thickness (m)

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= 3

= 4

= 5

DielectricConstant

= 2

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3M C-Ply Distributed embeddedcapacitance layer

1oz copper panes

3M C-Ply Dielectric layer

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Dupont InterraTM

planar embeddedcapacitance material

Polyimide Dielectric


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Source:SunMicrosystems


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Power Distribution


Data from NCMS Embedded Decoupling Capacitance Project Report - 12/00

(Time Domain - 50 MHz)

Power Bus Noise

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Data from NCMS Embedded Decoupling Capacitance Project Report - 12/00

-40

-35

-30

-25

-20

-15

-10

-5

0

5

No Caps (FR4) Decoupling Caps BC2000 EmCap HiK DuPont 3M C-Ply

1MHz to 1GHz

1 GHz to 3 GHz

3 GHz to 5 GHz

Power Bus Noise

Data normalized to FR-4 with no caps

Power Distribution

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RLC relationships for 1.0 mm array patterns

Simulations cover a range of antipad diametersthat could be encountered with mechanicaldrilling and laser drilling

1.0 oz copper planes Copper planes are separated by 50 mm (0.002)

Dielectric constant of 4.0

Temperature of 20 degrees C

Current density (j) in amps/meter

Power Distribution

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Current Density : 1.0 mm Array Pattern

1.0 mm Array pattern: 0.76mm (0.030) anti-pads

1oz copper50m dielectric

r = 4.0

Currentflow

R= 1.433 x 10-3

L= 1.55 x 10-10

C= 4.695 x 10-12

R= 5.656 x 10-4

L= 8.021 x 10-11

C= 6.884 x 10-12

Solid planes Anti-pads

R= 253%

L= 193%

C= -31.8%

Change

0.76 mm (0.030) dia. Anti-pad

Area = 1.395 x 10-2 in.2

Anti-Pad Area = 6.36 x 10-3 in.2 Area = - 45.6%

Area = 9.0 x 10-2 cm.2

Anti-Pad Area = 4.1 x 10-2 cm2

Area = - 45.6%

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1.0 mm Array pattern: 0.63 mm (0.025) anti-pads

1oz copper50 m dielectric

r = 4.0

Currentflow

R= 1.036 x 10-3

L= 1.228 x 10-10

C= 5.448 x 10-12

R= 5.656 x 10-4

L= 8.021 x 10-11

C= 6.884 x 10-12


R= 183%

L= 153%

C= -20.8%

Change


Area = 1.395 x 10-2 in.2


Area = 9.0 x 10-2 cm.2

Anti-Pad Area = 2.85 x 10-2 cm.2

Area = - 31.7%

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r = 4.0

Currentflow

R= 8.206 x 10-4

L= 1.025 x 10-10

C= 6.048 x 10-12

R= 5.656 x 10-4

L= 8.021 x 10-11

C= 6.884 x 10-12


R= 145%

L= 127%

C= -12.1%

Change

.051 mm (0.020) dia. Anti-pad

Area = 1.395 x 10-2 in.2


Area = 9.0 x 10-2 cm.2

Anti-Pad Area = 1.82 x 10-2

cm.2

Area = - 20.26%

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r = 4.0

Currentflow

R= 6.907 x 10-4

L= 9.016 x 10-11

C= 6.488 x 10-12

R= 5.656 x 10-4

L= 8.021 x 10-11

C= 6.884 x 10-12


R= 122%

L= 112%

C= -5.75%

Change


Area = 1.395 x 10-2 in.2

Anti-Pad Area = 1.59 x 10-3 in.2

Area = - 11.4%

Area = 9.0 x 10-2 cm.2

Anti-Pad Area = 1.03 x 10-2 cm.2 Area = - 11.4%

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RLC as a Function of Copper Area 1.0 mm Array

3 mm square9 anti-pads1 oz copper50 m dielectric

er 4.0

Anti-Pad Data Points

(mil)15

202530

(mm)0.381

0.5080.6350.762

Array Details

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3 mm square9 anti-pads1 oz copper50 m dielectric

er 4.0


(mil)15

202530

(mm)0.381

0.5080.6350.762

Array Details

M i i i C O 1 0 A

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Maximizing Copper On 1.0 mm ArraysUsing Blind Vias


Using alternating blind and through holes onarray patterns will increase the copper areawithin an array pattern thereby:

Reducing the plane resistance

Reduce the plane inductance

Increase capacitance when using plane pairs forde-coupling

Improve thermal performance

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Channel Generation With Via Structures

1.0 mm Array pattern with alternating blind vias

48.8mils

BGA land pad

0.010 via, 0.020 Pad

0.010 blind via, 0.020 Pad

Bused copper, lower

resistance & Inductance

0.030 Anti-pad

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Channel Generation With Via Structures

1.0 mm Array pattern with alternating blind vias

BGA land pad

0.010 via, 0.020 Pad

0.010 blind via, 0.020 Pad

Bused copper, lower

resistance & Inductanceincreased capacitance

0.030 Anti-pad

0.00

2

Plane pairs

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1.0 mm Array pattern: 0.030 anti-pads

1oz copper0.002 dielectric

r = 4.0

Currentflow

R= 8.513 x 10-4

L= 1.002 x 10-10

C= 4.96 x 10-12

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Current Density : 1.0 x 2.0 mm Array Pattern

1.0 x 2.0 mm Array pattern: 0.030 anti-pads


r = 4.0

Currentflow

R= 6.297 x 10-4

L= 8.244 x 10-11

C= 5.48 x 10-12

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Power Distribution


RLC relationships for 0.8 mm array patterns

Simulations cover a range of antipad diametersthat could be encountered with mechanicaldrilling and laser drilling

1.0 oz copper planes Copper planes are separated by 50 mm (0.002)

Dielectric constant of 4.0

Temperature of 20 degrees C

Current density (j) in amps/meter

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r = 4.0

Currentflow

R= 2.324 x 10-3

L= 1.939 x 10-10

C= 2.583 x 10-12

R= 5.656 x 10-4

L= 7.908 x 10-11

C= 4.498 x 10-12

Solid planes Anti-padsR= 411%

L= 245%

C= - 42.5%

Change

Area = 8.93 x 10-3 in.2


Area = 5.76 x 10-2 cm.2


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r = 4.0

Currentflow

R= 1.305 x 10-3

L= 1.363 x 10-10

C= 3.28 x 10-12

R= 5.656 x 10-4

L= 7.908 x 10-11

C= 4.498 x 10-12


R= 230%

L= 172%

C= - 27.1%

Change

Area = 8.93 x 10-3 in.2


Area = 5.76 x 10-2 cm.2


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r = 4.0

Currentflow

R= 9.126 x 10-4

L= 1.069 x 10-10

C= 3.824 x 10-12

R= 5.656 x 10-4

L= 7.908 x 10-11

C= 4.498 x 10-12


R= 161%

L= 150%

C= - 14.98%

Change

Area = 8.93 x 10-3 in.2


Area = 5.76 x 10-2 cm.2

Anti-Pad Area = 1.48 x 10

-2

cm.

2

Area = - 25.65%

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r = 4.0

Currentflow

R= 6.922 x 10-4

L= 8.796 x 10-11

C= 4.263 x 10-12

R= 5.656 x 10-4

L= 7.908 x 10-11

C= 4.498 x 10-12


R= 103%

L= 111%

C= - 5.22%

Change

Area = 8.93 x 10-3 in.2


Area = 5.76 x 10-2 cm.2


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2.4 mm square9 anti-pads1 oz copper50 m dielectric

er 4.0


(mil)12

182328

(mm)0.304

0.4570.5840.711

Array Details


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2.4 mm square9 anti-pads1 oz copper50 m dielectric

er 4.0


(mil)12

182328

(mm)0.304

0.4570.5840.711

Array Details


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Overview



Buried resistors

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Embedded Resistor Technology


Advantages:

Increase Active Circuit Density

Replace discrete resistors

Build resistors inside the PWB

Reduce board size

Convert boards to single sidedSMT

Improved Electrical Performance

Reduce signal path length toresistors

Lower inductance

Reduce surface EMI

Improve signal integrity

Improved Reliability

Eliminate solder joints

Increase board testability

Reduce holes and vias Simplify rework

Reduce Cost

Eliminate discrete resistors Reduce rework

Reduce board size

Increase yield

Source: Ohmega Technologies Inc.

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PhotoResist

PhotoResist

PhotoResist

PhotoResist

Copper

Copper

Copper

Copper Copper

Copper

Copper

Copper

Base Laminate Base Laminate

Base Laminate Base Laminate

Basic Process Sequence

Step 1: Apply photo resist

Step 2: Primary Image copperisolation area and develop

Step 3: Chemically etch copper

Step 4: Chemically etch nickelresistor layer forming the resistor


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Step 5: Strip photo resist

Step 6: Apply photo resist forsecondary image

Step 7: Image and develop resistorgeometry for precise resistance value

Step 8: Strip photo resist and testfor resistance values

Basic Process Sequence

Finished Resistor


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Embedded Resistor Within A Plane Layer


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Resistors on an internal signal layer

Via hole land pad

Low resistance copper

High resistance nickelresistor element


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25 ohm 25 ohm25 ohm

Increasing power dissipation

2 x 25 ohm/square= 50 ohm



Increasing resistanceL

W

Resistance = (L x W) x Sheet Resistance


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33 ohm resistor example

Resistor widt1h = 27 milsResistor length = 36 milsSheet resistance = 25 ohms/square

R= (36/27) * 25 = 33.3 ohms

R = (L x W) x Sheet Resistance

Where:


E b dd d R i T h l

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Variation sheet resistance dueto thickness

Copper etching tolerance Nickel etching tolerance

Temperature

Source of resistance variations


E b dd d R i t T h l

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Serpentine ResistorsCorner squares have lower resistanceR= 0.56 * Sheet resistance

Example using 100 ohm/square material

Total squares = 20Non-corner squares = 16Corner squares = 4

Resistance = (16 * 100) + (4 * 0.56 * 100)

Resistance = 1824 ohms



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Serpentine Resistors

Low resistance copper barseliminate the corner resistanceof the nickel resistive layer

Total squares = 14Non-corner squares = 14Corner squares = 0

Resistance = 14 * 100 = 1400 ohms

Example using 100 ohm/square material



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100 1000 10000

0.1

1

10

45o C

70o C

110o C

140o C

Time in hours

%Changeinresistance

Resistor Stability vs Temperature

Data Source: Ohmega Technologies Inc



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200 400 600 800 10000

0

20

40

6080

100

120

140160

Power dissipation in mWT

emperaturerise

indegreesC

R1

R2R3R4R5

Temperature vs Power Density


R1= 25 ohm (0.500 x 0.500) = 0.2500 in.2

R2= 25 ohm (0.250 x 0.250) = 0.0625 in.2

R3= 25 ohm (0.125 x 0.125) = 0.0156 in.2

R4= 25 ohm (0.063 x 0.063) = 0.0039 in.

2

R5= 25 ohm (0.031 x 0.031) = 0.0096 in.2

Resistance Size Area



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10 20 30 40 50 60 70 80 90 10000

20

40

60

80

100

120

140

160

180200 R1

R2

R3 R4R5 R6

Power density in watts/in.2

TemperatureriseindegreesC

Temperature vs Power Density


R1= 250 ohmR2= 250 ohmR3= 250 ohmR4= 250 ohm

R5= 250 ohmR6= 250 ohm

0.00250.00250.0250.025

0.0620.062

1R25/0 (unclad)1R25/1 (Clad)1R25/0 (unclad)1R25/1 (Clad)

1R25/0 (unclad)1R25/1 (Clad)

Resistance Thickness Construction



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Design Considerations Resistor width is the most critical dimension in determining yield

Wider resistor geometry yield tighter tolerances

At present, 10 mil resistor widths are the hard limit to yield +/- 15 %

tolerance

Signal traces should run no closer than 8 mils to the resistor element

Resistor elements should be placed no closer than 15 mils to the drilled

hole

Use 25 ohm/square material if design criteria allows

Minimum core thickness of 4 mils (thicker cores provide better yield)


PWB

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