Pulse Pulse GeneratorGenerator

High Speed Digital Systems LabHigh Speed Digital Systems LabWinter 2007/08Winter 2007/08

Project definitionProject definition

Instructor: Instructor: Yossi HipshYossi Hipsh

Students: Students: Lior Shkolnitsky, Lior Shkolnitsky, Yevgeniy LobanovYevgeniy Lobanov

2Pulse Generator

TopicsTopics

The main goalThe main goal I/O schemeI/O scheme Specifications definitionSpecifications definition Block diagram (preliminary) Block diagram (preliminary) Time table of the projectTime table of the project

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The main goalThe main goal To build a Programmable Pulse Generator.To build a Programmable Pulse Generator. The Generator will be integrated into an The Generator will be integrated into an

existing lab experiment, that teaches existing lab experiment, that teaches about High Speed Systems Phenomena: about High Speed Systems Phenomena: reflections, skew and jitter. reflections, skew and jitter.

The Generator will create a The Generator will create a deltadelta signal signal (very short pulse) and (very short pulse) and pulsepulse signal into signal into transmission line.transmission line.

This will allow a better way to observe This will allow a better way to observe reflections.reflections.

Pulse Generator

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I/O schemeI/O scheme

Programmable

Fast Pulse

Module

Power supply

Function selection

Short pulse (delta)

Long pulse (step)

Pulse Generator

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Specifications definitionSpecifications definitionOUTPUTSOUTPUTS Short pulse width: 0.5 to 1 nSecShort pulse width: 0.5 to 1 nSec Long pulse width: 10 to 13 nSecLong pulse width: 10 to 13 nSec Very fast rising/falling edge: ~130 pSecVery fast rising/falling edge: ~130 pSec Pulses repetition: 0.1-1 Pulses repetition: 0.1-1 µµSec (1-10 MHz)Sec (1-10 MHz) Stable period (low jitter): <10psec peak-to-peakStable period (low jitter): <10psec peak-to-peakINPUTSINPUTS Function selection:Function selection:

Control of the pulse width: 10pSec stepsControl of the pulse width: 10pSec steps 32 fixed pulse widths, changed by switch, to provide 32 fixed pulse widths, changed by switch, to provide

different results for different studentsdifferent results for different students Power supply: +2.5 to +5 VdcPower supply: +2.5 to +5 Vdc

Pulse Generator

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Block diagram Block diagram (preliminary)(preliminary)

An option: to use a two channel delay unit - NB6L296M.

Splitter

Buffer

Oscillator AND

Controller

Programmable

Delay

Power Supply

Programmable

Delay

Pulse Generator

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Time table of the projectTime table of the projectTask \ WeekTask \ Week 11 22 33 44 55 66 77 88 99 1010 1111 1212 1313 1414

Exploring the problem Exploring the problem 22-10                          

Definition presentation Definition presentation        22-11                  

Block diagram Block diagram consolidation consolidation                            

Finding suitable Finding suitable components components                            

Designing the board Designing the board                            

Design presentation Design presentation                19-12          

Ordering components Ordering components and board and board                            

Writing the booklet Writing the booklet                            

Designing a test setup Designing a test setup                            

Building the project Building the project                    15-01      

Building the test setup Building the test setup                            

Test and Debug Test and Debug                            

Final presentationFinal presentation                          30-01

Pulse Generator

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Questions / AnswersQuestions / Answers

Thank you!Thank you!

Pulse Generator

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BackupBackup

Pulse Generator

10High-speed experiment upgrade

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Delay Vcc Delay

Incr

emen

t

Rin(D

own)

Rin(U

p)

Rin

RoutVtt diff

eren

tial

T rise

/fall

fmax

# of P

ins

Size

Volt nsec psec KohmKohm Ohm Ohm Volt psec GHz mm x mmtermination

MC10EP195-D 3.3 2.2 -- 12.2 10 75 37.5 50 Vcc-2 yes 110 1.2 32(50 Mhz)

MC100EP196-D 3.3 2.4 -- 12.4 10 75 36.5 50 Vcc yes 120 1.2 32(50 Mhz)

NB6L295M-D 3.3 / 2.5 3.2 -- 9 11 37 50 50 Vcc yes 100 1.5 24 4x4(2 channels) 6.2 -- 17.8 (50 Mhz)AD9501 5 2.5 -- 10000 10Vol=0.5; Voh=2.5

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AND Vcc Rin(D

own)

Rin(U

p)

RoutVtt diff

eren

tial

T rise

/fall

fmax

Size

Volt Kohm Kohm Ohm Volt psec MHz pins

MC10E104-D 5 50 50 Vcc-2 no 425 700 28

MC10E404-D 5 50 50 Vcc-2 yes 150-400 900 28

MC10EL05-D 5 … 50 Vcc-2 yes 225 tbd 8

MC100LVEP05 3.3 75 37.5 50 Vcc-2 yes 130 3000 82.5

MC10EP05-D 3.3 75 37.5 50 Vcc-2 yes 130 3000 85

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Fan Out Buffer Vcc Rin(D

own)

Rin(U

p)

Rin

RoutVtt diff

eren

tial

T rise

/fall

fmax

Size Scew

Volt Kohm Kohm Ohm Ohm Volt psec GHz pins psectermination

MC10EP11-D 5 75 37.5 50 Vcc-2 yes 130 3 8 153.3

NB6L11-D 3.3 75 37.5 50 Vcc-2 yes 75 6 8 52.5

NB6L11M-D 3.3 50 50 Vcc yes 70 4 16 32.5

NBSG11-D 3.3 75 36.5 50 50 Vcc-2 yes 30 12 16 62.5

SY10/100EL11V 5 75 yes 225 8 5(MICREL) 3.3SY89311U 5 75 75 yes 120 3 8 5(MICREL) 3.3

2.5SY89835U 2.5 100 100 yes 75 2 8 5(MICREL)MC100ES6011 3.3 75 56 50 Vcc-2 yes 70-220 3 8(MOTOROLA) 2.5IDT 300---

AZ100EL11 5 75 50 Vcc-2 yes 100-350 8 5(ARIZONA MICROTEK)100EL11 5 50 Vcc-2 yes 225 tbd 8 5(FAIRCHILD)100LVEL11 3.3 50 Vcc-2 yes 120-320 1 8 5(FAIRCHILD)

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