Prospects for Nanoelectronics CMOS Scaling and Functional ...

S.Deleonibus SRC/SFI/NSF FISC-2030) Carton House, Maynooth, Ireland

Prospects for Nanoelectronics CMOS

Scaling and Functional Diversification

Simon Deleonibus

CEA-LETI, MINATEC Campus,

17 rue des Martyrs, Grenoble 38054, France

E-mail: [email protected]

SRC/SFI/NSF Forum on Integrated Sensors for Cybersy stems (FISC-2030)

© CEA. All rights reserved

| 2S.Deleonibus SRC/SFI/NSF FISC-2030) Carton House, Maynooth, Ireland

Outline

•Introduction

•Nanoelectronics scaling with thin films devices, new materialsand new devices architectures.

Exploitation of 3rd dimension. Low Power/ High Perfomance

•Heterogeneous Co-integrationof More Moore and More than Moore. 3D as a strong asset. New applications .New progress laws.

•Conclusion



Scaling: a success story…thanks to innovation Progress law for microelectronics

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Num

ber

oftr

ansi

stor

s pe

rch

ip

100µm

10µm

1µm

0,10µm

10 nm

Crit

ica

lDim

ensi

on

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

microp

roce

ssors

dynam

icmem

ories

(DRAM

)

contacts « plugs »(3 lev met)

vias « plugs »,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

Main Frame

C.T.V.

VCRDefense

Home PC

Portable Internet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Num

ber

oftr

ansi

stor

s pe

rch

ip

100µm

10µm

1µm

0,10µm

10 nm

Crit

ica

lDim

ensi

on

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

microp

roce

ssors

dynam

icmem

ories

(DRAM

)

contacts « plugs »(3 lev met)

vias « plugs »,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

Main Frame

C.T.V.

VCRDefense

Home PC

Portable Internet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

Moore’s law: 2Xdevices/year

Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS DevicesEditor: S.Deleonibus, Pan Stanford Publishing, Oct 2008



Thin Films Devices Relaxing optimization scaling rule by architecture

TSi= ¼ Lg

TSi= 1 to 2 Lg

Planar Double-gate

Planar or Finfet

Trigate/nanowire

tsource

Gate

tsource

Gate

Gate source

t

Gate

SourceL

w

ThinSOI

Bulk or thick SOI

TSi= ½ Lg

w

TSi=2.5nmStrain global & local

Lg=10nm

Barral et al. IEDM2007

Andrieu et al VLSI2006

Bernard et al. VLSI 2008

Dupré et al. IEDM 2008

Ernst et al. IEDM 2008

Jahan et al. VLSI2005

Vinet et al. EDL 2005

4.8 nm

3.4 nm

4.8 nm

3.4 nm



Stacked Multichannels and MultiNanowires« Top-Down » approach

LETI: Dupré et al. IEDM 2008, San Francisco(CA) Ernst et al., Invited talk IEDM 2008, San Francisco( CA) Bernard et al, VLSI Symposium 2008 Honolulu K.Tachi et al., IEDM 2010, San Francisco

LETI top down approach for Low Power and High performance

10-12

10-10

10-8

10-6

10-4

10-2

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Dra

in C

urre

nt I

D (

A/µ

m)

Gate Voltage VG (V)

VD=1.2VV

D=1.2V

NWFET

P N

VD=50mV

ION

=6.5mA/µm

IOFF

=27nA/µm

SS=68mV/decDIBL=15mV/VV

T=0.5V

C.E.T.=1.8nm

VD=50mV

ION

=3.3mA/µm

IOFF

=0.5nA/µm

SS=65mV/decDIBL=7mV/VV

T=-0.62V

-CV/I outperforms Planar in loaded environment-Gate separation possible -Transport properties in small nanowires-Flexibility to tune channel conductance wrt FinFET-Pervasion into microsystems (More than Moore)



0.5

1

1.5

2

2.5

3

10 20 30 40 50 60

AV

t (m

V.u

m)

Gate length L (nm)

FinFETs

Planar FDSOI

Wfin

=10nm

UTBSOILETI

square : Vd=50mV

circle : Vd=1V

Wfin

=20nm

Wfin

=15nmW

fin=20nm

[14]

[13]

[1]

[12]

[13]

[15]

[15]

[16]

0

20

40

60

80

100

120

-105 -8

7-6

9-5

1-3

3-1

5 0 15 33 51 69 87 105

σ∆Vt=34.5mV

σVt=24.5mV

AVt=0.95mV.µm

Cou

nt

Vt shift ∆Vt (mV)

0

20

40

60

80

100

120

-105 -8

7-6

9-5

1-3

3-1

5 0 15 33 51 69 87 105

σ∆Vt=34.5mV

σVt=24.5mV

AVt=0.95mV.µm

Cou

nt

Vt shift ∆Vt (mV)

Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs

L=25nmW=60nm

(σVt=σ∆Vt/√2 to compare measurements on pairs and on arrays of transistors in the literature)

LETI: LETI: LETI: LETI: O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008WL

AVtVt =σ

FDSOI Undoped channels vs.FinFETRecord-high VT matching performance



SOI TFETs co-integrated with CMOSFETs

F.Mayer et al., IEDM 2008, C.LeRoyer et al., ULIS 2009

SOI TFET w. LDDn

BOx

S D

GP mode N mode

LDDHDD

50nm

NiSi NiSi

NiSi

Source

HDD

Gate

tSi

TiNHfO2

Poly

LG

1st spacer

2nd spacer

NiSi

SiN protection layer

Drain

LDDHDD

50nm

NiSi NiSi

NiSi

Source

HDD

Gate

tSi

TiNHfO2

Poly

LG

1st spacer

2nd spacer

NiSi

SiN protection layer

Drain

Vth

VG

Log ID

IOFF

ideal switch

TFETMOSFET

Vth

VG

Log ID

IOFF

ideal switch

TFETMOSFET

L=100nm; T=300K

•P mode: VDS<0 & VGS<0 •N mode: VSD>0 & VGD>0

Experimental demonstrationof Tunnel FET operations:



Pervasion of Nanowire technology: towards heterogenerous integration

20nm

Poly SiSiO2Si3N4SiO2

3D NAND Flash

Q=870 resonatorGauge width = 80 nm

15 nm oscillator

Zeptogram mass resolution

Mass detection

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Con

duct

ance

(nS

)

pH 7

pH 4pH 5

pH 6

pH 3

pH 2

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Con

duct

ance

(nS

)

pH 7

pH 4pH 5

pH 6

pH 3

pH 2

Metaln-doped Si Hole ElectronPassivation

Buffer solutionat pH<7

Buffer solutionat 7<pH<10

Buffer solutionat pH>10

Metaln-doped Si Hole ElectronPassivation

Buffer solutionat pH<7

Buffer solutionat 7<pH<10

Buffer solutionat pH>10

T.Ernst et al., IEDM 2008 Hubert et al., IEDM 2009

Chemical sensing



CoCo--Integrating Heterogeneous materials and devicesIntegrating Heterogeneous materials and devices3D sequential process: one step ahead to3D sequential process: one step ahead to

(100)

First First heterogeneousheterogeneous orientation in 3D Si orientation in 3D Si sequentialsequential integrationintegrationEnabledEnabled by use of wafer by use of wafer bondingbonding by by keepingkeeping lowlow thermal budgetthermal budget

(110)

0.0 0.2 0.4 0.6 0.8 1.00

50

100pMOS

Reference TiN/ HfO2/ Si (100)

TiN/HfO2/Si(110) <100>

µe

ff,

ho

le (

cm

2/

V.s

)

Eeff (MV/cm)

P.Batude et al., Best student Paper Award, IEDM 2009

Ge

- cold end process(bonding) Improved IgOpportunities for other SC(Ge,III-V, C, ...) - improved layout (40% area SRAM cell) - 4T SRAM -dynamically controlled VT:

improved RNM and SNM P.Batude et al, 2011 VLSI Tech Symp

Tsi 10 nm

Tsi ~10 nm

LG~50 nm

THFO2

2.5 nmTiN

LG~50 nm

Tsi 10 nm

Tsi ~10 nm

LG~50 nm

THFO2

2.5 nmTiN

LG~50 nm



~ 1 node gain with same design rules for Front end levels

topGeOI pMOS

2µm

nMOSGate

nMOSSource

pMOSGate

pMOSSource

bottomSOI nMOS

topGeOI pMOS

2µm

nMOSGate

nMOSSource

pMOSGate

pMOSSource

bottomSOI nMOS

Y-H. Son et al, VLSI 07, Jung et al, IEDM 2006

� Nanoelectronics & Photonicsapplications withSi-Ge Co-integration

�SRAM on top SOI logic, I/Os, analogon bottom bulk

�…

� SRAMs � FLASH

Sequential 3D: Potential and Demonstrated Applicati onsSequential 3D: Potential and Demonstrated Applicati ons

High density logic applicationsHigh density logic applications Highly miniaturized Highly miniaturized CMOS imagers pixelsCMOS imagers pixels

Heterogeneous integrationHeterogeneous integration 3D memories3D memories

P. Coudrain et al, IEDM 08,

P. Batude et al,VLSI09

P.Batude et al., IEDM 2009, Best Student Paper Award



Logic + Stacked NVM: High bandwith, Reduced Power consumption,…Reconfigurable, Neuromimetic

ex: 32 nm node : > 1TB/s per 1mm2

Resistive switchesToshiba, Stanford Univ.: K.Abeet al, ICICDT 2008;

Suri et al. IEDM 2011

3D-Xbar Memory stacked on Logic: towards NV Logic

proven in 2D withMagnetic Tunnel Junctions, FeRAM Tohoku Univ., Hitachi: S.Matsunaga et al., Appl.Phys.Express(2008);

ROHM



Advanced Devices and Systems Future Vision based on FDSOI

More Moore

More thanMoore

Dual channel

xsSOI(N)/ Ge(P)

UTBOX

22nm 16nm

sSOI

FDSOI

11nm

Std SOI

HP options

Nanowire

3D Nanowires

3D stacked devices3D

Logic

3D

III-V/Ge Heat sink C

Memory storing (SRAM, NVM) -

ZDRAM

3D stacked Mixed functions: NV Logic +sensors/polymers

X bar

3D Sensing/Actuation Bio, Mechanical & Chemical –(functionalization, NEMS, Single electronics, RF, opto,… )

Diversified Logic(association to Memory, Passives, Sensors,…)

Beyond CMOS (e-wavesconfinement, Spin electronics)

Si

FeFe

Si

FeFe

Low stress, HiD

Car

bon

elec

tron

ics(

CN

T,G

raph

ene,

Dia

mon

d)

Technology node

< 11nm

TFET

MetallizedDNA interco

More Moore

More thanMoore

Dual channel

xsSOI(N)/ Ge(P)

UTBOX

22nm 16nm

sSOI

FDSOI

11nm

Std SOI

HP options

Nanowire

3D Nanowires

3D stacked devices3D

Logic

3D3D

III-V/Ge Heat sink C

Memory storing (SRAM, NVM) -

ZDRAM

3D stacked Mixed functions: NV Logic +sensors/polymers

X bar

3D Sensing/Actuation Bio, Mechanical & Chemical –(functionalization, NEMS, Single electronics, RF, opto,… )

Diversified Logic(association to Memory, Passives, Sensors,…)

Beyond CMOS (e-wavesconfinement, Spin electronics)

Si

FeFe

Si

FeFe

Low stress, HiD

Car

bon

elec

tron

ics(

CN

T,G

raph

ene,

Dia

mon

d)

Technology node

< 11nm

TFET

MetallizedDNA interco



Heterogenous Integration On Silicon

80 µm diameter TSV imagers packaging

1 µm diameter High AR TSV stacked ICs

12µm1µm

Si

Si

12µm1µm

Si

Si

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Copper/Copper bonding

Oxide/Oxide bonding

Wafer level packaged MEMS

Packaging is taken into accountat the 3D wafer level

System On Wafer: Heterogeneous co-Integrated System s (Parallel 3D)

Embedded passives (Passives, filters, spin

torque osc,…)

Stacked Memories + Logic, Sensors,,…

Optical Interconnects

Energy source converter

MEMS

Stacked ICs

Coolingoption



Heterogenous Integration On Silicon

80 µm diameter TSV imagers packaging

1 µm diameter High AR TSV stacked ICs

12µm1µm

Si

Si

12µm1µm

Si

Si

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Copper/Copper bonding

Oxide/Oxide bonding

Wafer level packaged MEMS

Packaging is taken into accountat the 3D wafer level

System On Wafer: Heterogeneous co-Integrated System s (Parallel 3D)

Embedded passives (Passives, filters, spin

torque osc,…)

Stacked Memories + Logic, Sensors,,…

Optical Interconnects

Energy source converter

MEMS

Stacked ICs

Coolingoption

Commercial products- image on board VGA camera, - mixed nodes & modes, - high density TSV

Cross talks:-delay, matching,

-power dissipation(global temp. increase, hot spots, reliability, …)

Multiphysics

New Progress Laws- application specific

Via belt technology

MEMS + IC stack

Ultra flat 3D

Chip stacking(TSV)

Active Silicon interposer



Image-on-BoardActive Silicon interposer

Die to Die Copper pillars

Die to substrate

copper pillars

Thinned wafer (~100 µm)

Diam 60µmThick 120 µm

Via Last TSV (Aspect Ratio 2-3)

3D Integration: from imagers to advanced 3D ICs

Memory, Processors, Memory, Processors, Memory, Processors, Memory, Processors, ImagersImagersImagersImagers

withwithwithwith highhighhighhigh densitydensitydensitydensity TSV, NEMSTSV, NEMSTSV, NEMSTSV, NEMS…………

3D-IC

Metal1

ØTSV~3µm Thin Si~15µm

ØTSV~3µm Thin Si~15µm

3D highdensity

withTSV

2001

2008

VGA cameras (300kpixels)

withTSV

2001

2008

2001

2008

VGA cameras (300kpixels)

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Mixed Signal Digital/Analog



« More, More than, Beyond Moore »Tomorrow’s top added value markets

ITRS 2009

High growth with ‘More than Moore’ technologies:they require expertise in all technical domains and in-

depth knowledge of the targeted markets



NEMS scaling laws: is it worth?

k3 [rough estimate]energy consumption

k-4mass responsivity

k-1resonant frequency

kstiffness

k3mass

Scaling ruleParameter

twlM eff ⋅⋅∝

3

3

l

tweff ⋅∝κ

20 l

t

Mf

eff

eff ∝∝κ

effeff M

f

M

f

200 −=

∂∂=ℜ

2

21

MaxeffP xE ⋅≈ κ

txMax ∝and

- potentially many applications : sensors, actuators(switches /RF, memory,…) - resolution increases- areal cross section decreases (SBR,SNR) => arrays, actuation,…- figures of merit pressure and vacuum quality dependent

( )20/10 DReff

Q

Mm −⋅=δ

SNRP

SDR

act

noise 1=∝ ∑

ML Roukes et. al. APL (2005)



Nanowires & Arrays used for mass detection

- First 200 mm wafers with 3.5 millions NEMS - Association Nanowire/Resonator ; Cantilever arrays CMOS compatible

Capacitive actuation & detection Capacitive actuation & piezo-resistive detection with nanowires

Thermo-elastic actuation & piezo-resistive detection.

15 nm oscillator

Hzzgm /5.0≈δ

Q=870 resonatorGauge width = 80 nm

LETI: T.Ernst et al., IEDM 2008, Invited talkL. Duraffourg et. al, APL 92, 174106 (2008)

E Mille et al, Nanotechnology, 165504, (2010) J.Arcamone et al. , IEDM 2011

NEMS array



A possible solution: coupling GC and NEMS

• Gas Chromatography (GC) is a well-known separation methodIt provides selectivity by separating in time and space the gas

mixture components

• NEMS detectors sequentially detect the elution peaks at the

GC output

• Both GC column and NEMS detectors can be fabricated

with VLSI silicon micro / nanofabrication techniques

Injection of the

gas mixtureCarrier gas flow

GC column

NEMS chip

J.Arcamone et al. , IEDM 2011



Bubblers

NEMS (Test chamber)

Automated gas lines

Dilution flowN2

Analyte flowgenerated by bubblers

Specific constraints related to gas sensing: NEMS functionalization• deposition of sensitive layers (they have to absorb everything)

• targeted gases: alkanes (for instance, octane) and volatile organic

compounds (toluene, xylene, etc…)

• every coating layer is characterized (at equilibrium) in a gas test bench

Resonators exposed to sequences of

[carrier gas / carrier gas + analyte]

→ determination of K coefficients




Gas recognition: multigasanalysis

Partnership:


spin off fromLETI and Caltech



Front-end co -integration of ultra-scaled Si NEMS with FDSOI CMOS

Integration of first amplification stage enables dire ct measurement of small electrical signalsprovided by the NEMS resonators (40nmx40nm cross sect ion)

Alu

W

BOX

BE oxides

SiSuspended NEMS area

Actuation electrode

1.2µm

NEMS part

CMOS part

LETI: E.Ollier, C.Dupré, IEEE MEMS 2012

EU NEMSIC project



0100110…0000110…

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

E-Cell

Signal amplification and multiplexing

A multi-physics system vision



M&NEMS co integrated devices platform for 3D sensing

i

P.Robert et al, 2009 IEEE SensorsD.Ettelt et al, 2011 Transducers

3-axis accelerometer∆∆∆∆R/R<5x10-4 ( ±1g) Linearity <0.3% ( 0 and 200MPa)S<1mm2 (3 axis)

3-axis gyroscopeF0 ≈ 20.3 kHzQ > 100.000 S=0.8mm² / axis

3D magnetometer Resol 20-80 nT/ √Hz Lin 4.5 mTS=0.25 mm²/axis

microphone

pressure sensor

NanobeamsArea ÷4 vs SoA



Closer to « human processing »…

rf CMOS+ passives

bioMEMS

touchsensors

MEMSmicrophones

imagers

on-boardpower

integratedmemory

“Devices that can see…

“Devices that can remember…

“Devices that can speak with others…

“Devices that can keep goingwhen the rest have stopped…

“Devices that can feel…

“Devices that can sensetheir environment…

“Devices that can hear…

gassensors

“Devices that can smell…

•Sense in various domains•Communicate

•Fusion•Interpret

�� ImproveImprove qualityquality of lifeof life

Nowadays : independentreplications of senses in

different domains

objective

…and more/”augmented”... with ethics!



Fusion:•Électronics•Algorithms•Memories

Communications

Pre treatment

Sensors

Restitution:•Mechanical

•Acoustic

•Electromagnetic

•Optical

•Digital

Chemistry, biotechnologies•Gas•Lab on chip

Physical•Pressure•Movements•Temperature

Field•photons•waves

Mechanical ,Logic•Switch

•nanowires

Multi Sensorial Extended System /Fusion,Intelligent communication

Applications: assistance , security (home, industrial, medical), surveillance, diagnostic, medical care, environment ,food, agriculture

To be published



ZeroZero power and science drivepower and science driveo Zero-power is the system ability to harvest energy

existing in dynamic environments (solar, thermal, vibrations,

electromagnetic) and power-up the smart GA systems.

o Science drive: energy efficiency limits and disruptive harvesters.

100aJ/op

0.1aJ/op

1-1

0n

J/b

it

1pJ/bit

10-1

00µµµµW

100nW100µµµµW/cm 2

10

mW

/cm2



Conclusion : Nano–« electronics and systems »from Devices to Systems Perspectives

� Innovation from strong association of

System/Device/Materials Science and Engineering

� Si CMOS: Nanoelectronics Base platform beyond ITRS

� Low Power consumption: major challenge to Zero Power.

Device/ system architecture optimization(GAA nanowires, low slopes,design, 3D)

Opportunities for new materials(revised low BG III-V, Carbon based ,…)

� Heterogeneous 3D co-Integration on Si, Low Power:

Co integration : Add Functionalities for diversification, Sensors, actuators, NonCMOS & CMOS, Monolithic, 3rd dimension in device, Stacked mixed functions, System On Wafer

� System Design towards Fusion: New Design Models, Multiphysics, Intelligent communication , Health, environment, quality of life, IST,food/agriculture, industrial control,…



Thank you for your attention

Merci de votre attention



Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS Devicesedited by edited by edited by edited by Simon Deleonibus ((((CEACEACEACEA----LETI, FranceLETI, FranceLETI, FranceLETI, France) ) ) ) ClothClothClothCloth July 2008July 2008July 2008July 2008 978978978978----981981981981----4241424142414241----28282828----1111

�� Discusses the scaling limits of CMOS, the leverage brought by nDiscusses the scaling limits of CMOS, the leverage brought by nDiscusses the scaling limits of CMOS, the leverage brought by nDiscusses the scaling limits of CMOS, the leverage brought by new ew ew ew materials, processes and device architectures (materials, processes and device architectures (materials, processes and device architectures (materials, processes and device architectures (HiKHiKHiKHiK and metal gate, SOI, and metal gate, SOI, and metal gate, SOI, and metal gate, SOI, GeOIGeOIGeOIGeOI, , , , MultigateMultigateMultigateMultigate transistors, and others), the fundamental physical limits of transistors, and others), the fundamental physical limits of transistors, and others), the fundamental physical limits of transistors, and others), the fundamental physical limits of switching based on electronic devices and new applications basedswitching based on electronic devices and new applications basedswitching based on electronic devices and new applications basedswitching based on electronic devices and new applications based on few on few on few on few electrons operationelectrons operationelectrons operationelectrons operation

�� Weighs the limits of copper interconnects against the challengesWeighs the limits of copper interconnects against the challengesWeighs the limits of copper interconnects against the challengesWeighs the limits of copper interconnects against the challenges of of of of implementation of optical interconnectsimplementation of optical interconnectsimplementation of optical interconnectsimplementation of optical interconnects

�� Reviews different memory architecture opportunities through the Reviews different memory architecture opportunities through the Reviews different memory architecture opportunities through the Reviews different memory architecture opportunities through the strong strong strong strong lowlowlowlow----power requirement of mobile nomadic systems, due to the increasipower requirement of mobile nomadic systems, due to the increasipower requirement of mobile nomadic systems, due to the increasipower requirement of mobile nomadic systems, due to the increasing ng ng ng role of these devices in future circuitsrole of these devices in future circuitsrole of these devices in future circuitsrole of these devices in future circuits

�� Discusses new paths added to CMOS architectures based on singleDiscusses new paths added to CMOS architectures based on singleDiscusses new paths added to CMOS architectures based on singleDiscusses new paths added to CMOS architectures based on single----electron transistors, molecular devices, carbon electron transistors, molecular devices, carbon electron transistors, molecular devices, carbon electron transistors, molecular devices, carbon nanotubesnanotubesnanotubesnanotubes, and spin , and spin , and spin , and spin electronic electronic electronic electronic FETsFETsFETsFETs

Available at Amazon.com or any good bookstores.



Hot Topics: parasitic effects in MOSFET technology� Introduction of HiK and metal gate allows continued scaling and relaxes SiO2

gate leakage current related issues - Ig added to SCE, DIBL,

subthreshold leakage(LETI IEDM 2002, Intel IEDM 2005)

� Statistical dopant variability

- number of dopants in the active area decreases with scaling

- random distribution of channel dopants

Poisson’s law. Standard deviation:

Major interest for LowDoped channels

21

=Volume

Ndopingσ

0.01

0.1

1

10

100

1000

104

0.01 0.1 1

σσ σσ N/N

Nom

bre

d'im

pure

tés

Lg (µm)

Statistical fluctuations of threshold voltage: 150 mV decayfor VT=200mV( Lg=25nm) !!



Low Power FDSOIThin Films Undoped channels

LETI, ST Micro: C.Fenouillet Beranger et al., IEDM 2007, VLSI Symp 2010 V.Barral et al., IEDM2007

VDD=1V Ioff=6pA/µm

0.248µm2 SNM (1.2V)=140mV 0.179µm2 SNM (1.2V)=230mV

6T SRAM

10 nm BOx8 nm TSi 10 nm BOx8 nm TSi

Range = ±4 Å!

0000

+5+5+5+5

----5555

1 9 17

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SO

I Thi

ckne

ssD

evia

tion

to ta

rget

(Å

)SOI Thickness

Max

Mean

Min

XUT+/- 5 Å - SOI thickness deviation

1 9 17

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SO

I Thi

ckne

ssD

evia

tion

to ta

rget

(Å

)SOI Thickness

Max

Mean

Min

XUT+/- 5 Å - SOI thickness deviation

300mm wafers

Lg=32nm



Merits of FDSOI

Reachable Scaling rules(TSi, TBOx)

Delay vs. Power x Delay22% improvement/bulk (20nm)

O.Faynot et al, IEDM 2010, invited talk

L.Clavelier et al, IEDM 2010, invited talk



Expected impact

35

Society and life� as personal companions, GA’s will preserve human health and improve the quality of life for all

categories of ages, in an affordable way

� GA’s will make our environment more interconnected and smart, more energy efficient and safe

� Disruptive technology focused on prevention based on augmented information for personal level decision

Leadership in science and technology� leading role of Europe in zero-power novel technologies

� enabling a stronger role of manufacturing in Europe

� improving the competitiveness for leading communication and medical companies

Employment� creation of new employment in Europe in ICT domain

� new business opportunities



Towards a zero-power technology platform

Bio-inspired energy scavenging: artificial photosynthesis

• Environmentally

friendly materials

• High efficiency in-

door & out-door

• Low cost processing



TFET for Ultra Low Power outperforms CMOS Offset/drain reduces Ioff(ambipolar current)

LETI: Mayer et al, IEDM 2008 Intel: U.E. Avci et al, VLSI Tech Symp 2011

EPFL: K. Boucart & A. M. Ionescu, ESSDERC 2006TUM: M. Schlosser et al. IEEE TED, Jan. 2009

Multigate improves Ion

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