Propagation Delay - University of Waterloomhanis/ece637/lecture7.pdf · CMOS Inverter Propagation...

Propagation DelayPropagation Delay

CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response

tpHL = f(Ron.CL)

= 0.69 RonCL

VoutVout

R n

Rp

VDDV DD

V in = VDDV in = 0

(a) Low-to-high (b) High-to-low

CLCL

Computing the CapacitancesComputing the CapacitancesM1 and M2 are either in cut-off or in saturation mode during the first half (up to 50%) of the output transient.

Thus, the only contribution to Cgd12are the overlap capacitances of both M1 and M2.

The channel capacitance is either completely located between gate and bulk (cut-off) or gate and source (saturation).

The lumped model requires the gate-drain capacitance to be replaced by a capacitor to ground. So we take the Miller effect.

VDD VDD

V in Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout 2

Fanout

Interconnect

VoutVin

CL

Simplified (lumped)Model

Diffusion capacitances Cdb1 and Cdb2 are due to the reverse-biased pn-junction (same as we did for diode & MOS case – Ceq=KeqCj0)

])()[()1)((

10

10

0 mlow

mhigh

lowhigh

m

eq VVmVV

K −− −Φ−−Φ−−

Φ−=

Miller EffectMiller Effect

Vin

M1

Cgd1Vout

∆V

∆V

Vin

M1

Vout ∆V

∆V

2Cgd1

“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”

WCC GDgd 02= CGD0 is the overlap capacitance per unit width

Gate Capacitance (CGate Capacitance (Cg4 g4 , C, Cg3g3))VDD VDD

V in Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout 2

Fanout

Interconnect

VoutVin

CL

Simplified (lumped)Model

)()( PMOSCNMOSCC gategateoutfan +=−

)()( 0000 oxpppGDpGSoxnnnGDnGSoutfan CLWCCCLWCCC +++++=−

Assumptions

(1) Ignores Miller effect on the gate-drain capacitance. This is acceptable since the connecting gate would not switch before the 50% point is reached, and Vout2 remains constant in the interval of interest.

(2) The channel capacitance of the connecting gate is constant over the interval of interest. In reality it varies from 2/3CoxWL in saturation to WLCox in linear and cutoff.

Propagation Delay: First Order AnalysisPropagation Delay: First Order Analysis

Integrate the capacitor (dis)charge current.

This is very difficult to solve since both CL(v) and i(v) are nonlinear functions of v.

We fall back to the simplified switch model of the inverter. The voltage dependencies of the “on” resistance and the load capacitance are addressed replacing both by a constant linear element with a value averaged over the interval of interest.

dvvivC

tv

v

Lp ∫=

2

1)()(

)97

1(43

)1(2/1

2/DD

DSAT

DDV

V DSATDDeq V

IV

dVVI

VV

RDD

DD

λλ

−≈+

= ∫

−−=

2)('

2DSAT

DSATTDDDSAT

VVVV

LW

kI

© Digital Integrated Circuits2nd Inverter

CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayVDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

Ron=Req

LeqppLH CRt 69.0=

+=

+=

269.0

2eqpeqn

LpLHpHL

p

RRC

ttt


0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vou

t(V)

Transient ResponseTransient Response

tp = 0.69 CL (Reqn+Reqp)/2

tpLHtpHL

Vin

Hand calculatedtpHL=0.69x(13Kohm/1.5)x6.1fF=36psectpLH=0.69x(31kohm/4.5)x6.1fF=29psecThus, tp=32.5psec

SpicetpHL=39.9psectpLH=31.7psec


The previous example might give the impression that manual analysis always leads to close approximations of the actual response. This is not necessarily the case. Large deviations canoften be observed between first and higher order models. The purpose of the manual analysis is to get a basic insight into the behavior of the circuit and to determine the dominant parameters. A detailed simulation is indispensable!


Delay as a function of VDelay as a function of VDD DD (ignoring (ignoring channelchannel--length modulation)length modulation)

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(no

rmal

ized

)

For high VDD values (VDD>VTn+VDSATn/2), the delay is virtually independent of VDD.

It comes as no surprise that Req has the same behavior with VDD.

When VDD<VTn+VDSATn/2 ~ 2VTn, a sharp increase in delay is seen. This operation region should be avoided if achieving high performance is a primary goal.


Design for PerformanceDesign for Performance

q Keep capacitances small (diffusion capacitances, gate capacitances, wiring capacitance, and fanout)

q Increase transistor sizes§ watch out for self-loading! Once the intrinsic capacitance

(diffusion capacitance starts to dominate the extrinsic load formed by wiring and fanout, increasing the gate size no longer helps reduce delay. It only makes the gate larger in area.

q Increase VDD (????) – trading off performance for power. Increasing VDD above a certain values yields minimal improvement to delay. Reliability issues – oxide breakdown, hot carrier effects.


NMOS/PMOS ratioNMOS/PMOS ratio

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

β

t p(sec

)

tpLH tpHL

tp

β = Wp/Wn

Making PMOS width ~ 3 times larger than NMOS width is to create an inverter with symmetrical VTC and equal tpHL, tpLH. However, this doesn’t yield minimum delay.

Widening PMOS improves tpLH by increasing the charging current, but degrades tpHL by causing larger parasitic capacitance. Thus, a transistor ratio must exist to optimize the delay of the inverter.

WgngpdndpL CCCCCC ++++= )()( 2211

When PMOS is β times larger than NMOS, all device capacitances scale approximately in same way; Cpd1~ β Cdn1 and Cgp2~ β Cgn2.

WdngnL CCCC +++= ))(1( 11β

)]())(1[(269.0

21 ββ eqp

eqnWgndnp

RRCCCt ++++=

)1(]))(1[(345.0 21 ββ

rRCCCt eqnWgndnp ++++=

eqn

eqp

R

Rr = )1(

21 gndn

Wopt CC

Cr

++=β ropt =β When wiring is negligible

Smaller devices yield faster designs at expense of symmetry and noise margin


Device SizingDevice Sizing

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(sec

)

(for fixed load)

Self-loading effect:Intrinsic capacitancesdominate

)(69.0 int exteqp CCRt +=

The PMOS and NMOS are sized to achieve equal rise and fall delays.

)/1()/(69.0 int0intint CCtCCCRt extpexteqp +=+=

By sizing up the inverter by S (a sizing factor to relate to a minimum sized inverter) – Cint = SCiref and Req=Rref/S. Cint consists of the diffusion + miller capacitances.

)/1()1(69.0)/)()(/(69.0 0 irefextpiref

extirefrefextirefrefp SCCt

SCC

CRSCCSCSRtiref

+=+=+=

(1) Intrinsic inverter delay tp0 is independent of the gate sizing, and is determined by the technology + layout. (2) Making S large yields high performance gain, eliminating the impact of external loads, and reducing delay of the intrinsic one – but also yield large silicon area!

Cext/Cint~1.05 (Cint=3fF, Cext=3.15fF). This leads to a max performance gain of 2.05. With S=10 it allows us to get within 10% optimal performance, while larger device sizes only yield ignorable performance gains. By simulating, max obtainable performance improvement = 1.9 (tp0=19.3psec)


Impact of Rise Time on DelayImpact of Rise Time on Delayt p

HL(n

sec)

0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20

All previous assumptions are rise and fall times = 0. Only one device was assumed to be (dis)charging. In realiy, the input signal changes gradually, and temporarily PMOS and NMOS devices conduct simultaneously. This affects the current available for (dis)charging and hence delay.

If a latter gate is indefinitely strong, its output slope is zero, and the performance of the gate under examination is unaffected.

The main point here is that a gate is never designed in isolation, and that its performance is affected by both the fanout and driving strength of the gate(s) feeding into its inputs.

Note: It is advantageous to keep the signal rise times smaller than or equal the gate propagation delays. Aside from enhancing performance, it saves on power consumption. Keeping the rise and fall times of signals small and approximately equal is one of the major challenges in high-performance design ; slope engineering

Propagation Delay - University of Waterloomhanis/ece637/lecture7.pdf · CMOS Inverter Propagation...

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