project async

8/7/2019 project async

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Test generation for asynchronous sequential digitalcircuits

Roland Dobai

Institute of InformaticsSlovak Academy of Sciences

Dbravsk cesta 9, 845 07 Bratislava, [email protected]

AbstractThe dissertation thesis is aimed at test generation forasynchronous sequential digital circuits, contributes totheir time- and cost-effective testing, and indirectly sup-

ports their wider application, which improves the perfor-mance, the power consumption and the electromagneticemission of future digital circuits. The main scientific con-tribution is design of the new test generator (optimizedfor test length and area overhead) for wide spectrum ofasynchronous sequential digital circuits. The contribu-tions are identification of unacceptable signal transitionsbefore test generation, reduced number of generated testpatterns for combinational representation, effective statejustification on the gate level, fast (optimized for testlength) sequential fault propagation to outputs and ef-fective fault simulation. Experimental results confirmedthe generation of optimal tests with good fault cover-age and without application of any method for increasingthe testability. The developed methods can be used withwider spectrum of circuits than other recently developedtest generators, and at the same time their effectivenessensures fast test generation.

Categories and Subject DescriptorsB.7.3 [Reliability and Testing]: Test generation

Keywordstest pattern generation, asynchronous circuit, stuck-at-zero fault, stuck-at-one fault, state justification, sequen-tial fault propagation, fault simulation

1. IntroductionTodays digital circuits are mainly synchronous becausethey are well supported in commercial computer-aided

Recommended by thesis supervisor: Prof. Elena Gram-atovaDefended at . . . in Bratislavaon . . . .

c Copyright 2010. All rights reserved. Permission to make digitalor hard copies of part or all of this work for personal or classroom useis granted without fee provided that copies are not made or distributedfor profit or commercial advantage and that copies show this notice onthe first page or initial screen of a display along with the full citation.Copyrights for components of this work owned by others than ACM

must be honored. Abstracting with credit is permitted. To copy other-wise, to republish, to post on servers, to redistribute to lists, or to useany component of this work in other works requires prior specific per-mission and/or a fee. Permissions may be requested from STU Press,Vazovova 5, 811 07 Bratislava, Slovakia.

design tools. However requirements against digital cir-cuits are growing rapidly which causes many difficulties,e. g. high power consumption and electromagnetic inter-ference. Asynchronous sequential digital circuits (ASDCs)are able to overcome the limitations of synchronous cir-cuits but the problem of testing emerges when it comes totheir practical use. The methods for testing synchronouscircuits is a well explored area, but the testing of ASDCsstill faces many challenges [1, 31].

ASDCs perform self-synchronization and hence an exter-nal clock signal is not required. Another major differ-ence is in use of other memory elements, first of all C-elements [19]. C-element holds the output value whiledifferent logic values are on inputs, or sets it to the equalinput value.

These fundamental differences may result in oscillations(signal values on feedbacks never stabilize), races (signal

values on feedbacks change simultaneously) or hazards.Hazards are unwanted temporary signal value changes;and require attention during design and test also. Basi-cally, they are results of varying delays along the pathsin circuit. The temporary change of the assumed sta-ble value is called static hazard. The dynamic hazard isdefined as an unwanted multiple signal transition replac-ing the single one. Hazards can arise also in synchronouscircuits but they disappear before the clock period ends,therefore they do not cause any problem [14].

Test pattern generation (TPG) is the process of generat-ing test patterns to test the circuit, usually performed byan automatic test pattern generator (ATPG). The test

patterns are generated to detect a desired set of faults.ATPGs for synchronous circuits target various fault mod-els, e. g. stuck-at faults (SAFs), stuck-open faults, bridg-ing faults, delay faults. ATPGs for ASDCs were publishedmainly for SAFs [27, 10]. Delay faults of ASDCs [28, 12]are delay constraint failures and should not be confusedwith delay faults of synchronous circuits.

The TPG process is more simple if design-for-testability(DfT) methods [32] were previously applied to the sequen-tial circuit. These methods are intended to ensure fasterfault activation and test response evaluation by increasingcontrollabilities and observabilities with additional circuitelements; therefore a negative side effect is the significant

area overhead. Time-frame expansion methods [3] areused when DfT methods are not acceptable (e. g. theASDC could become nonfunctional due to timing con-straint violation). The area overhead is eliminated in this


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2 Dobai, R.: Test generation for asynchronous sequential digital circuits

case, but the test is longer because the fault is activatedand propagated to an observable point by a sequence oftest patterns.

Test patterns generated by an ATPG are evaluated byfault simulation with the goal to determine the fault cov-erage (ratio of detected and undetected faults). The faultsimulation of combinational and synchronous sequentialcircuits is a well explored area. The basic methods arethe serial, the parallel, the deductive and the concurrentmethods. The serial method is based on evaluating thecircuits response individually for every fault. The paral-lel method simulates simultaneously more than one fault.Deductive and concurrent methods are propagating thelists of detectable faults in the circuit. Every fault is con-sidered with only one simulation overpass, hence deduc-tive and concurrent methods are the fastest among thesefault simulation methods [21].

The aim of the dissertation thesis was to improve theTPG for ASDCs and to contribute to the time- and cost-

effective testing of ASDCs. The developed methods sup-port indirectly the wider application of ASDCs, which im-proves the performance, the power consumption and theelectromagnetic emission of future digital circuits. Themain scientific contribution is development of the newmethod for TPG (optimized for test length and area over-head) for wide spectrum of ASDCs. The contributionsare identification of unacceptable signal transitions be-fore TPG, reduced number of generated test patterns forthe combinational representation (CR) of ASDC, effec-tive state justification on the gate level, fast (optimizedfor test length) sequential fault propagation to outputsand effective fault simulation.

The rest of the paper is organized as follows. Section 2contains closely related research results to TPG and faultsimulation of ASDCs. Goals of the dissertation thesisare outlined in Section 3. Section 4 is dedicated to thenew TPG method. The new fault simulation method isdescribed in Section 5. Section 6 analyzes the achievedresults and Section 7 concludes the paper.

2. Related workMany multi-valued logics have been developed and pub-lished for hazard detection starting with 3-valued till even27-valued ones [2]. These logics are intended to representevery possible kind of hazards besides the stable logic val-

ues and transitions. Algorithms were also developed todetermine if a combinational circuit is hazard-free evenwithout examining every gate, therefore providing effi-cient hazard detection [15, 17]. These multi-valued logicsand hazard detection algorithms are able to determine ifthe existence of hazards is possible under the given cir-cumstances, but are unable to determine all possible haz-ardous conditions. Usually they provide many informa-tion about hazards but were developed for combinationalcircuits only, hence they do not consider ASDCs.

TPG for combinational circuits is a well explored area.Usually 5-valued logic {0, 1, X, D, D} is used for consid-ering SAF in the circuit (where 0 is logic false; 1 is logictrue; X is undefined/do-not-care value; D is logic true infault-free and logic false in faulty circuit; and D is logicfalse in fault-free and logic true in faulty circuit). Consid-erable advance in TPG performance was achieved in thelast decades starting with D algorithm [23], PODEM [13],

FAN [11] and followed by others [3]. These algorithms arebased on search for a test pattern which ensures the de-tection of the desired fault (the output of the circuit willbe different in the faulty and the fault-free state). Thefaulty signal D/D is assigned to the fault site and the faulteffect is propagated to primary outputs (POs). The prop-agation is based on creation of sensitive paths along whichthe faulty signal can be propagated. The sensitive pathis created by assigning logic values to the gates along thepath and by propagating the D-frontier. The D-frontieris the set of logic gates with a faulty signal on an inputand an undefined value on the output. Initial objectscontaining the required value assignment are created andpropagated in the circuit by a process called backtrace.The final objects after this propagation are used to assigna value to some place in the circuit. The value assignmentcannot be determined always uniquely and can cause con-flict of logic values. This conflict is called inconsistencyand is tried to be resolved by backtracks. The backtrack isthe process of assigning the opposite value at some placein the circuit where previously a decision of value assign-

ment was made. A process called implication is used afterevery value assignment for determination of every othervalue uniquely implied by this assignment. If every sen-sitive path from the fault site to POs goes through thesame logic gate then it is preferable to assign immedi-ately the values supporting the fault propagation at thatlogic gate. This process is called the unique sensitizationand is intended to speed up TPG.

Usually the ASDCs are represented in a form acceptableas input to TPG algorithms for combinational circuits.This form is called CR of ASDC and is intended to rep-resent the ASDC in the environment of combinationalATPGs. The CR is constructed in two steps: (1) Every

memory element is replaced by a set of simple gates. Thisset represents the function of the memory element withoutaltering the function of the ASDC (the set and the originalmemory element have the same delay and the structureof the set does not create new hazards). (2) The feed-backs are cut into pairs of pseudo-primary inputs (PPIs)and pseudo-primary outputs (PPOs) denoted as (P P I0,P P O0), (P P I1, P P O1), . . . , (P P In1, P P On1), wheren is the number of feedbacks. These PPIs and PPOsare recognized by the combinational ATPG just like theregular primary inputs (PIs) and POs, and are speciallyhandled only by the embracing sequential ATPG.

Many TPG algorithms for ASDCs were developed and

published [9, 30, 22, 16, 27, 10]. SPIN-TEST [27] is acomplete ATPG for SAFs of ASDCs. Hazard detectionis performed using 13-valued logic during fault simula-tion [29]. SPIN-TEST transforms the ASDC into CR anduses ATALANTA [18] (derivate of FAN) to generate ev-ery possible test pattern for every SAF of this CR. ATA-LANTA performs this step by returning to every possibleplace where value assignment decision was made previ-ously (through exhaustive number of backtracks). Thisprinciple is in contradiction with the requirement of fastTPG (backtrack number reduction), so ATALANTA isslower in this operational mode by many order of mag-nitude. SPIN-TEST performs forward state justificationand sequential fault propagation. It uses the A* search al-

gorithm [24] to generate the sequence of test patterns fora selected SAF. The goal for the state justification is toreach one of the states specified by test patterns (obtainedfrom ATALANTA) for the targeted SAF from the initial


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Information Sciences and Technologies Bulletin of the ACM Slovakia 3

state of ASDC. Every state is considered at the sametime because it is not possible to know in advance whichstate is the easiest to justify. Every possible assignmentto the PIs (represents a test pattern) is considered forevery state, and for every state a cost is computed. Thiscost predicts the number of patterns required to reach thegoal after the acceptation of the given test pattern, andis based mainly on the number of different bit positionsbetween the next state and the goal states, and on therange of corresponding different PPOs from the PIs (thisaffects how easily these values can be changed). The testpattern with the lowest predicted cost is selected, and theexamination continues with the next state. The sequen-tial fault propagation is performed similarly; the goal isto find a state when the faulty signal is on a PO. Thecost is computed based on the range of the PPOs witha faulty signal from the POs. SPIN-TEST uses the A*search algorithm which results in a shorter test sequencein comparison to depth-first search [24] (where always thefurthest state from the initial state is explored first anda closest one is considered only if the search is unsuccess-

ful in the previous direction), but can not guarantee theshortest test length.

IB-TPG [10] is the most general method ever proposedfor the ASDCs and is based on PODEM [13]. In the con-trast to SPIN-TEST, it does not transform ASDC intoCR. The feedbacks are removed using a DfT method [4].C-elements remain in the circuit and their hold/set func-tions are determined. The possible previous states in thejustification process are identified based on these func-tions. The possibility of hazards is examined during thisidentification. The generated test sequence is hypotheti-cally shorter or equal than that of SPIN-TEST (becausebackward state justification is used together with breadth-

first search [24] all of the states reachable with s testpatterns are examined before the states reachable withs + 1 test patterns). The sequential fault propagation ismissing in IB-TPG; the fault is considered as undetectedif the fault is propagated to a PPO and not to a PO. IB-TPG can be used only for ASDCs with C-elements andtogether with DfT methods.

The algorithm proposed in [9] is based on D algorithm andimproves the test quality by considering faults even insideC-elements. Buffers are inserted to feedbacks and a newtime frame is assumed when D algorithm reaches thesebuffers. Going back one time frame is executed whenan inconsistency occurs. The method in [30] deals with

timing constraint violations. It is not a general method,therefore it is applicable just to a smaller class of ASDCs.The ATPG in [22] represents the ASDC as synchronousfinite-state machine and uses methods of synchronous cir-cuits to generate test for the ASDC. The method in [16]is based on D algorithm and is limited to a specific gatelibrary and DfT environment.

SPIN-SIM is a serial fault simulator for the speed-inde-pendent (SI) ASDCs [29, 26]. SPIN-SIM adopts the 13-valued logic [2] to improve the hazard detection accuracyand maintains the relative order of causal signal transi-tions using time stamps. The time stamp includes only asignal group ID and a time. The group ID is used to in-

dicate causal transitions; signal transitions with a causalrelation are assigned to the same group ID. The relativeorder of the causal transitions is recorded in the time field,which is incremented when the transition propagates.

3. Goals of the dissertation thesisMany TPG methods were developed for ASDCs how-ever these methods have many disadvantages: (1) Themost significant problem of current methods is insuffi-cient support of different types of ASDCs. (2) Gener-ated tests are optimized for length only with application

of DfT methods. This results in increased area overheadwhich may negatively influence the timing constraints ofASDCs. (3) Hazards are detected ineffectively just in thefinal phase of TPG. (4) Current ATPGs generate un-necessarily every test pattern for the CR of ASDC and(5) perform fault simulation the least effective way.

The main scientific goal of the dissertation thesis was tocontribute to time- and cost-effective testing of ASDCswith development of the new ATPG which (1) can beused for different types of ASDCs, (2) generates shortertests, (3) does not require DfT area overhead.

The dissertation goals were: (1) to identify the hazardsbefore TPG, (2) to decrease the number of generated testpatterns for CR of ASDC, (3) to justify the state in a uni-versal way, (4) to propagate the fault sequentially usingthe shortest test, (5) to speed up the fault simulation.

4. The new test pattern generation methodThe new developed test pattern generator is designatedas TACTLESS (aTpg for Asynchronous CircuiTs incLud-ing brEadth-firSt Search) [7]. TACTLESS generates thetest sequence for a given ASDC according to Figure 1.The ASDC is transformed into CR, the fault list is pre-pared, and hazardous signal transitions are identified. Afault in the CR is selected and a test pattern is generatedfor this fault by the new developed method. Anotherfault is selected if the fault is untestable (undetectable).The sequential TPG begins after the successful TPG forCR. The state defined by the test pattern is justified (se-quence of test patterns is generated which initialize theASDC to this state from the undefined state). The se-quential fault propagation takes place after the successfulstate justification (sequence of test patterns is generatedwhich propagates the fault effect from PPO to a PO if itis necessary). The TPG for CR is repeated if the statejustification or the sequential fault propagation is unsuc-cessful. The new deductive fault simulator is used afterthe test sequence has been generated; every detected faultis removed from the fault list and TPG continues with thenext fault. The logic value of port P P O0 will be denotedas P P O0 throughout the paper.

Definition 1. The ordered n-tuple S= (s0, s1, . . . ,sn1) is the state of ASDC withn feedbacks ifq {0, 1,. . . , n 1} : sq = P P Oq.

Definition 2. Sa is the previous state ofSb andSb isthe next state ofSa if at least one pattern exists for thePIs of ASDC which changes the state fromSa to Sb.

Definition 3. State Su = (su0, su1, . . . , s un1) is theundefined state of ASDC withn feedbacks only ifq {0,

1, . . . , n

1} :su

q =X

.

Definition 4. The process of finding a sequence of testpatterns for PIs of ASDC which will initialize the ASDC


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Start

ASDC transformation into CR

Fault list preparation

Identification of hazards

Fault

TPG for CR

State justification

Sequential fault propagation

Fault simulation

Every fault

examined?End

Fault list

pass

fail

pass

fail

pass

fail

yes no

Figure 1: Flowchart of TACTLESS

to state Sfrom the undefined state Su is called state jus-tification ofS.

Definition 5. The process of finding a sequence of testpatterns for PIs of ASDC which will propagate the faultysignal from the PPO to a PO is called sequential faultpropagation.

Definition 6. The state justification ofSis consid-ered forward if the space of possibilities is searched in thedirection from the undefined state Su to S, and is calledbackward if the search is performed in the opposite direc-tion.

Definition 7. The sequential fault propagation is con-sidered forward if the space of possibilities is searched inthe direction from PPOs to POs, and is called backwardif the search is performed in the opposite direction.

4.1 Identification of hazards

Current ATPGs are able to detect hazards only in thefinal phase of TPG (by fault simulation). The detectionresults in the repetition of the entire TPG process. This isvery ineffective because not only TPG for CR is executedagain but state justification and sequential fault propa-gation too. The contribution of TACTLESS in this areais identification of hazardous signal transitions before theTPG process. The hazardous signal transitions are notaccepted during the sequential TPG, therefore the num-ber of insufficient test sequences is reduced. However, notevery hazard can be identified in advance; e. g. hazardscan be invoked by faults too. These remaining hazardsare detected by fault simulation.

A new 6-valued logic A6 was developed for hazard identi-fication. Every value of this logic is intended to represent

Table 1: Values of the new 6-valued logic

Symbol Meaning0 logic false1 logic trueX do-not-care value

T 0 1 or 1 0T inverse to TH all hazard types

two subsequent logic values on the given circuit line. Ta-ble 1 enumerates the values of the proposed A6 logic. Thisnew logic does not recognize the direction of transitionsbecause it is not necessary to know it during hazard iden-tification. Another unique characteristic of this 6-valuedlogic is that every type of hazard is denoted as H. Again,it is sufficient to know if a hazard arises somewhere insidethe circuit and propagates to an output. The logic oper-ations on the proposed 6-valued logic are defined in [7].Hazard vectors (Definition 8) are used in TACTLESS toidentify possible hazards.

Definition 8. Letk be the number of PIs andn thenumber of PPIs for a given CR of ASDC, then the vector(a0, a1, . . . , ak1, b0, b1, . . . , bn1) where ar A6 ar =`

P Ir(t) P Ir

(t+1)

for allr {0, 1, . . . , k 1} and

bq A6 bq =`

P P Iq(t) P P Iq

(t+1)

for allq {0,1, . . . , n 1}, is the hazard vector representing transitionof logic values on PIs and PPIs in two subsequent stepst andt + 1 if it is causing a hazard on at least one POand/or PPO.

A new algorithm was developed for hazard identificationwith the A6 logic. The flowchart of the proposed algo-rithm was published in [7]. Hazard vectors are identifiedin CR for every PO and PPO. Hazard value H is assignedto them and backward propagation (in direction from out-puts to inputs) is executed. Values are assigned to thegate inputs based on logic operations. Usually more thanone possibility exists for justification of the given value.The first possibility is assigned to the gate inputs and theothers are inserted into the stack for later evaluation. Theassignments continue in the direction to CR inputs. An-other assignment possibility is examined from the stack ifa contradictory (inconsistent) assignment is detected on a

fanout. The hazard vector (values on CR inputs) is savedafter the assignments are finished and the inputs of CRare reached. The search for hazard vectors continues withanother assignment p ossibility from the stack. All of thehazard vectors are found for the current examined CRoutput with assigning every possibility from the stack.This process is repeated for every CR output. Hazardsare considered on the PPOs too, therefore hazardous sig-nal transitions are not allowed neither on the feedbacks ofASDC. Similarly, the hazard vectors contain signal tran-sitions on PPIs also, which will eliminate hazards causedby state changes.

The space search would become unacceptably extensive ifevery meaningless possibility is considered for gate outputjustification. Heuristic 1 and 2 were developed to reduceeffectively this space under the assumption of single inputchanges (SICs). If during TPG only SICs are consideredthen these heuristics does not interfere with identification


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of every hazard. Firstly, if only one transition can o ccuron the CR inputs then on the inputs of a given gate morethan one transition can occur only if those gate inputsare reachable from a fanout; and these transitions can beof opposite direction only if this fanout reconvergence isof inverse polarity. This implication is used to limit theconsideration of hazardous gate outputs by Heuristic 1.Secondly, hazards can be propagated just from hazardorigins (Definition 9). This is used to reduce the numberof hazardous gate inputs by Heuristic 2.

Heuristic 1. Assign transitions of opposite directionsT, T at the gate with inputs I0, I1, . . . , Ij1 only to IoandIp : o, p {0, 1, . . . , j 1} o = p and ifIo andIpare reachable with different polarity from a fanout (recon-vergence with inverse polarity).

Definition 9. The j-input gate with inputs I0, I1, . . . ,Ij1 is called hazard origin if at least one Io andIp :

o, p {0, 1, . . . , j 1}o = p, suchIo andIp are reachablewith different polarity from a fanout.

Heuristic 2. Assign hazard value H at the gate withinputs I0, I1, . . . , Ij1 only to Io : o {0, 1, . . . , j 1}and ifIo is reachable from at least one hazard origin.

4.2 Test pattern generation for CR of ASDC

New TPG method was developed for CR of ASDCs [8].This method is based on FAN which was developed forcombinational circuits. TPG methods for combinationalcircuits cannot be directly used for ASDCs. The new

method differently handles PIs, PPIs, POs and PPOs;considers complex gates and uncontrollable/unobservablelines of ASDCs. The proposed method extends the ex-isting strategies of FAN and contains new algorithms forsuccessful TPG for CR of ASDCs. The contributions inthis area are: (1) development of the new method basedon FAN, (2) generation of test patterns one-by-one ac-cording to the requirements from state justification andsequential fault propagation (another test pattern is gen-erated only if the previous one was insufficient), (3) gen-eration of better test patterns for CR of ASDC (the testpattern is better if by a shorter test is possible to justifythe state and propagate the fault effect to a PO).

A new definition supporting complex gates is proposedfor the lines in ASDC. This definition eliminates incon-sistencies at complex gates in the fanout-free part of thecircuit. The line of the circuit can be free or bound. Abound line is a line which is reachable from a fanout pointwhile a free line is not reachable from any. A free line isa head line if it is adjacent to some bound line.

Definition 10. Let the Boolean functionFof vari-ables x1, x2, . . . , xk be in disjunctive normal form (DNF)withs conjunctions representing the k-input complex gateG, then mark the inputxi ofG for everyi {1, . . . , k}as a head line and the outputFand all of the subsequentlines in the direction of signal propagation as bound line

ifxi is free line andxi Xg xi Xh, g = h, whereg {1, . . . , s}, h {1, . . . , s}, Xg is the set of variables ofconjunctionmg, Xh is the set of variables of conjunctionmh.

4.2.1 New strategies for test pattern generation

Existing strategies of FAN were extended with the follow-ing new ones to ensure the effective and successful TPGfor ASDCs.

The new strategy for the early identification of unde-

tectable faults is not necessary for the correct execution ofthe TPG but could make it more effective. The necessarycondition for the fault detection is to assign the fault-freevalue to the fault site. This strategy helps to identify ifthis condition is not met.

Strategy 1. Consider the stuck-at-one (stuck-at-ze-ro) fault as undetected if it is on a0-uncontrollable (1-uncontrollable) line.

New strategies eliminate some problems during uniquesensitization of ASDCs by suggesting execution of back-

track when inconsistency occurs with a previously impliedlogic value or at a complex gate with an inner fanout. Itis advised to execute multiple backtrace if none of logicgates can be uniquely sensitized. This will allow to assignboth values if required (by backtrack).

Strategy 2. If the required fault propagation is notpossible during unique sensitization then backtrack shouldbe executed.

Strategy 3. If unique sensitization is not possible forany logic gate then multiple backtrace should be executed.

New strategies for determination of final objectives adviseto execute backtrack in two more cases: (1) When the setof initial objects is empty before the multiple backtrace(this could happen when the set of unjustified lines isempty and the D-frontier cannot be propagated becauseof uncontrollable lines). (2) When the set of head linesis empty after the multiple backtrace (this could happenwhen none of the unjustified lines can be justified).

Strategy 4. If the set of initial objects is empty beforethe multiple backtrace then execute backtrack.

Strategy 5. If the set of head lines is empty after themultiple backtrace then execute backtrack.

The new strategy for multiple backtrace allows to stop themultiple backtrace at free lines and feedbacks. Stoppingat free lines is important because the multiple backtracecan miss the head lines in the presence of complex gateswith inner feedbacks. Stopping at feedbacks is necessarybecause the test pattern should be generated for CR ofASDC.

Strategy 6. Add the current object to the set of headlines during the multiple backtrace if the line is head, freeor is connected to a PPI.


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4.2.2 New algorithms for test pattern generation

Algorithm FAN executes many propagations of differenttypes. These propagations are ensured by many specificalgorithms, e. g. multiple backtrace. These algorithmswere replaced in the proposed new method by new onesto support ASDCs.

Testability measurements (controllabilities and observa-bilities) were previously used in ATPGs for combinationaland synchronous sequential circuits. These measurementsfor complex gates of ASDCs are computed in the proposedATPG as follows. Firstly, controllabilities are determinedfor every logic conjunction in DNF of the given complexgate. This computation is based on application of theexisting rule for the logic gate AND. Consequently thecontrollability is computed for the output of the complexgate by application of the rule for the logic gate OR toprevious results. Secondly, observabilities are transferredfrom the output of the complex gate to the conjunctionsin DNF of this gate (rules of the logic gate OR are used).Consequently the observabilities are determined for everygate input with application of rules of the logic gate ANDto previous results.

The backward implication is the process of assigning u-niquely implied logic values in the direction to POs andPPOs. The justification process of free lines is very simi-lar with only one difference. Assignments during the jus-tification of free lines are not necessarily unique. Whenmore than one possibility exists then the assignment isexecuted randomly. The logic value at the output of thecomplex gate is justified/implicated as follows:

X The undefined value is not justified or impli-

cated. D or 1 The logic (fault-free) value 1 at the gate

output is justified by setting one gate input to value1 while this assignment together with the values onother inputs for the same conjunction in DNF im-plicate the value 1 at this conjunction. When thisassignment is not possible then an inconsistency oc-curred. When there is more than one possibilitythen the assignment is not unique. The assignmentis executed by the multiple backtrace in this caseduring the backward implication, or a random oneis selected during the justification of free lines.

D or 0 The logic (fault-free) value 0 at the gate

output should be implicated by setting one gate in-put while this assignment should be supported byother inputs for the same conjunction. When thereis a logic 1 implied at least on one conjunction thenan inconsistency occurred. When this assignmentis not unique than multiple backtrace follows dur-ing the backward implication, or a random one isselected during the justification of free lines.

Initial objects supporting the fault propagation throughcomplex gates are created as follows. Conjunctions inDNF of the given complex gate are analyzed. If the ana-lyzed conjunction does have an input with a faulty signalthen for every other inputs of this conjunction objects re-questing logic value 1 are constructed. If the conjunctiondoes not have a faulty input then an object requestinglogic value 0 is created on that input where 0 is the easi-est to control.

The algorithm for the multiple backtrace was extendedby the new process for the propagation of objects throughcomplex gates. The input to this process is the object forthe gate output. Outputs of the proposed process are theobjects for gate inputs. The object is propagated to con-junctions in DNF of the given complex gate. The numberof requested values 1 is preserved only for that conjunctionwhere value 1 is the easiest to control. The created newobjects for conjunctions are propagated further to gateinputs. During this propagation the number of requestedvalues 0 is preserved only for the easiest 0-controllableinput of the given conjunction.

The new algorithm developed for unique sensitization sup-ports also complex gates. The sensitization is not al-ways p ossible uniquely. The sensitization should not beexecuted for the complex gate where sensitive paths gothrough more than one conjunction in DNF of the givengate. This algorithm handles differently conjunctions withand without a sensitive path. Logic value 1 is assigned forevery fault-free input of conjunction with a sensitive path.

Supporting the propagation through the complex gate bythe conjunction without a sensitive path is ensured bychanging one undefined value X to value 0. When there ismore than one input with value X in the given conjunctionthen the sensitization is not possible uniquely.

4.3 State justification

Backward state justification is executed by TACTLESSafter the test pattern for CR has been generated. Thestate required by this test pattern is justified perform-ing breadth-first search [24]. Backward state justifica-tion together with breadth-first search guarantee short-est test lengths. The contribution of TACTLESS in thisarea is state justification on the gate level (TACTLESScan be used with any ASDC and is not limited to C-elements; simple gates are used hence it is just the matterof ASDC transformation into CR) and stepwise composi-tion of state graph (it is possible to find interconnectionwith the existing part of the graph, which can make thelater state justifications more effective).

Definition 11. LetV=`

s0, s1, . . . , sn1 `sq

AN sq = P P Oq

for allq {0, 1, . . . , n 1}

denote

the state set based on N-valued logic ANand =`

a0, a1,

. . . , ak1 `ar {0, 1, X} ar = P Ir

for allr {0,

1, . . . , k 1}

denote the test pattern set of ASDC with

n PPOs andk PIs, then the directed graphG = (V,E , )withVas the finite set of vertexes, E

(u, v) | u, v

V u = v

as the finite set of edges and : E as the edge labeling function is the state graph of ASDCwith state logic ANif(u, v) E: test pattern

`(u, v)

changes the ASDC from state u to state v.

Definition 12. The state graphG of ASDC with statelogic A3 = {0, 1, X} is the justification state graph.

Definition 13. LetG = (V,E , ) be the justificationstate graph of the ASDC andut is a state, then for ev-ery(u0, u1), (u1, u2), . . . , (ut2, ut1), (ut1, ut) Ethe

sequence `

(u0, u1)

, `

(u1, u2)

, . . . , `

(ut2, ut1)

,

`

(ut1, ut)

is the sequence of test patterns for statejustification of state ut ifo, p {0, 1, . . . , t} (uo, up V o = p) : uo = up and state u0 is the undefined state.


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The flowchart of the proposed state justification was pub-lished in [7]. Path in the justification state graph is at-tempted to be found from the undefined state to the re-quired state and if this search is successful then the se-quence of test patterns for state justification is reported;and the state justification ends. If the path does not ex-ist yet then the previous states (together with the corre-sponding test patterns) are determined and put into listL (the algorithm for identification of previous states isdescribed later). Every item from L is examined and isadded as an edge to the state graph if the transition isnot hazardous (two subsequent states and test patternsare combined into one vector of 6-valued logic; this vectoris evaluated based on the hazard vector list; the list waspreviously generated as it was described in the previoussubsection). The state part of this item is placed in the listD for later breadth-first evaluation. Every previous statewill b ecome evaluated while list L is becoming empty. Anew state from list D becomes the current (the state se-lection is executed according to breadth-first principle)and its previous states are examined. This process is re-

peated until every state from D is not considered and theundefined state is not found. The path in the state graphis attempted to be identified again. The justification se-quence is reported if this search is successful. Otherwise,generation of another test pattern for CR is suggested tothe embracing sequential TPG. It is possible to find aconnection to the existing part of the graph where a pathwas previously identified. The TPG time is reduced inthis case because it is unnecessary to continue the search.

An algorithm very similar to that one proposed for hazardidentification is used for identification of previous states.The differences are the following: (1) Standard 3-valuedlogic {0, 1, X} is used instead ofA6 logic. (2) The values

for PPOs (the state) are assigned all at once instead of in-dividual processing of the outputs. (3) The current SAF isconsidered inside the CR. (4) The vector defined by PPIsis considered as previous state, and the vector defined byPIs as the pattern required to change the previous stateto the current state.

4.4 Sequential fault propagation

TACTLESS uses forward sequential fault propagation ifthe fault is propagated to PPOs instead of a PO by thetest pattern for CR. The test sequence assembled be-fore is supplemented by the sequential fault propagationsequence which ensures the propagation of faulty signalfrom the PPOs to a PO. The forward sequential fault

propagation performed together with breadth-first searchensures shortest test sequences [24]. The recently pub-lished ATPGs for ASDCs either do not deal with sequen-tial fault propagation or can not guarantee shortest testsequences.

The algorithm for sequential fault propagation is verysimilar to that of state justification. The differences arethe following: (1) Different state graph is used (Defini-tion 14) which considers faulty signals in the state becausethe search is conducted to propagate further these faultysignals. Therefore, the search is interrupted in the direc-tion of states without any faulty signal. (2) The sequen-tial fault propagation sequence is interpreted according to

Definition 15. (3) Not previous states but next ones aresearched for.

Definition 14. The state graphG of ASDC with statelogic A5 = {0, 1, X, D, D} is the state graph for sequentialfault propagation.

Definition 15. LetG = (V,E , ) be the state graphfor sequential fault propagation of the ASDC, then for ev-

ery(u0, u1), (u1, u2), . . . , (ut2, ut1), (ut1, ut) Ethesequence

`(u0, u1)

,

`(u1, u2)

, . . . ,

`(ut2, ut1)

,

`

(ut1, ut)

is the sequential fault propagation sequencefor state u0 ifo, p {0, 1, . . . , t}(uo, up V o = p) :uo = up and a faulty signal (D orD) is in state ut on atleast one PO.

The next states are determined by exhaustive simulationof every test pattern for the given state. This would re-sults in a huge space search without another feature ofthe inner ATPG for CR, i. e. the faulty signal propaga-tion is performed in the direction closest to a PO whichmeans POs have higher priorities than PPOs, and if the

propagation to a PO is impossible then the signal is prop-agated to that PPO from which the further propagationto a PO will be the easiest. This results in a relativelyshort sequential fault propagation, and represents anothercontribution in comparison to other ATPGs for ASDCsbecause their external ATPGs for CR does not considerASDCs.

5. The new fault simulation methodThe new fault simulator was developed for ASDCs [6].This fault simulator is used in TACTLESS for determi-nation of detectable faults. The proposed fault simulatoris able to detect hazards and oscillations too.

The new method was developed for faster fault simula-tion of ASDCs because the existing methods are based onthe slowest method (on the serial method). The proposedmethod is based on the deductive method which was pre-viously used for combinational circuits only. The faultsimulator propagates the list of detectable faults throughfeedbacks (when the fault lists differ on the input and out-put side of the feedback and when the maximum numberof sequential propagations is not reached).

Existing rules for the propagation of fault lists were ex-tended by the developed new algorithm supporting com-plex gates of ASDCs. This algorithm is universal and canbe used for any complex gate represented with Boolean

function in DNF. The list of detectable faults is deter-mined based on fault lists on inputs of the given gate.

5.1 Fault list propagation through complex gates

The deductive fault simulator is based on the propagationof detectable faults in the circuit. The list of detectablefaults is necessary to propagate through logic gates. Thispropagation is executed according to existing rules [21].

Existing rules for logic gates are insufficient for ASDCswhich can contain complex gates too. The new methoddeveloped for complex gates is able to determine detect-able faults at the output of the complex gate if the faultlists are known for the inputs. The first conjunction inDNF of the given complex gate is analyzed. Logic valuesand fault lists of this conjunction are processed accordingto rules for the logic gate AND. The result (faults) isplaced to the set A or B based on the evaluated logic value


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2004.[16] A. Khoche and E. Brunvand. Critical hazard free test generation

for asynchronous circuits. In Proc. 15th IEEE VLSI Test Symp.,pages 203208. 1997.

[17] H. Krad. Multi level combinational circuits and hazard detection.In Proc. IEEE Southeastcon, volume 2, pages 573575. 1992.

[18] H. K. Lee and D. S. Ha. On the generation of test patterns for

combinational circuits. Technical Report 12_93, Dept. of Elect.Eng., Virginia Polytechnic Inst., 1993.

[19] D. E. Muller and W. S. Bartky. A theory of asynchronous circuits.In Proc. Int. Symp. Theory of Switching, pages 204243. HarvardUniversity Press, 1959.

[20] Myers Research Group. Atacs online demo.www.async.ece.utah.edu/atacs-bin/demo, [Accessed:8.10.2010], 1999.

[21] O. Novk, E. Gramatov, R. Ubar, and col. Handbook of TestingElectronic Systems. Czech Technical University PublishingHouse, 2005.

[22] O. Roig, J. Cortadella, M. Peiia, and E. Pastor. Automaticgeneration of synchronous test patterns for asynchronous circuits.In Proc. 34th Design Automation Conf., pages 620625. 1997.

[23] J. P. Roth. Diagnosis of automata failures: a calculus and a

method. IBM J. Res. Dev., 10(4):278291, 1966.[24] S. J. Russel and P. Norvig. Artificial Intelligence: A Modern

Approach. Prentice-Hall, New Jersey, USA, 1995.[25] F. Shi and Y. Makris. Fault simulation and random test generation

for speed-independent circuits. In Proc. 2004 Great Lakes Symp.VLSI, pages 127130, 2004.

[26] F. Shi and Y. Makris. SPIN-SIM: Logic and fault simulation forspeed-independent circuits. In Proc. 2004 Int. Test Conf., pages597606, 2004.

[27] F. Shi and Y. Makris. Spin-test: automatic test pattern generationfor speed-independent circuits. In IEEE/ACM Int. Conf.Computer Aided Design, pages 903908. 2004.

[28] F. Shi and Y. Makris. Testing delay faults in asynchronoushandshake circuits. In Proc. 2006 IEEE/ACM Int. Conf. ComputerAided Design, pages 193197. 2006.

[29] F. Shi and Y. Makris. Enhancing simulation accuracy throughadvanced hazard detection in asynchronous circuits. IEEE Trans.

Comput., 58(3):394408, 2009.[30] F. Shi, Y. Makris, S. Nowick, and M. Singh. Test generation for

ultra-high-speed asynchronous pipelines. In Proc. IEEE Int. TestConf., pages 110. 2005.

[31] J. Sparso and S. Furber. Principles of asynchronous circuitdesign: A systems perspective. Kluwer Academic Publishers,Dordrecht, The Neederlands, 2001.

[32] F. te Beest and A. Peeters. A multiplexer based test method forself-timed circuits. In Proc. 11th IEEE Int. Symp. AsynchronousCircuits and Systems, pages 166175. 2005.

[33] W. Toms. Synthesis of Quasi-Delay-Insensitive DatapathCircuits. Ph.d. thesis, University Manchester, School of ComputerScience, Manchester, United Kingdom, 2006. ftp://ftp.cs.man.ac.uk/pub/amulet/theses/Toms06_phd.pdf,[Accessed: 8.10.2010].

Selected Papers by the AuthorM. Bal, R. Dobai, E. Gramatov. Delay Faults Testing. In R. Ubar,

J. Raik, and H. T. Vierhaus, editors, Design and Test Technologyfor Dependable Systems-on-Chip. IGI Global, Hershey, 2010. Inpress.

R. Dobai, E. Gramatov. A Novel Automatic Test Pattern Generatorfor Asynchronous Sequential Digital Circuits. Microelectron. J.,2010. In press. Doi:10.1016/j.mejo.2010.10.013.

R. Dobai, E. Gramatov. Deductive Fault Simulation Technique forAsynchronous Circuits. Comput. Inform., 29(6): 10251043,2010.

R. Dobai, E. Gramatov. Deductive Fault Simulation forAsynchronous Sequential Circuits. In 2009 12th EUROMICROConf. Dig. System Design, Architectures, Methods and Tools:

DSD 2009, pages 459464, Patras, Greece, 2009.

R. Dobai, E. Gramatov. Test Pattern Generation for theCombinational Representation of Asynchronous Circuits. In 13thIEEE Int. Symp. Design and Diagnostics of Electronic Circuits

and Systems, pages 323328, Wien, Austria, 2010.

R. Dobai. Testing of Delay Faults in Asynchronous Circuits. In 14thIEEE European Test Symp.: ETS09, Sevilla, Spain, 2009. CD.

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