Proj08 ECG Notes

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EE4410 Integrated circuit and system design Xu YP 1

EE4410 ProjectECG Signal Acquisition System

XU Yong Ping

Dept of Electrical and Computer EngineeringEmail: [email protected]


1. Module organization

2. Project Introduction

3. A-to-D Conversion Basics

4. Successive Approximation ADC

5. Band-gap reference

6. Noise analysis

Outline


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1. Module organization

AimsThrough the design of a prototype IC chip

To provide the opportunity for students to applyfundamentals and theory to the real life problems

To improve students analytical and problem solvingskills

Expose students to commercial integrated circuitdesign flows and teamwork

To introduce mixed-signal circuit design, in particular,ADCs and DACs


How to study in this module?

Try to apply what you have learned before and in this moduletothe practical problems in the project. Many modules you studiedbefore are relevant to this project.

Although the design tool (such as Cadence) is very powerful,always remember to pay attention to and understand theunderlying principles

Try and error with the powerful design tools is not a goodapproach to carry out the design. Only use the design software toassist your analysis.

Literature research helps you understand the existing methods andtechniques, as well as their limitations. Try not to copy whatpeople have done, but understand their approaches and

limitations, and see if you can come up with better ideas toovercome their limitations, and hence improve the performance.

There are many ways to design and realize the same function.Analog and mixed-signal IC designers need to be innovative.


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Lectures and Labs (1)

2 weeks 11 weeks

4 ~ 5 weeks

Semester 1:

Tape-out

Start

Familiarizationwith EDA tools Chip design

Lecture (2hrs/wk) Laboratory (4hrs/wk)


Lectures and Labs (2)

2-3 weeks 8 weeks

2-3 weeks

Semester 2:

Assessment

Start

1. Chip design presentation2. Chip test preparation

Testing thefabricated chip

2 week

Report writing

PresentationDesign presentation

from each group

Lecture (2hrs/wk) Laboratory (3hrs/wk)


4/46


2. Project introduction

Scope

Specifications

Project schedule and execution

Assessment

Refer to the handout for more details


The scope

ECG (Electrocardiogram) signal acquisition system

Successive Approx.ADC

+

Low noiseAmplifier

Dout

Vin,ECG -

ADCLPF

VoltageReference

Biascircuit

Lowpassfilter

S/H

Sample&hold

Recommendation for system partition

Low noise amplifier and LPF (one student)

ADC and S/H (two students)

Bandgap reference (one student)


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Specifications

System and analog Technology: 0.35-m CMOS System supply voltage: 3V

System bandwidth: 0.5 150Hz

Amplifier gain: 200

Input referred noise: 50 mV CMRR (instrum. amplifier): > 50dB

Power consumption: As low as possible

ADC Resolution: 10 bits

Sampling frequency 500Hz

Output format: Binary coded

DNL and INL: < 2 LSB

Load capacitance: 2.5pF@ADC output

With on-chip reference

End of conversion (EOC)


Schedule and execution

Week 0

Introduction to module and project

Grouping and lab schedule

Week 1 6

Lectures and chip design (lab)

Week 7 11

Chip design (lab)


6/46


Assessment

Individual

Subsystem design 35%

Subsystem performance 20%

Chip design presentation 10%

Team

Overall chip design 15%

Overall chip performance 15%

Report writing 5%


3. A-to-D conversion

Qantization

Sample & hold

Anti-aliasing filter

vinvo

Sample&hold

Anti-aliasing Quantizationn


7/46


Quantization and noise

000

001

010

011

100

Digitaloutputcode

Analog input0

101

110

111

3-bit ADC ADCDigital output

DoutAnalog input

VinTheoretical ADCtransfer characteristic

Practical idealADC transfercharacteristic

1LSB value (Step width)

Midstep ValueCenter point

1 2 3 4 5 6 7 (FS)

Analog input

-1/2 LSBQuantizationErr

or

0 1 2 3 4 5

+1/2 LSB

6 7

121

=

n

FSLSB

A full scale (FS) analog signal is convertedinto 2n discrete levels which correspond tondigital bits. Hence one LSB (Step width)for an n-bit ADC is

The quantization error is bounded between0.5LSB, that is

2)(

2

neq

where is the quantization step size, = 1 LSB.

For 2n >>1,

=

=nn

FSFSLSB

2121

Quantization noise:


Signal-to-quantization noise ratio

If assuming that eq(n) is equally distributed (equal

probability density) over the range of (-/2, /2), asshown below,

e

P(e)

/2/2

1/

0

12

1)(

22

2

22

2

22 =

===

deedeepeP en

and is not correlated with the signal, thequantization noise power (the variance) is

Quantization noise power: Signal-to-quantization noise ratio:

( )2

2

2

22FSA

Ps ==

Assuming that the signal is a full-scale sinusoidalwave with an amplitude of A, the signal power foran n-bit ADC is

( ) ( )

dBn

FSFS

A

P

PdBSQNR

n

n

s

76.102.6

12

2

2

2lg10

122lg10

lg10)(

22

22

+

=

=

The signal-to-quantization noise ratio (SQNR) is


8/46


Sampling and aliasing

t

xa (t)

t

ms (t)

1

t

xo (t)

xa (t)

ms (t)

xo (t)

|Xa ()|

2B

t ->

t ->

Sample

|Ms ()|

|Xo ()|

s 2s 3s

s 2s 3s

-2B 0 2B

Bs 2

2

'22

Bs 16?

320X = 13.7

ref1= 16

No 0 < X < 16

160

ref2 = 8

2. X > 8? Yes 8 < X < 16

168

ref3 = 12

3. X > 12? Yes 12 < X < 16

1612

ref4 = 14

4. X > 14? No12 < X < 14

1412

ref5 = 13

X

X

X

X

5. X > 13? Yes 13 < X < 14

(25)

LSBError

Errorx

2

15.0

2

1314(max)

2.07.135.135.132

131413~

=

=

===

+=

"0" is assigned to bit 4 (MSB)

"1" is assigned to bit 3



"1" is assigned to bit 0 (LSB) and the digital output is 01101.


12/46


System architecture

SAR

+

DAC

Comparator

Register

Dout

Vin,ana

Vref

-S/H

CLK

CLK

S.Conv

Vin

Vref

0

# of successive approximation1 2

34

5

0.5Vref1 0 1 1 0 Dout0 1

Final approx.

Error

67

SAR Successive Approximation Register


Successive approx. Register (SAR)

n- k= 0?

Vin > VDAC?yes

no

k = k+1

yes

noBit(n-k) = 1

S.conv

E.conv

k= 0

Bit(n-k) = 0

SAR

+

DAC

Comparator

Register

Dout

Vin,ana

Vref

-S/H

CLK

CLK

S.Conv


13/46


Successive approx. Register (SAR)

Example:

*Johns & Martin, Analog Integrated Circuit Design, First edition, John Wiley & Sons, 1997


Charging scaling DAC

C C

Vref

2C2n-1

C2

n-2C

Capacitor array DAC

(Ctotal

= 2nC)

Vo

)1(,2,1

22

2

=

==

nk

VVC

CV ref

nk

refn

k

o

L

Charge Scaling (Capacitor divider)

When the kth capacitor is switched to Vref

C C

D0

Vref

2C2n-1

C2

n-2C

Vout

D1

Dn-2

Dn-1

Charge Scaling DAC

=

=1

0 2

2n

k

refn

k

kout VC

CDV


14/46


SA-ADC based on charge scaling


Charge redistribution DAC

C C

Vref

2C

Vo

D2

D1

D0

S1

Charge redistribution (Charge sharing)

C C

Vref

2C

Vo

D2 D1

D0

S1

C C

Vref

2C

Vo

D2

D1

D0

S1C C

Vref

2C

Vo

D2

D1

D0

S1

Discharge C array D2 = 1, D1,0 = 0

24

2 refrefo

VV

C

CV ==

D1 = 1, D2,0 = 0

44

ref

refo

VV

C

CV ==

D2,1 = 1, D0 = 0

4

3

4

3 refrefo

VV

C

CV ==

* D2 returns to 0, 2C is discharged. Vo is back to zero before D1 becomes 1.


15/46


SA-ADC based on charge redistribution

Vin

C

reset

C

Dbit,out

Vref

2C2n-1C2n-2C

from SAR

Comparator

Capacitor arrayDAC

(Ctotal = 2nC) Vtop

Operation: Reset Sampling Vin Conversion

reset

Capacitorarray

Dbit,out

Comparator

Resetreset

Capacitorarray

Dbit,out

Comparator

Vin

VC

Sampling Vin

0=CV

inC VV =*Assume Vos = 0


SA-ADC based on charge redistribution(contd)

Vin

C

reset

C

Dbit,out

Vref

2C2n-1C2n-2C

from SAR

Comparator

Vtop

Capacitor arrayDAC

(Ctotal = 2nC)

Conversion:

reset

2n-1

C

Dn-1

Comparator

Vref

2n-1

C

Vi,comp

2

refV

2

refV

Vin

Vin

2,

ref

incompi

VVV +=

0

0

21

,

=

>+=

n

ref

incompi

D

VVV

reset

2n-2

C

Dn-1

Comparator

Vref

3(2n-2

)C

Vi,comp

4

refVVin

4,

ref

incompi

VVV +=


16/46


Capacitance mismatch error

22max,LSB

INLforC

CnINL


17/46


Commercial Successive approx. ADCs

Resolution: 10b

Conv. Time: 20S Supply: +5V and -12V

Power diss.: 325mW

Resolution: 12b

Conv. Time: 1.6S Throughput: 100kSPS

Supply: +2.7 to 5.25V

Power dissipation:0.9mW@100kSPS and 3V


Comparator

+

-

V0

Vop+

Vop-

V0Vin

+ = VVVin

=

+

)0(

)0(0

inop

inop

VV

VVV

=

)(0

)(0

refin

refinop

VV

VVVV

Non-ideal comparatorIdeal comparator

0

V0

Vop

Vin0 Vref

V0

Vop

t0

Vref

Vin Zero rise andfall time

No input offset

Infinite gain

No hysteresis

V0

Vop

t0

Vref

Vin

Low gain reduces theresolution.

Non-zero offsetintroduces error.

Hysteresis introduceserror, but increases thenoise immunity.

Slew rate limits thespeed.

Limited slew rate

Non-zero offset

Effect of non-idealities:

V0

Vin0

Minimum resolvedinput voltage

V0

Vop

Vin0

Hysteresis

High gain

Low gain

Zero offset


18/46


High-gain amplifier as a comparator

High gain

High speed

Low offset and hysteresis

In summary, a comarator should have

High-gain Amplifier as a comparator

Vin

V0

Vop+

Vop- inV

V

VslopeA

== 0

High gain and high slew rate are required.

ideal

high gain

low gain

+

-

V0Vin A

ucldBcl

udBvo

A

A

=

=

3

3

|A(j)|

Avo

0dB3dB u

Acl=1/

3dB-cl

V0

Vfinal

t0

Specified settling error

(% with respect to Vfinal)

tsettle

Setting time of the single-pole amplifier


Linear settling time

Linear settling time:

The settling time is a small signal behaviorand can be obtained from the inverseLaplace transform of the transfer function.

A closed-loop amplifier is shown below.Assume that the opamp is compensated to asingle-pole response.

( )dB

vv

s

AsA

3

0

1 +=Open-loop:

( )( )( )

( )( )sA

sA

sV

sVsA

v

v

in

cl +==

1

0Closed-loop:

Substitute (1) into (2),

( )cldB

u

u

ucl

sssA

+

=+

=

3

( )10 >> VA

A(s)

-Vo(s)

(1)

(2)

( ) ( )svs

sv incldB

u

+

=3

0

In time domain,

( ) ( ) ( )tvetv intcldB=31

10

=

=)(

)()(ln

1

)(

)(1ln

1 0

3

0

3 tv

tvtv

tv

tvt

in

in

dBindB

settle

The settling time is Actual output

Expected output

For the settling error less than 1%,

cldB

t

3

6.4or

The output of the closed-loop amplifier is,assuming that Vin (s) is a step signal,

Settling error

BW

t

6.4

BW = 3db (Open-loop)= 3dB-cl (Close-loop)= u (Unity-gain)


19/46


Nonlinear settling time slew rate

-

+

CC

A2I0

Vo

- VC +

M3 M4

M1 M2

I0

I0

C

C

C

I

dt

dV

dt

dVSR 00 ===

2

0

m

u

g

ISR

==

Nonlinear settling is a large signal behavior. Small-signal model or analysis istherefore not valid.

Transistors are operated in nonlinear regions (triode or cutoff)

The nonlinear settling time is determined by the slew rate

Slew rate indicates how fast the output signal reaches its final value under largesignal condition.

0I

dt

dVC C

C=

C

mu

C

g 2=Since

-

+

CL

A2 Vo

Vin

I0


Regenerative comparator

Regenerative latch and metastability:

- Regenerative latch increases the speed of thecomparator due to its positive feedback.

- Preamplifier increases the resolution of thecomparator and reduces the kick-back noise.

=

initial

final

m

Llatch

V

V

G

Ct ln

Gm is the transconductance of the inverter.

(2.1)

Latch time the time required for the latch output toreach a valid logic level.

Metastability occurs when the valid logic level cannot beReached within the required time frame. To reduce metastability,large Vinitial and high transconductance are required.

Vinitial/final

CL CL

Vfinal

Vinitial

Valid logic high

tlatch

Valid logic low

+

-

A V0

CLK

The kick-back noise occurs when the latch isreset. It disturbs the output of drive circuitwhich may take long time to recover.

+

-

A V0Regenerative

latch

Kick-back noise

Drive

circuitVin

CLK

Preamplifieracts as a buffer

Preamplifier

Latch

Regenerative latch


20/46


Examples

1 = 0 -> Track phaseThe drain voltage of M12 and M13. is equal to VDD and Q= 0. The drain voltage of M6 and M7 is ground.

1 = 1 -> Latch phaseThe drains of M6 and M7 are discharged initially throughM8 and M9. The discharge currents depend on the inputsignal. After the discharge starts, an Vinitial isdeveloped across the latch and regenerative processfollows.

The diode connected transistors D1 and D2 -> limits theoutput swing and helps the overload recovery.

No static current in the latch, therefore, low powerconsumption.

The bandwidth of the preamplifier may be limited due tothe high resistance at the output node.

Low kick-back noise.

VipQ

Qn

Vibias

1

1 1

Preamplifier Latch

M1M2

M3 M4

M5

M6 M7

M8 M9

M10 M11

M12 M13

M14 M15

Regenerative comparator 1

Vin

D2

D1


Examples (contd)

Vin

V0

Vbias

1

Low power consumption as there is no static

current in track phase.

High kick-back noise coupled through the drain-gate parasitic capacitance of M1 and M2.

Comparator 3 has less kick-back noise, but slightlyhigh power consumption due to the static currentin the latch during track phase.

M1 M2

M3

M4

M5

M6

M7

M8 M9

M10 M11

M12

Preamplifier Latch


Vin

To SR latch

Vbias

2

1 = 0 and 2 = 1 -> Track phaseTwo output nodes are pulled to Vdd and M12 is on.The RS latch holds the previous decision. Thedifferential current from the preamplifier (M1 andM2) causes a small Vinitial across M12.

1 = 1 and 2 = 0 -> Latch phase.The latch regenerates from Vinitial to a full digitaloutput.

M1 M2

M3

M8 M9

M10 M11

M12

Preamplifier Latch


1


21/46


Sample and hold circuits

Sample and hold

0

Vo

tt1 t2 t3

Vin

clk

vin voSample& hold

Ideal

hs

0

Vo

t

sh

Vin

Non-ideal

During the sample period, the output tracks the input.Thus, it is also called Track-and-hold.


Simplest S/H circuit

vo

Clk

C

vin

0

Vo

t

Vin

s h s sh

0t

0t

Clk

Input signal range:

TDDin VVV


22/46


On resistance of switch

Tddin

thinDDoxn

non VVVwhen

VVVL

WC

R =

= ,)(

1,

0

Ron

VinTDD VV

NMOS

0

Ron

VinTV

PMOS

Tin

thinoxn

pon VVwhen

VVL

WC

R =

= ,)(

1,

NMOS:

PMOS:

NMOS/PMOS: ponnonnpon RRR ,,, =

0

Ron,np

VinTV Tdd VV

Complementary switch gives low Ron,but requires- Complementary clock- More chip area- More leakage

0

Ron,np

VinTTdd VVV =

High Ron

Low voltageproblem


Settling (Acquisition) time

vo

C

vin

Ron

First-order settling:

( )( )

=

=

,%

1ln1ln 0

errorsettlingCR

tv

tvCRt on

in

onsettle

t t t th h h h

actual

t

V0

)(

,%

1ln

Tinclkoxn

settle

VVVL

WC

errorsettlingC

tor

=

Signal dependent

Fast settling requires small Ron and C


23/46


S/H errors and remedies

Clock feedthrough

Charge injection

Droop (Voltage on holding capacitor)

Aperture time and error


Clock feedthough

Lgs

gs

DDCC

CVV

+=

- Clock feedthrough is caused by parasitic capacitancein MOSFET.

- Independent of input voltage.- Only introduces constant DC offset or Pedestal error.

V

vo

Clk

C

vin

CgsCgd

vdd

0

Remedies:

vo

Clk

C

vin

CgsCgd

vdd

0 Clkvdd

0

Dummytransistor(half size of the switch)

Cgd/2 Cgs/2

q q/2 q/2

- Use dummy transistor- Use complementary switch- Use differential structure


24/46


25/46


Droop

Droop leakage of charge from the holding capacitor

P-sub

n n

CL

vin

v0

Clk

Leakage

Leakage

RL


S/H circuits

+

-

vinvo

C

A

Clk

RL

- Opamp voltage follower acts as a buffer for S/H circuit.- High gain is required to ensure the virtual short at the inputs of the op-amp and

hence the accuracy of the S/H signal.

- Fast settling is required for the op-amp voltage follower.- Since the non-dominant pole may not be far away from the unity gain frequency,

the follower is a second-order system and may have a slower settling than thefirst-order system.

- Signal dependent charge injection exists

vo

Clk

C

vin

qq

( )thinDDox VVVWLCq =2

1

Open-loop S/H circuits


26/46


Closed-loop S/H circuit -1

+

-

vinC

1

2

A +

-

voA

1

+

-

vinC

A +

-

voA

Track

C

+

-

voA

Hold

(vin)

- Closed-loop with holding capacitor at the output of the op-amp- The first op-amp can deliver large charging and discharging current and therefore, improve the speed.- Hold phase is similar to the open-loop S/H.- Signal dependent charge injection still exists


Closed-loop S/H circuit - 2

+

-vin

C

2A +

-

voA

1

+

-vin

C

A +

-

voA

Track (1)C

+

-

voA

Hold (2)

Signal dependent charge injection is eliminatedSince one terminal of the switch is at ground orVirtual ground.

ClkC

q

-

+( )thDDox VVWLCq =2

1


27/46


Bottom-plate sampling S/H circuit

vo

1

C

vin

q2q1

2

vo

1

C

vin

q2=0q1

2

Ic=0

SW1

SW2

2

t

1

t

- Clock 2 is closed slightly earlier than 1.- Since there is no current path through the capacitor, q2 is zero and the charge on

C remains unchanged.- The charge injection from SW2 to the bottom plate is signal-independent.- Signal dependent charge injection is therefore eliminated.


Outline

Bandgap voltage reference

PTAT current source

Design issues

5. Band-gap reference


28/46


29/46


Voltage source with positive TC

+ VBE -

nI0 I0

Q1 Q2

nV

I

IV

I

nIV

VVV

T

S

T

S

T

BEBEBE

ln

lnln2

0

1

0

21

=

=

=

Positive TCnq

k

T

VBE ln=

Assuming that two transistors are matched.

VBE

I0

I0

nV

nI

IV

I

IV

VVV

T

S

T

S

T

BEBEBE

ln

lnln1

0

1

0

21

=

=

=

R

Vb =VBE1

VBE1

a

b

(n x AE)Q2Q1(AE)



+

Vref-

(n x AE)

R1

Q1 Q2

-

+

R2

R3

(AE)

ab

ba VV = 21 RR = 232 BERRref VVVV ++=

nVRR

VVI T

BEBER ln

1

33

21

3=

=

nVR

RRIRIV TRRR ln

3

222 322

===

nVVVV TBEBER ln213 ==

2

3

2

2

3

2

ln1

lnln

BET

BETTref

VnVR

R

VnVnVR

RV

+

+=

++=

(Negative TC)(Positive TC)

0ln13

22 =

++

=

n

T

V

R

R

T

V

T

VTBErefFor zero TC of Vref,


or ( )( )qEVmVnVR

RgTBET +=

+ 4ln1 2

3

2

(1)

(2)

(2) into (1),

( ) qEVmV gTref ++= 4

, ,

When T = 0,

qEV gref =


30/46


31/463


Bandgap voltage reference using PTAT

R1

- +

IR

R2

Vref

Q3

3

1

2322

lnBETBERref VnV

R

RVRIV +=+=

R1 R2

Vref

Q3

Q2(nxAE)

Q1(AE)

Q2(nxAE)

Q1(AE)


Design issues

Collector current variation

Opamp offset

Feedback polarity

Start-up problem

Temperature dependence of reference

voltage


32/463


Collector current variation

T

qEVmV

T

V

T

I

I

V

I

I

T

V

T

I

IT

I

IV

I

I

T

V

T

V

qTBE

TS

S

T

S

CT

C

C

S

S

T

S

CTBE

+=

+

=

+

=

)3(

ln

11ln

R

nVII TRC

ln==VBE=VTlnn

I0

I0

R PTAT

Q2(nxAE)Q1(AE)


Opamp offset

osTBEosBER VnVVVVV == ln213

+

Vref-

(n x AE)

R1

Q1 Q2

-

+

R2

R3

(AE)

ab

Vos

Q1(AE)

R1

- +

IR

VBE

ba

VGS+

VDD

Q2(nxAE)

A

Vos

+

+

( ) 23

2 ln1 BEosTref VVnVR

RV +

+=

( )osTR VnVR

I += ln1

1

*The offset voltage may be a function of the temperature


33/463


Feedback polarity

223

23

1

1

RgR

gR

m

mN ++

+=

+

Vref-

(n x AE)

R1

Q1 Q2

-

+

R2

R3

(AE)

ab

-

+

R2

a

bR3

R1VBE1

VBE2

Vref

1/gm1

1/gm2

11

1

1

1

m

mP

gR

g

+=

Feedback coefficients:

( )( )NP

BENBEPBEBEref

A

VVVVAV

+

=1

2121

Positive feedback if P > N


Start-up problem

Q1

R1

The circuit has two equilibrium points. It may not start operationitself if all nodes have zero initial voltage

Q2

Rc

M5

Start-up circuit

M6


34/463


Noise definition

Noise presentation in time domain

Noise presentation in frequency domain

Noise measures

Noise models

Example

6. Noise analysis


Noise definition

Any unwanted signals or interferences tothe desired signal can be considered asnoise.

Examples

Random interferences (thermal noise)

Toned interference (50/60Hz from main, dcoffset)

Spectral interference (flicker noise, aliasing)

Mixed interference (inter-modulation)


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Noise presentation in time-domain

=T

nT

avn dttiT

P0

2

, )(1

lim

(Referring to random noise)

rms noise voltage or current:2/1

0

2, )(

1

=

T

nrmsn dttvT

V

2/1

0

2, )(

1

= T

nrmsn dttiT

I

2,

2,

1rmsn

rmsnn V

VP =

=

2,

2, 1 rmsnrmsnn IIP ==

Normalized noise power:

Average noise power: =T

nT

avn dttvT

P0

2

, )(1

lim

t

noise

T Time during which the noise is observed


Noise presentation in frequency-domain

=

0

22

,)( dffVV

nrmsn

=0

22, )( dffII nrmsn

f

Noisepower Noise spectrum

Mean squared value (total noise power):

V2n,rms(f) and I2n,rms (f) are the power spectral density (V

2/Hz or A2/Hz)

Understand noise spectrum:

nNoisepower

fnvVn

nrmsn =

=1

22, )(

1 2 3 4 5 6

Resolution BW


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Equivalent noise bandwidth (1)

[ ] 2/122 )()2()( fVfjHfV nino =H(s)Vni(f)

2/12

0

1

1)2(

+

=

f

f

fjH

Single-pole transfer function

f

0dB

f0

( ) 210

2

0

2

0

22

,fVdf

ff

VV nwnwrmsno=

+=

The total output noise power is

f

V2nw

f0

Filtered out

White noise

f

V2nw

White noise

ff0 ffeq

02

ffeq

=Equivalent noise bandwidth:

V2nw V2

nw


Time vs frequency domain (1)

t

f

VP

0f0

f1

f2

f3


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It is quite different result if the signal isobserved in the frequency-domain throughFourier Transformation (FFT). Its spectralcontents are clearly seen.

None of the signals cannot be identifiedexcept for a slight DC offset.



Phase difference between two signals can

be clearly seen in time domain. However, in frequency domain, they are

almost identical.

Power spectrum does not convey the phaseinformation.


38/463


Noise summation

Vn1(t)

Vn2(t)

Vn0(t)

In0(t)

In1(t) In2(t)

[ ]

2

,2

2

,1

021

2

,2

2

,1

0

2

21

2

,

)()(2

)()(1

rmsnrmsn

T

nnrmsnrmsn

T

nnrmsno

VV

dttVtVT

VV

dttVtVT

V

+=

++=

+=

( ) ( ) ( )tVtVtVnnno 21

+=

2

,2

2

,1, rmsnrmsnrmsnoVVV +=

2

,2

2

,1

2

, rmsnrmsnrmsno III +=

Similarly,

2

,2

2

,1, rmsnrmsnrmsnoIII +=

(Vn1 and Vn2 are not correlated)


Noise measures

Input referred noise (equivalent input noise)

V0

In1

In2

Vn1

Vn2

Noiseless circuit Output

RS

Noisy circuit

Input In,rms

Vn,rms

Vs

Noise equivalent circuit:

RS

Vs

Zin

Vin

v

in

Av

v=0

ovvv

ins

in

s

AAZR

Z

v

v,

0 =+

=

Vn,th Noiselesscircuit

Output

RS

Noisy circuit

InputVs

Vni

Input referred noise

Vn,th Thermal noise from the signal source

Zin Vno


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Vni1

Input referred noise (2)

( ) 22,

2

2

,

2

,

2

1 insrmsn

ins

inrmsnthnni ZRi

ZR

Zvvv +

++=

Noiselesscircuit

RS

Noisy circuit

In,rms

Vn,rms

Vn,th Zin Vno

( ) 22,22

2

,

2

,

2

1

2

insrmsnv

ins

inrmsnthnvnivno ZRiA

ZR

ZvvAvAv +

++==

niovvn vAv ,0 =

Noiselesscircuit

RS

Noisy circuit

Vni ZinVni1

22

,

2

,

22

,

2

,

2

,2

,

22

4 srmsnrmsnssrmsnrmsnthnovv

noni RivfkTRRivv

A

vv ++=++==


Signal-to-noise ratio (SNR)Noise figure (NF)

=

n

s

P

PdBSNR log10)(

Signal-to-noise ratio (SNR):

or

=

=

rmsn

rmss

rmsn

rmss

V

V

V

VdBSNR

,

,

2

,

2

, log20log10)(

Ps - signal power , Pn - total noise power

Noise figure (NF)

NF describes how much the noise has increased through the circuit under evaluation.

Total available output noise power

NF = Output noise power due to thermal noise from the source only

1log10log10)(2

,

22

,

2

,

2

,

,,

, >

++=

=

thn

srmsnrmsnthn

thnovv

niovv

v

Rivv

vA

vAdBNF

( )( )

o

i

SNR

SNRdBNF log10)( =or


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Thermal or Johnson noise generated from a resistor

kTRfV rn 4)(2, =

R

kTfI rn

4)(2, =

fkTRV rmsnr = 42

,

RfkTI rmsnr = 42

,

rmsnoise voltage in bandwidth f: fkTRV rmsnr = 4,

( ) 2/1, 4 RfkTI rmsnr =

Vn,r

RNoise spectral density:

rmsnoise power in bandwidth f:

In,rR

R - noiseless

Thermal noise is a white noise

Noise models

Noise in resistors


kT/C noise

( )

( ) CkT

dRC

RCkTRdjHVV nrmsn =

+

==

0 22

2

0

222,0

1

14

2

1)()(

2

1

R C

R

C

H(jw)

kTRfVnr 4)(2 =

2,0 rmsnV

2,0 rmsnV

CjR

CjjH

1

1)(

+=

Vnr(f)

Noise equivalent circuit

Recalculate the total noise power using the equivalent noise bandwidth:

RCf

=

2

10

RCRCffeq

4

1

2

1

220 ===

-3dB frequency: Equivalent noise bandwidth:

C

kT

RCkTRfkTRV xrmsn ===

4

1442 ,0 Independent of R

f0 feq

4kTR

kT/C

f


41/464


Diode

In,DrD

Ddn qIfI 2)(2

, =

The noise source in a diode or PN junction is shot noise, caused by random passage ofindividual charge carriers across a potential barrier. Shot noise is a random noise and white.

Noise spectral density:

rmsnoise power in bandwidth f: fqIIDrmsnd = 2

2

,

ID

i(t)

t

In,d (t)

Idiode

P(i)

ID

Ddn kTrfV 2)(2

, =

D

DqI

kTr =

fkTrVDrmsnd

= 22,


Bipolar transistor

Bnb qIfI 2)(2 =

The noise sources in a bipolar transistor include Shot noise in base and collector currents Flicker noise in base current

Relates to the trapping and releasing of the carriers by energy states (such as surfacestates) caused by the defects in the material.

Thermal noise in base resistance

Cnc qIfI 2)(2 =

bnb kTrfV 4)(2 =

f

Iqf

f

KIfI BcnrBnf

2)(2 ==

Vni

Ini

+=+=+= b

m

b

Cm

Cb

m

ncni

rg

kTkTrqI

kT

g

qIkTr

g

Iv

2

144

24

2

22

++=++=

22

2222

)(2

)( f

I

f

KIIq

f

IIII CBB

ncnfnbni

+

fcnr is correlated with the 1/f corner frequency

K is a constant related to the process

Input equivalent noise power spectral density:


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MOS transistor (1)

The noise sources in a MOS transistor include Thermal noise in the channel resistance

Flicker noise in the channel (arising from the gate-substrate interface)

Induced gate noise

Thermal noise in resistive polysilicon gate, drain and source

Shot noise of junction leakage current

Thermal noise due to distributed substrate resistance

Thermal noise on channel resistance*:

inversionWeak

inversionStrong

Triode

=21

32

1

is a bias-dependent parametermchd gkTkTgfi 44)(2 ==

*Christian C. Enz and Yuhua Cheng, MOS transistor modeling for RF IC design, IEEE Journal of Solid-State Circuits, vol. 35, pp. 186 - 201, February 2000.


MOS transistor (2)

fWLC

KfV

oxnf =)(2

Flicker noise:

K process-dependent constantW channel widthL channel lengthCox unit gate capacitance

Input equivalent noise power spectral density:

)(2 fVnf

)(2 fId

)(2 fVni

fWLC

K

gkTfV

oxm

ni+=

14)(2 *Only channel thermal noise and flicker

noise are considered.


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MOS transistor (3)

ngng kTgi 42 =

Induced gate noise

- Thermal noise induced channel voltage fluctuation coupled to the gate through

gate oxide capacitance

- A gate noise current is induced

S

G

CgsGngi2ng

m

gs

ngg

Cg

5

22

Induced gate noise is only important at high frequency

At strong inversion


Operational amplifier

Noiseless

The noise sources in an operational amplifier can be modeled by An input equivalent voltage noise source

Two input equivalent current noise sources For MOS operational amplifier, the two current sources can be ignored.

-

+

A

in-2

in+2

vn2


44/464


A cascode amplifer is shown in the figure below. Calculate the total output noise power at dcand the input-referred noise. Ignore the flicker noise and assume that gm1 = gm2 = gm, rds1 =rds2 =rds, RL1.

v0

vin M1

M2

RL

Vbias

(1) Total noise power at DC

(i) Equivalent circuit with all noise sources

gm1vgs1

rds1v

no

rds2

gm2vgs2vn1

RL

- vgs2+

vn2 vn3

vn1

vn3

vn2

Example 1 Cascode amplifer (1)


(ii) Calculate Vno1 due to Vn1

gm1vn1

rds1 +vno1

-

rds2

gm2vgs2+vn1-

RL-vgs2+

( ) 12

1211

1

2

1 ===m

mindsm

n

gs

avg

grrg

v

vA

( ) 2122

1

2

1

2

1 nLmnvno vRgvAv ==

Output noise power due to vn1:

rin2

2

2

ds

Lxx

xmxr

Rivvgi

+=

222

22

1

1 mdsm

Lds

x

xin

grg

Rr

i

vr

++

==

DC gain from Vn1

to Vn01

:

ix

(RL


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(iii) Calculate Vno2due to Vn2

rds1

+vno2

-

rds2

gm2vgs2+vn2-

RL+v1-

+ vgs2 -

DC gain from Vn2 to Vno2 :

ds

ds

nogsm

rr

vvvgv

+= 1221

( )

dsm

non

gs

nogsdsmnngs

rg

vvv

vvrgvvvv

+

=

+==

2

2

21

22

2

222122

( )2212

1nogsdsm vvrgv +=

Substituting (E1) and (E2) into (E3),

L

ds

nogsmno R

rvvvgv

+=

1222 (E3)

22 n

ds

L

nov

r

Rv

( )2>>dsmrg

2

2

2

2

2

2

2

22

2 n

ds

L

n

n

no

nov

r

Rv

v

vv

==

ds

L

n

nov

r

R

v

vA =

2

22

Output noise power due to vn2

:

(E2)

(E1)



rds

+vno3

-

rds

gm2vgs2 +vn3-

RL

-vgs2+

dsm

no

gs

ds

ds

gsno

gsmgs

rg

vv

r

r

vvvgv

+=

++=

23

2

23

22

233

23

233

1gsL

ds

mno

ds

LnL

ds

gsno

gsmnno vRr

gvr

RvR

r

vvvgvv

+=

++=

(E4)

(E5)

(iv) Calculate Vno3due to Vn3

DC gain from Vn3 to Vno3 :

Substituting (E4) into (E5),

3

3

311

1

n

dsm

L

ds

m

ds

L

n

no

v

rgR

rg

r

R

vv

++

=

13

33 =

n

nov

v

vA

23

23 nno vv =

Output noise power due to vn2:



46/46


( )

( )

+=

+

+

+=

++=

++=

LmL

L

m

Lm

L

mds

LLm

n

n

non

n

non

n

no

nononono

RgkTR

kTRg

kTRg

kTRg

kTr

RRg

vv

vv

v

vv

v

v

vvvv

3

214

41

3

24

41

3

24

2

2

2

2

3

2

3

32

2

2

2

22

1

2

1

1

2

3

2

2

2

1

2

(2) The input-referred noise

( )mLm

L

Lm

n

V

n

nig

kTRg

kTR

Rg

v

A

vv

3

24

422

2

0

2

2

02 +==

(v) Total output noise power

Vno2 can actually be ignored.

From RL

From input transistor

Since 2/3gmRL >> 1, the noise from the input transistor is the dominant noise source.


1. Johns and Martin, Analog Integrated Circuit Design, JohnWiley & Sons, 1997.

2. Razavi, Desing of Analog CMOS integrated circuits, McGrawHill, 2001.

3. Paul Gray, et al. Analysis and design of analog integratedcircuits, Fourth Edition, John Wiley & Sons, 2001

4. Allen & Holberg, CMOS Analog Circuit Design, SecondEdition, Oxford University Press, 2002

5. Jacob Baker, CMOS Circuit design, layout, and simulation,2nd edition, Wiley, 2005.

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