Progress towards a Long Shaping-Time Readout for Silicon Strips
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Progress towards a Long Shaping-Time Readout for
Silicon Strips
Bruce SchummSCIPP & UC Santa CruzCornell LC Workshop
July 13-16, 2003
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The SD Tracker
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Tracker Performance
SD Detector burdened by material in five tracking layers (1.5% X0 per layer) at low and intermediate mo-mentum
Code: http://www.slac.stanford.edu/~schumm/lcdtrk.tar.gz
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Idea: Noise vs. Shaping Time
Min-i for 300m Si is about 24,000 electrons
Shaping (s) Length (cm) Noise (e-)
1 100 2200
1 200 3950
3 100 1250
3 200 2200
10 100 1000
10 200 1850
Agilent 0.5 m CMOS process (qualified by GLAST)
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The Gossamer TrackerIdeas:• Long ladders substantially limit electronics readout and associated support• Thin inner detector layers• Exploit duty cycle eliminate need for active cooling Competitive with gaseous
track-ing over full range of momentaAlso: forward region…
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TPC Material Burden
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Pursuing the Long-Shaping Idea
LOCAL GROUP
SCIPP/UCSC• Optimization of readout & sensors• Design & production of prototype ASIC• Development of prototype ladder; testing
Supported by 2-year, $95K grant from DOE Advanced Detector R&D Program
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PRC MeetingDESY, Hamburg, May 7 and 8,
2003
SilC: an International R&D Collaboration to develop Si-
tracking technologies for the LC
Aurore Savoy-Navarro, LPNHE-Universités de Paris 6&7/IN2P3-CNRS, France
on behalf of the SiLC Collaboration
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The SiLC CollaborationThe SiLC Collaboration
Brookhaven
Ann Arbor Wayne
Santa Cruz
Helsinki
Obninsk Karlsruhe
Paris
Prague Wien Geneve
Torino
Pisa
RomeBarcelonaValencia
Korean Universities
Seoul&Taegu
Tokyo
EuropeUSA
ASIASo far: 18 Institutes gathering over 90 people from Asia, Europe & USAMost of these teams are and/or have been collaborating.
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The SCIPP/UCSC Effort
Faculty/Senior
Alex GrilloHartmut Sadrozinski
Bruce SchummAbe Seiden
Post-Doc
Gavin Nesom
(half-time LC postdoc from
1999 program)
Student
Christian Flacco
(will do BaBar thesis)
Engineer: Ned Spencer (on SCIPP base program)
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SCIPP/UCSC Development Work
Characterize GLAST `cut-out’ detectors (8 channels with pitch of ~200 m) for prototype ladder
Detailed simulation of pulse development, electronics, and readout chain for optimization and to guide ASIC development (most of work so far)…
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Pulse Development Simulation
Long Shaping-Time Limit: strip sees signal if and only if hole is col- lected onto strip (no electrostatic coupling to neighboring strips)Charge Deposition: Landau distribution (SSSimSide; Gerry Lynch LBNL) in ~20 independent layers through thickness of deviceGeometry: Variable strip pitch, sensor thickness, orientation (2 dimen-sions) and track impact parameter
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Uncorrelated Sampling Check
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Carrier Diffusion
)(21
exp),(0
2
ttDr
trPq
Hole diffusion distribution given by
Offest t0 reflects instantaneous expansion of hole clouddue to space-charge repulsion. Diffusion constant given by
hq qkT
D
Reference: E. Belau et al., NIM 214, p253 (1983)
sec65.00 nt
h = hole mobility
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Other ConsiderationsLorentz Angle:
18 mrad per Tesla (holes)
Detector Noise:
From SPICE simulation, normalized to bench tests with GLAST electronics
Can Detector Operate with 167cm, 300 m thick Ladders?
• Pushing signal-to-noise limits• Large B-field spreads charge between strips• But no ballistic deficit (infinite shaping time)
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Result: S/N for 167cm Ladder
At shaping time of 3s; 0.5 m process qualified by GLAST
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Result: S/N for 132cm Ladder
At shaping time of 3s; 0.5 m process qualified by GLAST
132cm Ladder 300m Thick
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Not Yet Considered
• Inter-Strip Capacitance (under study; typically ~5% pulse sharing between neighboring channels)
• Leakage Current (small for low-radiation environment)
• Threshold Variation (typically want some headroom for this!) But overall, 3 s operating point seems quite feasible proceed to ASIC design!
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Analog Readout Scheme: Time-Over Threshold
(TOT)
i-min
thresh
e
e
nn
i-min
pulse
e
e
nn
r
TO
T/
/r
/te
etr
TOT given by differencebetween two solutions to
(RC-CR shaper)
Digitize with granularity /ndig
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Why Time-Over-Threshold?
4
2
6
10
8
TO
T/
101 1000100
Signal/Threshold = (/r)-1
100 x min-i
With TOT analog readout:
Live-time for 100x dynamic range is about 9
With = 3 s, this leads to a live-time of about 30 s, and a duty cycle of about 1/250
Sufficient for power-cycling!
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Single-Hit Resolution
Design performance assumes 7m single-hit resolution. What can we really expect?
• Implement nearest-neighbor clustering algorithm
• Digitize time-over-threshold response (0.1* more than adequate to avoid degradation)
• Explore use of second `readout threshold’ that is set lower than `triggering threshold’; major design implication
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RMS
Gaussian Fit
RMS
Gaussian Fit
Readout Threshold (Fraction of min-i)
Trigger Threshold167cm Ladder
132cm Ladder
Resolution With and Without Second (Readout)
Threshold
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Lifestyle Choices
Based on simulation results, ASIC design will incorporate:
• 3 s shaping-time for preamplifier
• Time-over-threshold analog treatment
• Dual-discriminator architecture
The design of this ASIC is now underway.
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But Can It Track Charged Particles?
1 100.1
Energy (MeV)
z (cm)
Photon Distributions at R = 25 cmSee Upcoming Talks!
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Current Activity
ASIC architecture established with pulse sim…
• ASIC design underway (chips in hand 1/1/04?)
• Further pulse sim studies (x-talk, leakage current, angled tracks, etc.
• Developing test stand (long ladder, readout, etc.)
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Where Next?
We’ve just begun the process of fleshing out the design of this `Gossamer Tracker’
In the 3-year R&D window, SCIPP needs to:
• Design and submit prototype ASIC (chips in hand 1/1/04?)• Demonstrate ability to read out long ladders • Demonstrate resolution and dynamic range • Demonstrate passive cooling (data transmission is an issue!)• Mount testbeam effort to verify simulation studies, refine chip• Probably second submission and second round of testing