CDA 3101 Spring 2016

Introduction to Computer Organization

Processor Organization

Datapath Design

16 February 2016

Review

• Construction of the ALU– Building blocks (digital design gates)

– Modular design• Multiplexor chooses operation

• All operations are performed in parallel

– Carry lookahead adder

• Computer arithmetic– Finite precision

– Laws of algebra do not always hold

– Integers: two’s complement representation

– Floating point: IEEE 754 standard

Overview• Computer organization (microarchitecture)• Processor organization

– Datapath

– Control

– Register file

• Processor implementation overview• Clocking methodologies• Sequential circuits

– Latches

– Registers

Review: Processor Performance

Program

Compiler

ISA

Microarchitecture

Hardware

CPU time = IC * CPI * Cycle time

Review: Computer Organization

I/O device

I/O device

I/O Subsystem

Processor Memory Subsystem

. . .

Address Bus

Data Bus

Control Bus

Review: The Processor

• Processor (CPU)– Active part of the computer– Does all the work

• Data manipulation • Decision-making

• Datapath– Hardware that perform all required operations– ALU + registers + internal buses– The brawn

• Control – Hardware which tells the datapath what needs to be done– The brain

Review: Processor Organization

ALU

Control Unit

Registers

Control signals

Data values

Control signals

Control bus signals

Data values (results)

Data values (operands)

Address bus Data bus

Implementation of MIPS• ISA determines many aspects of implementation• Implementation strategies affect clock rate and CPI• MIPS subset to illustrate implementation

– Memory-reference instructions• Load word (lw)• Save word (sw)

– Integer arithmetic and logical instructions• add, sub, and, or, and slt

– Branch instructions• Branch if equal (beq)• Jump (j)

Implementation OverviewPC

Instructionmemory

+4

rtrs

rd

Registers ALUData

memory

immData

Data

Address

Controller

Opcode, funct

Address

Instruction

° Datapath is based on register transfers required to execute instructions

° Control causes the right transfers to happen

Logic and Clocking

• Combinational elements– Outputs depend only on current inputs– Example: ALU (adders, multiplexers, shifters)

• Sequential elements– Contain state– Output depend on input and state– Inputs: data values and clock– Memory, registers

• Asserted signal: logically high

Clocking Methodology

• Determines the order of (gate) events– Defines when signals can be read/written

• Clock: circuit that emits a series of pulses

clock

Timing diagrams

C Asymmetric clock

clock cycletime

(C1 AND C2)

Rising edge Falling edge

Edge-Triggered Clocking

State

element

1

State

element

2

Combinational logic

State

element Combinational

logic

• Either the rising edge or the falling edge is active

• State changes only on the active clock edge

clock

Review: NOR SR Latch

State 0 State 1

Inputs S - set

R - resetOutputs: Q and Q

Review: Clocked SR Latch

Review: Clocked D Latch

D

C

Q

Output is initially deasserted

Review: D flip-flop

D

C

Q

C

D QD

latchC

D QD

latch

C

D Q

QQ

Setup time

hold time

Falling-edge trigger, output is initially deasserted

Register File

Read ports

Write port

Register File Read Ports

Register File Write Ports

Core Topic –Datapath Design

• Datapath implements fetch-decode-execute

• Design Methodology

Determine instruction classes and formats Build datapath sections for each instr.fmt.Compose sections to yield MIPS datapath

• Challenge #1: What are instruction classes?

• Challenge #2: What components are useful?

Simple Datapath Components• Memory stores the instruction• PC address of current instruction• ALU executes current instruction

PC Read Addr

Instruction

Instruction Memory

4+

fetch

Increment program counter

R-format Datapath

• Format: opcode r1, r2, r3

Result

Zero

ALU

Read Data 1

Read Data 2

Read Reg 1

Read Reg 2

Write Register

Write Data

Register Write

ALU op

Register File 3

Instruction

Load/Store Datapath Issues

• lw $t1, offset($t2)– Memory at base $t2 with offset – lw: Read memory, write into register $t1 – sw: Read from register $t, write to memory

• Address computation – ISA says:– Sign-extend 16-bit offset to 32-bit signed value

• Hardware: Data memory for read/write

Load/Store Datapath Components

Address

Read data

Write data

MemWrite

MemRead

Data Memory

Sign Extend

16 32

1101 … 0011

1111 1111 1111 1111 1101 … 0011

Load/Store Datapath Actions

1. Register Access Register File-- Instruction/Data/Address Fetch

2. Memory Address Calculation ALU-- Address Decode

3. Read/Write from Memory Data Memory4. Write into Register File Register File

-- Load/Store Instruction Execute

Load/Store Datapath

Fetch Decode Execute

Branch Datapath Issues

• beq $t1, $t2, offset– Two registers ($t1, $t2) compared for equality– 16-bit offset to compute branch target address

• Branch target address – ISA says:– Add sign-extended offset to PC– Base address is instruction after branch (PC+4)– Shift offset left 2 bits => word offset

• Jump to target– Replace lower 26 bits of PC with lower 26 bits

of instruction shifted left 2 bits

Branch Datapath Actions

1. Register Access Register File-- Instruction/Data Fetch

2. Evaluate Branch Condition ALU #13. Calculate Branch Target ALU #2

-- Branch Computation – similar to Decode

4. Jump to Branch Target Control Logic-- Branch Instruction Execute

Branch Datapath

Fetch Decode Execute

Delayed Branch (MIPS)

• MIPS ISA: Branches always delayed

- Instr. Ib following branch is always executed- condition = false => Normal branch- condition = true => Ib executed

Why bother?

1. Improves efficiency of pipelining

2. Branch not taken (false condition) can be common case

Conclusions• MIPS ISA: Three instruction formats (R,I,J)

• Datapath designed for each instruction format

• Datapath Components:

-- R-format: ALU, Register File

-- I-format: Sign Extender, Data Memory

-- J-format: ALU #2 for target address comp’n.

Trick: Delayed branch to make pipeline efficient

Think: Weekend !

Anticipate the Exam Weekend!!

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