Process Int Exam UH Spring 2015

Midterm Exam ELEE7366 April 3 rd , take-home, deadline is Monday, April 6 th , 10:30 am (hard-copy). Please limit the exam (your writing) to 6 pp. Please read the questions carefully to include the main aspects of the problems. Answer concisely (outline format is ok) but thoroughly. Page limit is 6 total. The writing style is not important but clarity (including handwriting) is. Please open the ITRS tables from the Blackboard. Use only Front End Processes (FEP2, FEP3, and FEP11-thermal i ) and Process Integration (PIDS2 – high performance and PIDS3-low operating power) for bulk CMOS devices (no SOI, MG, memories etc.) and related notes. You will see that there are no bulk Si devices beyond 2017. Explain why we are reaching the limits in design and fabrication of MOS transistors. Important issues here include: known constrains and solutions to these constrains in the high performance and low power devices; those are related to saturation drive current, off-state current, and speed and power. Also related are EOT, poly-Si gate electrodes vs. metal gates, threshold voltage tuning, channel doping concentrations, doping of the S/D regions and contact formation, gate capacitance, and gate leakage etc. Please be very clear in your explanations why we cannot continue with traditional scaling. Why new solutions and changes in technology (work on those) stop working as shown in these tables.

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Transcript of Process Int Exam UH Spring 2015

Midterm ExamELEE7366

April 3rd, take-home, deadline is Monday, April 6th, 10:30 am (hard-copy). Please limit the exam (your writing) to 6 pp.

Please read the questions carefully to include the main aspects of the problems. Answer concisely (outline format is ok) but thoroughly. Page limit is 6 total. The writing style is not important but clarity (including handwriting) is.

Please open the ITRS tables from the Blackboard. Use only Front End Processes (FEP2, FEP3, and FEP11-thermali) and Process Integration (PIDS2 – high performance and PIDS3-low operating power) for bulk CMOS devices (no SOI, MG, memories etc.) and related notes. You will see that there are no bulk Si devices beyond 2017.

Explain why we are reaching the limits in design and fabrication of MOS transistors.

Important issues here include: known constrains and solutions to these constrains in the high performance and low power devices; those are related to saturation drive current, off-state current, and speed and power. Also related are EOT, poly-Si gate electrodes vs. metal gates, threshold voltage tuning, channel doping concentrations, doping of the S/D regions and contact formation, gate capacitance, and gate leakage etc.

Please be very clear in your explanations why we cannot continue with traditional scaling. Why new solutions and changes in technology (work on those) stop working as shown in these tables.