Proceedings i Ber Chip 2012

IBERCHIP 2012 PROCEEDINGS

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IBERCHIP 2012 Program Co-Chairs Message

On behalf of the Organizing and Program Committees, the General and Program Chairs welcome all the participants to the XVIII IBERCHIP Workshop. This year, the Workshop will continue with the tradition of being held in a beautiful Latin American venue: Playa del Carmen, Mexico.

This edition of the IBERCHIP Workshop will be held in parallel with the 3rd Latin American Symposium on Circuits and Systems (LASCAS 2012), since both events provide a forum for the presentation and discussion of the advances in the analysis, modeling, characterization, design, implementation and application of microelectronic circuits and systems in Iberoamerica. For the case of IBERCHIP, the Technical Program includes five sessions of oral presentations and an open forum for one-to-one discussions on contributions presented as posters. In this regard, twenty-seven contributions are included as oral presentations and thirteen as posters.

The topics included in the Technical Program of IBERCHIP cover different disciplines within the field of electronics, ranging from FPGAs and Signal Processing to Semiconductor Materials, Circuits and Devices. We were glad of having received excellent papers from several Latin American countries, Spain and Japan, which allows us to reach one of the key objectives of this workshop: bringing together researchers, students, and practicing engineers from industry, universities, and government laboratories from all over Iberoamerica to address the current and future trends of microelectronics.

A further objective of the workshop is the encouragement of informal interaction among the participants during the time between sessions and evening forum. In our experience, such interactions result in productive collaborations and lead to significant inter-institutional approaching for the advancement of science and technology in our countries.

In addition, within the frame of IIBERCHIP and LASCAS, six keynote speeches will be given by: Prof. Pedro Julin (Universidad Nacional del Sur, Argentina), Dr. Maynard Falconer (Intel Labs, USA), Dr. Alvaro Maury (SILTERRA, Malaysia), Prof. Mounir Boukadoum (Universit du Qubec Montral, Canada), Prof. Maciej J. Ogorzalek (Jagiellonian University, Krakow, Poland), and Dr. Fernando Guarn (IBM Microelectronics Semiconductor Research, USA). We are glad to have confirmed the participation of these internationally renowned specialists in the field of Electronics.

Last, but not least, the Steering Committee for the XVIII IBERCHIP Workshop wishes to thank the invited speakers, authors, and the members of the Technical Program Committee for their contributions in allowing to prepare this year's exciting technical program. The sponsorship of INAOE, IEEE and ISTEC is also acknowledged and greatly appreciated as well as all the unrelenting support provided by INAOE's staff. Again, be all welcome to Mexico and enjoy the Workshop! Roberto Murphy Reydezel Torres Jos Luis Huertas INAOE, Mexico INAOE, Mexico Universidad de Sevilla, Spain

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Table of Contents Tatsuya Maruyama and Alberto Palacios Pawlovsky. A Study of Methods to Improve an Immune Algorithm for Searching for the Pair of Inputs that Cause the Maximum Number of Switching Gates in a Combinational Circuit ------------------------ 1 Laurentiu Acasandrei and Angel Barriga. Implementacin sobre FPGA de un sistema de deteccin de caras basado en LEON3 ------------------------------------------------ 6 Jess Balosa, Francisco Jos Crespo and Angel Barriga. Sistema empotrado de reconocimiento de voz sobre FPGA ------------------------------------------------------------ 10 Juan Nez, Mara J. Avedillo and Jos M. Quintana. Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits -------------------------------------------------------------- 14 Romulo Volpato, Tales Pimenta, Filipe Ramos, Michel Santana and Paulo Crepaldi. Prediction of Energy Transfer in Implantable Devices ----------------------------- 18 David Cabral, Leonardo Zoccal, Paulo Crepaldi and Tales Pimenta. Schottky Barrier Diodes SBD in Standard CMOS Process ---------------------------------------------- 21 Joel Molina, Rafael Ortega, Wilfrido Calleja, Pedro Rosales, Carlos Zuniga and Alfonso Torres. Performance of a MOHOS-type Memory by Using Different Tunneling Oxide Thickness. --------------------------------------------------------------- 26 Elisa Calvo Gallego, Piedad Brox Jimnez and Santiago Snchez-Solano. Un algoritmo en tiempo real para etiquetado de componentes conectados en imgenes --------------------------------------------------------------------------------------------------- 30 Alexander Zemliak, Antonio Michua and Tatiana Markina. Behavior of Lyapunov Function for Different Strategies of the Circuit Optimization Problem ---------------------------------------------------------------------------------------------------- 36 Adriana Aparecida Dos Santos Izidoro, Eduardo Souza Dias, Fernando A Cardoso and Tales Cleber Pimenta. Digital Multiplexer of an EEG Signal Acquisition System -------------------------------------------------------------------------------------- 40 Diego Brengi, Salvador Tropea and Christian Huy. S3Proto-mini: Tarjeta de Hardware Libre con FPGA de encapsulado BGA ------------------------------------------------ 43 Fernando Urbano, Vladimir Trujillo and Jaime Velasco. Implementacin Hardware de un Multiplicador Serial Basado en Bases Normales sobre GF(2^163) ------------------------------------------------------------------------------------------------- 47

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Carlos Torres-Torres. Electromagnetic blooming by vectorial laser irradiation in semiconductive nanostructures ------------------------------------------------------------------- 52 Andres Marquez, Wilfrido Moreno and Ramiro Jordan. Experiences Teaching a Rapid System Prototyping Class ------------------------------------------------------------------ 55 Mauricio Huixtlaca-Quintana, Jose Miguel Rocha-Perez, Alejandro Diaz-Sanchez and Carlos Muiz-Montero. Circuito para la Extraccin de Raz Fraccional Usando Transistores en Inversin Dbil --------------------------------------------- 60 Adalbery Rodrigues Castro, Lilian Coelho De Freitas, Claudomir Cardoso and Aldebaro Klautau. Classificao de Modulao em Rdio Cognitivo: Uma Implementao em FPGA ---------------------------------------------------------------------- 64 Duarte Oliveira, Luiz Ferreira, Lester Faria and No Alles. Asynchronous Control in CMOS Technology for Synchronous FSMs Partitioned with One-Hot Encoding ---------------------------------------------------------------------------------------------- 70 Duarte Oliveira, No Alles, Lester Faria, Diego Bompean, Thiago Curtinhas and Luiz Ferreira. Synthesis of Asynchronous Digital Systems of High Performance using Simpler Approach -------------------------------------------------------------- 74 Gracieli Posser, Guilherme Flach, Gustavo Wilke and Ricardo Reis. Dimensionamento de Portas Lgicas e de Transistores Minimizando Atraso e rea --------------------------------------------------------------------------------------------------------- 80 Walter Enrique Calienes Bartra, Fernanda Lima Kastensmidt and Ricardo Reis. Simulacin de Fallas SET en un Oscilador Controlado por Voltaje ------------------ 86 Ma. Del Roco De Jess, Isaac Esa Jimnez, Luis Hernndez and Mnico Linares. Implementacin De Una Celda CNN Digital en FPGA para la Aplicacin en Deteccin de Bordes ----------------------------------------------------------------- 92 Jones Yudi Mori, Camilo Snchez-Ferreira and Carlos Humberto Llanos. Real-Time Image Processing based on Neighborhood Operations using FPGA ------------------------------------------------------------------------------------------------------- 97 Hernando Gonzlez Acevedo. Diseo de controladores difusos utilizando algoritmos genticos ----------------------------------------------------------------------------------- 103 Anelise Kologeski, Caroline Concatto, Fernanda Kastensmidt and Luigi Carro. Combinao de Estratgias para Lidar com Falhas Permanentes nas Interconexes de uma Rede Intra-Chip ----------------------------------------------------------- 109

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Thiago Brito Bezerra, Antonio Petraglia and Sebastian Yuri Cavalcante Catunda. Transistor Level Design of a Switched Capacitor Integrating ADC with Programmable Input Range and Resolution ----------------------------------------------- 115 Lucas L. Gambarra, Jos A. G. Lima, Hamilton S. Silva, Leonardo V. Batista and Daniel S. Marques. Otimizao do algoritmo Non-local means utilizando uma implementao em FPGA ---------------------------------------------------------------------- 121 Marcio Bender Machado, Marcio Cherem Schneider and Alfredo Arnaud. A Battery Charge Monitor Topology for Implantable Medical Devices ----------------------- 126 Gabriela A Rodrguez, Arturo Sarmiento and Edmundo Gutirrez. A Schrdinger-Poisson CAD tool for calculation of tunneling through different gate-oxide potential profiles -------------------------------------------------------------------------- 131 Tania Mara Ferla, Guilherme Flach and Ricardo Reis. Uma Ferramenta Educacional para o Ensino de Simulated Annealing e Posicionamento ------------------ 135 Georgina Rosas, Roberto Murphy and Wilfrido Moreno. Novel Fabrication Tecniques for RF-MEMS Devices ------------------------------------------------------------------ 140 Fabio Pereira, Edward David and Fernando Yokota. Algoritmo SHA-3 Keccak em Smart Card: Implementao e Desempenho ----------------------------------------------- 145 Germn lvarez-Botero, Roberto Murphy and Reydezel Torres. Accurate Modeling to Characterize the Distributed Substrate Effects in SiGe HBTs --------------- 151 Fabin Zrate-Rincn, Germn lvarez-Botero, Reydezel Torres-Torres and Roberto Murphy-Arteaga. Extraction Methodology of the Substrate Parasitic Network of an RF-MOSFET with Separate Substrate DC Connection -------------------- 155 Roberto Castaeda-Sheissa, Hctor Vzquez-Leal, Ahmet Yildirim, Uriel Filobello-Nio, Arturo Sarmiento-Reyes and Luis Hernndez-Martnez. Mtodo modificado de hiperesferas aplicado a homotopas biparamtricas: simulacin de circuitos con transistores bipolares ---------------------------------------------- 160 Gerson Scartezzini and Ricardo Reis. Dissipao de potncia em Redes de Transistores versus Clulas Padro --------------------------------------------------------------- 164 Adriana Carolina Sanabria Borbon, Jaime Vitola Oyaga, Cesar Pedraza Bonilla and Martha Johanna Sepulveda. Algoritmo rpido para la bsqueda de audio por contenido -------------------------------------------------------------------------------- 169 Svetlana Sejas and Reydezel Torres-Torres. Deembedding On-Wafer S-parameters: Is a One-Step Procedure Enough? ------------------------------------------------ 174

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Salvador Antonio Arroyo Daz, Alejandro Diaz Sanchez and Apolo Zeus Escudero Uribe. Architecture for myolectric features extraction by H.O.S. of four sMES channels ------------------------------------------------------------------------------------ 179 Salvador Antonio Arroyo Daz and Karina Rosas Paleta. Control de Robot Mvil Basado en FPGA -------------------------------------------------------------------------------- 183 Victor H. Vega G. and Edmundo Gutierrez. Multiport Analysis of Two-Dimensional Nanosystems in a Magnetic Field Based on the NEGF Formalism ------------------------------------------------------------------------------------------------- 188

Proceedings of the XVIII International IBERCHIP Workshop

Playa del Carmen, Mexico, February 29-March 2, 2012 1 ISSN 977-2177-128009

Implementacin sobre FPGA de un sistema de deteccin de caras basado en LEON3

Laurentiu Acasandrei, Angel Barriga IMSE-CNM-CSIC/Univ. Sevilla

Sevilla, Espaa {laurentiu,barriga}@imse-cnm.csic.es

AbstractEn esta comunicacin se presenta un sistema empotrado de deteccin de caras sobre FPGA. Con objeto de disponer de aceleracin en el proceso de deteccin de caras se propone un sistema basado en tcnicas de codiseo hardware-software. Se detalla el mecanismo de aceleracin en la deteccin de caras. Tambin se describe la implementacin de un mdulo IP que permite la aceleracin hardware as como los resultados obtenidos.

I. INTRODUCCIN La deteccin de caras constituye una tarea importante en

aplicaciones biomtricas y de interaccin hombre-mquina. Debido a la complejidad de los algoritmos de deteccin de caras se requiere una gran cantidad de recursos de computacin y memoria. Por lo tanto las implementaciones software de los algoritmos de deteccin resultan poco eficientes cuando deben ejecutarse sobre sistemas SoC (System on Chip) que requieran alta velocidad de procesado, pocos recursos y bajo consumo de potencia. En estos casos el uso de tcnicas de codiseo hardware-software pueden aplicarse para el desarrollo de aceleradores hardware para las partes que requieren de mayor consumo computacional en los algoritmos de deteccin.

El principal xito de un algoritmo de deteccin de caras consiste en conseguir un balance adecuado entre la precisin en la deteccin (robustez) y una operacin eficiente (coste computacional). Los detectores heursticos o basados en conocimiento, tales como las tcnicas basadas en el color de la piel y las tcnicas basadas en plantillas, utilizan el conocimiento directo de las caras y a veces dan lugar a mejores prestaciones. Sin embargo estas tcnicas son poco robustas respecto a variaciones en las caras y a interferencias del entorno (como es el caso de los cambios de iluminacin). Por otro lado los mtodos estadsticos o los basados en aprendizaje, como las redes neuronales o los detectores SVM, hacen uso de algoritmos de clasificacin y dan lugar a mejores prestaciones a la hora de discriminar entre patrones de caras y de no-caras. Sin embargo estos algoritmos basados en aprendizaje requieren una alta complejidad de procesado por lo que resultan muy costosos para aplicaciones en sistemas empotrados.

Recientemente se han realizado algunas propuestas de implementaciones hardware de sistemas de deteccin de caras. As en [1] se presenta un sistema dedicado sobre FPGA. Dicho

sistema recibe la imagen de una cmara y la almacena en la memoria interna del FPGA. Otras realizaciones estn basadas en GPUs. En [2] se propone acelerar la deteccin de caras distribuyendo el clculo entre 4 GPUs. Esta comunicacin presenta el diseo de un sistema empotrado de deteccin de caras basado en el procesador LEON3. El sistema de deteccin implementa el algoritmo de deteccin de objetos de Viola-Jones.

II. ALGORITMO DE DETECCIN DE CARAS DE VIOLA-JONES El algoritmo de Viola-Jones [3] permite procesar imgenes

de manera muy rpida y consigue una razn de deteccin alta. La velocidad en el procesado se debe a tres elementos claves de dicho algoritmo. En primer lugar la imagen se transforma en una imagen integral lo que permite calcular el rea de rectngulos en un tiempo constante como se muestra en la figura 1. Dicha imagen integral consiste en acumular para cada pixel el valor de los pxeles previos:

yyxx

yxiyxii','

)','(),( (1)

En segundo lugar se usa un clasificador simple y eficiente construido mediante el algoritmo de aprendizaje AdaBoost [4]. Esto permite seleccionar un nmero reducido de caractersticas visuales de un conjunto muy alto de caractersticas potenciales. Ejemplos de las caractersticas tipo Haar usados por el clasificador se ilustran en la figura 2. Consisten en reas rectangulares cuyo procesado requiere operaciones aritmticas simples. En el clculo se aplica un umbral a las sumas y diferencias de las regiones rectangulares de la imagen (las regiones oscuras se restan de la regiones blancas).

Fig. 1. La suma de pxeles del rectangulo D se calcula mediante la siguiente operacin en la imagen integral: ii4+ii1-(ii2+ii3)

En tercer lugar el clasificador est constituido combinando clasificadores sencillos en cascada (figura 3). La tcnica Viola-Jones se basa en explorar la imagen mediante una ventana en busca de caractersticas. Dicha ventana se escala con objeto de

A B

D C ii1 ii2

ii3 ii4



localizar caras de diferentes tamaos. Las primeras etapas consisten en detectores simples, muy rpidos y de bajo coste. Esto permite eliminar aquellas ventanas que no contienen caras y deja pasar las que son candidatas a tener caras. Los siguientes detectores aumentan en complejidad con objeto de realizar un anlisis ms detallado en un conjunto menor de las zonas de inters. Las caras son detectadas en el final de la cascada.

Fig. 2. Ejemplos de caractersticas de tipo Haar.

Fig. 3. Arquitectura de detectores en cascada

III. CODISEO HARDWARE-SOFTWARE El algoritmo de deteccin de objetos de Viola-Jones

requiere un nmero muy alto de recursos de computacin y un alto ancho de banda de memoria. Esto constituye un impedimento a la hora de construir sistemas de deteccin de objetos en tiempo real. Con objeto de disponer de aceleracin en el proceso de deteccin de caras se propone un sistema basado en tcnicas de codiseo hardware-software. La figura 4 muestra un esquema de dicho sistema. Aquellas partes del algoritmo de deteccin que requieren flexibilidad son implementadas en software mientras que las partes crticas son implementadas como acelerador hardware.

Fig. 4. Sistema hardware-software para deteccin de caras

A. Aceleracin del algoritmo de Viola-Jones La tcnica de deteccin de caras de Viola-Jones ha sido

implementada en la librera OpenCV (Open Source Computer Vision) [5]. Esta librera contiene funciones para visin artificial en tiempo real. Teniendo en cuenta que la librera contiene una aplicacin para deteccin de caras en video, se decidi utilizar los archivos fuente de la aplicacin como punto de partida en el desarrollo del sistema de deteccin de vdeo para sistemas empotrados basados en LEON3.

Las caractersticas tipo Haar de la distribucin OpenCV han sido entrenadas para aplicarse a ventanas rectangulares de 20x20 pxeles. Para otras dimensiones de ventanas las caractersticas tipo Haar deben ser escaladas. El sistema de deteccin de caras consiste en 22 detectores en cascada que contienen 2135 caractersticas tipo Haar.

La aplicacin de deteccin de caras de OpenCV se implementa en dos modos de operacin diferentes (figura 5):

Modo 1: escalando la imagen. En este modo la imagen es escalada mediante interpolacin hasta que se alcanza un tamao mnimo predefinido. En cada momento del escalado se necesitan dos imgenes integrales (normal=x y cuadrtica=x2) para calcular la varianza. La ventana de bsqueda tiene un tamao fijo en todo el proceso de deteccin.

Modo 2: escalando los clasificadores. En este modo las imgenes integrales (normal=x y cuadrtica=x2) necesarias para calcular la normalizacin de la varianza ( 222

HWx

HWx ) se obtienen una sola vez de la imagen

original. Sin embargo las caractersticas tipo Haar de los clasificadores son escaladas progresivamente hasta que sus dimensiones son similares a las de la imagen original. La ventana de bsqueda tiene, por lo tanto, dimensin variable durante el proceso de deteccin.

En los dos modos los componentes de las caractersticas de tipo Haar (pesos y dimensiones) son escalados progresivamente con las dimensiones de la ventana de bsqueda. Esto significa que para una ventana de bsqueda de dimensin WxH el peso de cada rectngulo de la caracterstica de tipo Haar son escalados por el valor WxH. En la ventana de bsqueda el clculo de la caracterstica de tipo Haar se realiza mediante:

31I

scaledII

Sum WeightAreaeHaarFeatur (2)

Area representa la suma de todos los pxeles dentro de un rectngulo e I=1,2, 3 representa el nmero de rectngulos de la caracterstica de tipo Haar. Con objeto de determinar el valor del peso para la suma cada HaarFeatureSum es comparado con el umbral normalizado de la correspondiente caracterstica de tipo Haar:

norm

JSumJ

WeightJ

normJ

SumJ

WeightJ

ThreseHaarFeaturifStageStageSumThreseHaarFeaturifStageStageSum

StageSum,,

1

2

(3)

donde J=[12135] representa el ndice de la caracterstica de tipo Haar y ThresJnorm= ThresJHaarFeature, ( es la desviacin estndar de la ventana de bsqueda).

D1 D2 D3 DN



Si no se escalan los pesos de las caractersticas de tipo de Haar y se realiza el clculo de la varianza mediante la expresin )22(2 xxHWadjusted entonces se reduce tanto el nmero de operaciones aritmticas (divisin, multiplicacin) como los accesos a memoria. Esto hace que el algoritmo sea ms rpido [6].

B. Mdulo IP para aceleracin hardware Tras un anlisis de la aplicacin de deteccin de caras se ha

encontrado que el cuello de botella del software reside en la gran cantidad de accesos de lectura a memoria, las operaciones de multiplicacin y raz cuadrada, que son necesarias para la evaluacin de las ventanas de bsqueda. As para detectar una cara en una imagen se requiere evaluar cientos de miles de ventanas de bsqueda y ello representa el mayor consumo del tiempo por parte de la aplicacin. Por ello se ha decidi acelerar la evaluacin de las ventanas de bsqueda mediante un mdulo IP hardware [7].

Fig. 5. Algoritmo propuesto para la aceleracin en la deteccin de caras

Para mantener un alto grado de flexibilidad y poder compartir los recursos hardware con el resto del sistema basado en LEON3 se ha decidido que el mdulo IP IMSE_OBJECT_DETECTION tenga dos modos de operacin [9]: el modo libre en el cual los recursos del IP (multiplicador, memoria, etc) pueden ser usados por LEON3 para implementar otra funcionalidad y el modo de deteccin de caras. El mdulo IP opera con el reloj del sistema (80 MHz).

Como se ha mencionado anteriormente el mdulo IP implementa el algoritmo de ventanas de bsqueda. La aplicacin software es la encargada de almacenar las caractersticas de tipo Haar en la memoria del mdulo. Tambin se encarga de establecer los valores de los registros de configuracin (escala, coordenadas x-y, dimensin de la imagen, etc.). Cuando la aplicacin software realiza el comando de inicio el procedimiento de deteccin de caras es

controlado por el componente Imse_stage_evaluator_unit (figura 6). Esta unidad es el motor del sistema de aceleracin en la deteccin de caras. Al finalizar el proceso de deteccin el componente indica si hay caras actualizando el registro de estado con el resultado obtenido y se genera una interrupcin. La unidad contiene varias unidades de control con objeto de soportar las diferentes latencias en los accesos a la memoria del sistema (externa al mdulo IP). Junto a las diferentes mquinas de estado que constituyen las unidades de control este componente tambin contiene mdulos especializados: el mdulo que calcula el rea de los rectngulos en la imagen integral usando solo los datos de las esquinas (como se explica en la figura 1), un modulo pipeline para el escalado y clculo de la direccin de las caractersticas de tipo Haar, un circuito que realiza la raz cuadrada entera de nmeros de 64 bits (tiene una latencia de 16 ciclos de reloj) y un multiplicador de nmeros con signo de 41x33 bits.

Fig. 6.Diagrama de bloques del mdulo IP IMSE_OBJECT_DETECTION

El mdulo IP tiene una memoria compartida basada en una RAM de doble puerto con interfaz AHB. Dicha memoria sirve para almacenar las caractersticas de tipo Haar. LEON3 puede usarla como memoria adicional en el modo de operacin libre.

IV. RESULTADOS El sistema de deteccin de caras propuesto trabaja con

imgenes (en color o gris) con una resolucin inferior a 1024x1024 pxeles. Usa la cascada completa de clasificadores para caras frontales de OpenCV y puede almacenar en la memoria interna aproximadamente 2730 clasificadores de tipo Haar. Podra trabajar con mas clasificadores pero estos se tendran que almacenar en la memoria de programa para ser cargados en la memoria interna cuando se requieran.

El sistema ha sido implementado en una FPGA de Xilinx XC5VLX50. El sistema de deteccin basado en LEON3 completo ocupa 6,435 slices (89% del dispositivo) y contiene



10,962 flip-flops (38% del dispositivo). El consumo de potencia estimado (medido con Xpower Analyzer de Xilinx) ha sido de 603 mW. El componente de mayor consumo es el controlador de memoria DDR2 (216 mW), la interfaz DVI (136 mW) y los generadores de reloj. El procesador LEON3 consume 32.39 mW. Por su parte el modulo IP IMSE_OBJECT_DETECTION, que requiere ms flip-flops y tiene aproximadamente la misma cantidad de lgica que LEON3, consume 6 veces menos (5.39 mW) que el procesador.

Con objeto de medir las prestaciones del sistema empotrado de deteccin de caras propuesto se han comparado tres implementaciones:

El software OpenCV portado al sistema empotrado. La versin software acelerada del sistema software portado

al sistema empotrado. La versin acelerada hardware-software basada en el

mdulo IP. Las mtricas empleadas para medir las prestaciones han

sido el tiempo de ejecucin y el nmero de ventanas de bsquedas aplicadas. Para las dos primeras implementaciones (software) se han considerado los dos modos de deteccin (modo 1 y 2). En el caso de la implementacin hardware-software solo opera en el modo 2. En cada modo se han considerado 4 tipos de parmetros (setup 1 al 4) para el tamao de la ventana de bsqueda mnima (S) y el paso de escala (step): 1) S=30x30, step=1.2; 2) S=30x30, step=1.1; 3) S=20x20, step=1.2; 4) S=20x20, step=1.1.

En la figura 7 se muestran los resultados obtenidos. Puede observarse que la aplicacin software que acelera la deteccin de caras es 3-4 veces ms rpida que la aplicacin portada OpenCV en ambos modos. Usando el mdulo IP de aceleracin hardware se consiguen velocidades 7-9 veces mayores.

Fig. 7. Tiempos de deteccin de imagenes VGA, a) modo de escalado de la

imagen, b) modo de escalado de las caractersticas de tipo Haar

V. CONCLUSIONES Se ha descrito el diseo e implementacin de un sistema de

deteccin de caras basado en una estrategia hardware-software sobre FPGA. Para ello se ha presentado el mecanismo de aceleracin propuesto y el diseo de un mdulo IP para el procesador LEON3 que permite realizar la aceleracin hardware. Los resultado de test del sistema muestran unos Buenos tiempos de respuesta lo que hace que el sistema sea adecuado en aplicaciones biomtricas de tiempo real.

AGRADECIMIENTOS Este trabajo ha sido soportado parcialmente por el proyecto

financiado por la Unin Europea MOBY-DIC Project FP7-IST-248858, por el Ministerio de Ciencia y Tecnologa bajo el proyecto TEC2008-04920 y TEC2011-24319 con cofinanciacin FEDER y por la Junta de Andaluca bajo el proyecto P08-TIC-03674.

REFERENCIAS [1] J. Cho, S. Mirzaei, J. Oberg, and R. Kastner, Fgpa-based face detection

system using haar classifiers, in FPGA 09: Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays. New York, NY, USA: ACM, 2009, pp. 103112.

[2] D. Hefenbrock, J. Oberg, N.T.N. Thanh, R. Kastner, S.B. Baden, Accelerating Viola-Jones Face Detection to FPGA-Level using GPUs, Proc. IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010.

[3] P. Viola, M.J. Jones, Robust Real-Time Face Detection, International Journal of Computer Vision, v.57 n.2, pp.137-154, May 2004.

[4] R.E. Schapire, Y. Freund, P. Bartlett, W.S. Lee, Boosting the Margin: A New Explanation for the Effectiveness of Voting Methods, The Annals of Statistics, pp. 1651-1686, 1998.

[5] OpenCV: http://sourceforge.net/projects/opencvlibrary/ [6] L. Acasandrei, A. Barriga: Accelerating Viola-Jones Face Detection for

Embedded and SoC Environments, Fifth ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC2011), Ghent, Belgium, Aug. 2011.

[7] L. Acasandrei: Embedded Face Detection System Implemented on LEON3 Microprocessor, Master Thesis, Univ. Seville, 2011.

a) b)



Sistema empotrado de reconocimiento de voz sobre FPGA

Jess Balosa, Francisco J. Crespo, Angel Barriga IMSE-CNM-CSIC/Univ. Sevilla

Sevilla, Espaa [email protected]

AbstractEn esta comunicacin se presenta un sistema empotrado sobre FPGA de reconocimiento de voz que aplica el algoritmo LPC (Linear Predictive Coding). El sistema est basado en el procesador MicroBlaze de Xilinx. Se describe el desarrollo del sistema desde la implementacin del controlador del cdec de audio (tanto el hardware como el desarrollo de los drivers) hasta la adaptacin del algoritmo LPC a los requerimientos de la arquitectura hardware.

I. INTRODUCCIN Los sistemas automticos de reconocimiento de voz (ASR,

Automatic Speech Recognition) han experimentado un notable avance en las ltimas dcadas. Sin embargo la mayora de las aplicaciones de los sistemas ASR estn basadas en realizaciones software sobre ordenadores. El desarrollo de aplicaciones sobre sistemas empotrados hace necesaria la adaptacin de los sistemas ASR. El objetivo de esta comunicacin consiste en presentar la puesta a punto de un entorno de desarrollo para aplicaciones ASR empotradas. Esto supone la especificacin de la plataforma de desarrollo y la adaptacin de tcnicas ASR para dicha plataforma. Por lo tanto en esta comunicacin se va a presentar por un lado la adaptacin de una plataforma hardware reconfigurable basada en FPGA que permita configurar diferentes arquitecturas de sistemas empotrados y, por otro lado, el desarrollo de un algoritmo de reconocimiento de voz sobre dicha plataforma hardware.

Se ha seleccionado como plataforma de desarrollo una placa basada en FPGA de Xilinx ML505 que, entre otros componentes, dispone de entradas y salidas de audio, cdec de audio, dispositivos de comunicacin, memorias (SRAM, DDR2, CompactFlash), etc. Se ha desarrollado un controlador de audio como perifrico del procesador MicroBlaze.

El desarrollo del algoritmo de reconocimiento de voz ha requerido su adaptacin a los requerimientos del sistema empotrado (recursos reducidos de memoria, procesador sin unidad de manejo de memoria, etc). Como resultado se dispone de una plataforma de desarrollo de aplicaciones ASR que facilita tanto la exploracin de nuevas arquitecturas hardware como el desarrollo de otros algoritmos empotrados de reconocimiento de voz.

II. RECONOCIMIENTO DE VOZ Una de las tcnicas ms empleadas en la codificacin del

modelo de voz corresponde a la tcnica LPC (Linear Predictive Coding). Dicho algoritmo permite representar una seal de voz de 160 muestras en tan slo 13 datos. Esto permite su aplicacin a la compresin de voz, transmisin digital (voz sobre IP, PCS, GSM) y, en nuestro caso, reconocimiento.

Los elementos que mejor caracterizan la voz humana son las frecuencias de los formantes del tracto vocal y las propiedades de la seal de excitacin generada por las cuerdas vocales. La tcnica LPC permite representar la voz mediante un nmero reducido de parmetros en lugar de tener que almacenar la forma de onda [1]. Esto se debe a que es posible predecir una seal mediante la siguiente expresin:

Ni

i inxany1

)()( (1)

donde y(n) es la muestra predicha en el instante n y ai son los coeficientes LPC.

La diferencia entre la muestra predicha y la seal se denomina error de prediccin:

Ni

i inxanxnynxne1

)()()()()( (2)

El objetivo del algoritmo LPC es minimizar ese error. Por lo tanto, con objeto de tener coeficientes LPC que minimicen ese error es necesario diferenciar la ecuacin 1 respecto a cada coeficiente e igualar a cero. Esto da lugar a un sistema de N ecuaciones lineales [2]:

rRa (3) donde

)0()2()1(

)2()0()1()1()1()0(

RNRNR

NRRRNRRR

R



)(

)2()1(

NR

RR

r

El algoritmo de Levinson-Durbin es un mtodo iterativo que permite obtener los coeficientes LPC [2].

III. PLATAFORMA DE DESARROLLO

A. Codec de audio La placa de desarrollo ML505 dispone de una FPGA de

Xilinx de la familia Virtex-5. Dicha placa contiene entradas y salidas de audio controladas mediante el cdec AC97 de Analog Device AD1981B [3]. Entre las caractersticas de este cdec destacamos las siguientes:

Salida S/PDIF de 20 bits para el formato de dato con frecuencia de muestreo de 48 kHz y 44.1 kHz.

Muestreo de frecuencia variable para salida y entrada de audio.

Cdec estreo full-duplex. Tasa variable de las muestras de 7040 Hz a 48 kHz con

resolucin de 1Hz. Micrfono estreo con funcin de preamplificado.

El cdec dispone de mdulos de conversin analgico-

digital (ADC) y digital-analgico (DCA). Los convertidores ADC y DCA estn basados en convertidores -. El mdulo de conversin digital-analgico se utiliza para generar la salida de audio, es decir, para reproducir sonidos. Est compuesto por 4 convertidores -, dos de 16 bits y dos de 20 bits.

Por otro lado el mdulo de conversin analgico-digital recibe los datos de entrada de audio y convierte la seal analgica en una seal digital. Este mdulo est constituido por dos convertidores - de 16 bits.

Las entradas y salidas de audio estn conectadas a 4 puertos tipo jack. Dispone de dos entradas de micrfono y conexin en lnea (Line In) y dos conectores de salidas de audio (para auriculares y conexin en lnea).

B. Mdulo IP del controlador AC97 La versin del mdulo IP del controlador AC97 de Xilinx

empleado es la versin 1.00a. Dicho controlador ha sido diseado para configurar el cdec AC97, grabar (capturar) sonido usando el bus OPB y reproducirlo usando el bus FSL. Puesto que en las actuales versiones de Microblaze el bus OPB ya est obsoleto se ha adaptado el controlador mediante un puente PLB-OPB. Tambin se han corregido errores en la descripcin de dicho componentes que originaban que tanto la funcin de grabacin de sonido como la lectura del registro de estado del AC97 no funcionaran.

Los problemas con la grabacin y con la lectura del registro de estado del AC97 se encuentran relacionados entre s. Ambos son causados por un error en el fichero de descripcin del hardware del controlador. Dicho error se debe a una mala

alineacin de las lecturas de datos en serie, que son desplazados, lo que provoca que el controlador se encuentre sin el estado vlido en el registro de entrada o en los datos de sonido.

El controlador recibe/transmite los datos desde/hacia el cdec AC97 usando dos flujos de datos series unidireccionales, SData_In y SData_Out. El dato es separado en tramas simultneas en las que cada trama est dividida en 12 ranuras de datos. Adems un reloj Bit_Clk, es generado por el cdec y transmitido al controlador. Por su parte el controlador enva una seal Sync para indicar que empieza una trama.

El flujo de datos de entrada se lee desplazando secuencialmente el flujo de datos de SData_In y escribiendo dicho dato en el registro apropiado al final de una ranura por medio de la seal Slot_End generada en el controlador. Esta seal se activa un ciclo de reloj antes del final de la actual ranura porque el flujo de salida debe ser cargado antes del comienzo de la siguiente ranura. El problema de la mala alineacin de las lecturas de datos en serie se solucion aadiendo un ciclo de reloj de retraso antes de leer el registro de desplazamientos de datos.

Figura 1. Arquitectura del sistema de captura de sonidos

C. Desarrollo de los drivers Los drivers son aplicaciones software que permiten

configurar y controlar el controlador AC97. Estas aplicaciones facilitan el desarrollo de aplicaciones de usuario. En concreto los drivers desarrollados contienen la declaracin de las direcciones de memoria donde se encuentran los registros internos del controlador AC97, as como las macros para el manejo dichos registros y los valores constantes ms significativos. La tabla 1 describe las principales funciones.

Estas funciones ofrecen las facilidades para inicializar e interaccionar con el cdec AC97. El cdec se inicializa con las funciones XAC97_SoftReset, XAC97_HardReset. Estas funciones inicializan los registros del cdec a los valores adecuados para realizar la captura de sonidos. Las funciones WriteAC97Reg y ReadAC97Reg son las funciones principales para realizar la grabacin y reproduccin de sonido.

Junto a estas funciones existen una serie de constantes y macros que facilitan el uso del cdec y su configuracin.

Cdec AC97

FPGA

Sync

SData_

Out

SData_

In

AC97

Reset

nBit

Clk

PLB OPB MicroBlaze plbv46_opb bridge

Controlador AC97



Adems de las funciones de bajo nivel mostradas en la tabla 1 se han desarrollado funciones de alto nivel que el usuario puede utilizar para manejar el cdec desde la aplicacin software. Dichas funciones son:

init_sound: Inicializa el dispositivo. Para ello aplica un reset hardware, se limpia la FIFO y se hace un reset software. La tarea de inicializacin requiere establecer una secuencia de operaciones en un determinado orden de ejecucin. Tras la inicializacin el cdec informa al controlador que est operativo. A continuacin se activan los convertidores ADC y DAC y se establece la frecuencia de muestreo. Finalmente se configuran los controles de volumen y del micrfono.

rec_sound: Se capturan los datos de la entrada de audio y se almacena en memoria.

play_sound: Se habilitan los controles de sonido para la reproduccin por la salida correspondiente. Se envan al cdec los datos de reproduccin almacenados en memoria.

TABLA 1. DRIVERS DEL CONTROLADOR DEL CDEC AC97

Funcin Descripcin

WriteAC97Reg Escribe un valor en la direccin indicada del cdec AC97

ReadAC97Reg Lee un dato de la direccin indicada del cdec AC97

XAC97_ClearFifos Limpia la memoria FIFO del controlador AC97

XAC97_SoftReset Realiza un reset software del cdec AC97

XAC97_HardReset Realiza un reset hardware del cdec AC97

IV. IMPLEMENTACIN DEL ALGORITMO LPC Existen multitud de implementaciones software del

algoritmo LPC tanto en aplicaciones especficas como formando parte de libreras para el tratamiento de seales de audio. Estas implementaciones son inadecuadas para un sistema empotrado debido a diversos aspectos relacionados con la implementacin del algoritmo. As, por ejemplo, dichas realizaciones suelen hacer uso de memoria dinmica tanto para la seal de entrada de audio como para los vectores intermedios y para la base de datos con la cual se compara el locutor a identificar. Otro aspecto a tener en cuenta corresponde a la limitacin de tamao de memoria del sistema empotrado.

La seal de audio que se procesa en el algoritmo tanto para el entrenamiento como para el reconocimiento es adquirida mediante un micrfono conectado a la placa de desarrollo basada en FPGA. El cdec AC97 convierte dicha seal en una seal digital que es capturada por el controlador AC97 y almacenada en memoria. A continuacin se realiza el procesado de los datos de acuerdo con el esquema mostrado en la figura 2.

Figura 2. Flujo del proceso de identificacin

La etapa de pre-nfasis realiza un filtrado para hacer ms significativas las frecuencias altas de la seal de voz. Este filtro de prenfasis obedece a la expresin siguiente:

s(n) = v(n) - a s(n -1) (4)

donde v(n) es la seal de voz de entrada y s(n) la seal filtrada.

La siguiente etapa corresponde a una segmentacin en ventanas de Hamming en intervalos de 20 ms. Durante ese tiempo la seal se considera cuasi estacionaria. A continuacin se aplica el producto de la seal con la ventana de Hamming con objeto de suavizar los bordes de dicha ventana:

NnN

nWn

0246.054.0 (5) siendo Wn=0 en cualquier otro caso.

A continuacin se calcula la autocorrelacin de la seal:

mNn

lll pmmnxnxmr1

0,...,1,0)]()([)( (6)

donde p es el orden del anlisis LPC [4]. Valores tpicos de p van entre 8 y 16. En el desarrollo que se describe en esta comunicacin se ha empleado p=13.

El algoritmo de Levinson-Durbin [2] permite calcular en forma recursiva la solucin de una ecuacin que involucra una matriz Toeplitz (ecuacin 3).

V. OPERACIN DEL SISTEMA El sistema de identificacin tiene dos fases de operacin:

entrenamiento e identificacin.

La etapa de entrenamiento consiste en crear una base de datos de los coeficientes LPC de individuos que debern ser identificados por el sistema. El entrenamiento requiere realizar un conjunto de iteraciones en las que los coeficientes se ajustan realizando la media aritmtica con los coeficientes asociados.

Digitalizacin

Pre-nfasis

Ventana de Hamming

Autocorrelacin

Clculo de coeficientes LPC

Decisin

Seal de audio



La figura 3 muestra un ejemplo que ilustra como a medida que se incrementa el nmero de iteraciones en el entrenamiento se incrementa la precisin en la identificacin.

Figura 3. Tasa de reconocimiento en funcin de la iteraciones en el entrenamiento.

La fase de reconocimiento consiste en determinar la similitud entre los coeficientes LPC del locutor con los contenidos en la base de datos de los individuos entrenados. En este caso se aplica la distancia euclidiana y tomando como referencia dos umbrales, uno de acierto (Ta) y otro de similitud (Ts), se decidir si se ha identificado al individuo dentro de la base de datos. Los umbrales seleccionados han sido los siguientes:

Ta, umbral de acierto: Ta < 0.02 Ts, acierto parcial (similitud): 0.02 < Ts < 0.03 en otro caso significa que no se ha encontrado un

individuo registrado que corresponda al locutor que se quiere identificar

VI. CONCLUSIONES Se ha descrito un sistema de identificacin de voz basado

en el procesador MicroBlaze de Xilinx. El sistema ha sido implementado sobre la placa de desarrollo ML505 que dispone de un FPGA Virtex5 as como entradas y salidas de audio controladas mediante el cdec AC97 de Analog Device AD1981B. La puesta a punto del sistema ha requerido adaptar un controlador del cdec de audio y desarrollar los drivers que permiten controlar la captura de audio desde la aplicacin software. La aplicacin software que implementa el algoritmo LPC se ha adaptado a la arquitectura del procesador. Por lo tanto se dispone de un sistema empotrado que permite desarrollar aplicaciones biomtricas de reconocimiento de voz.

AGRADECIMIENTOS Este trabajo ha sido soportado parcialmente por el proyecto

financiado por la Unin Europea MOBY-DIC Project FP7-IST-248858, por el Ministerio de Ciencia y Tecnologa bajo el proyecto TEC2008-04920 y TEC2011-24319 con cofinanciacin FEDER y por la Junta de Andaluca bajo el proyecto P08-TIC-03674.

REFERENCIAS [1] Priyabrata Sinha, Speech Processing in Embedded Systems, Springer,

2010 [2] L. Rabiner and B. H. Juang. Fundamentals of Speech Recognition.

Prentice-Hall, Englewood Cli_s, NJ, 1993. [3] AD1981B: AC97 SoundMAX Codec Datasheet, Analog Devices Inc,

Rev. C, 2005. [4] Milan G. Mehta: Speech recognition system, Master Thesis, Texas

Tech University, 1996.



Abstract The behavior of a circuit able to implementfrequency division is studied. It is composed of a blockwith an IV characteristic exhibiting NegativeDifferential Resistance (NDR) built from MOS transistorsplus an inductor and a resistor. Frequency division isobtained from the period adding sequences which appearin its bifurcation diagram. The analyzed circuit is an allMOS version of one previously reported which useResonant Tunneling Diodes (RTDs) The results show thatthe dividing ratio can be selected by modulating the inputsignal frequency, in a similar way to the RTD-basedcircuit.

I. INTRODUCTION

Non-autonomous, very simple frequency dividercircuit based on the period-adding bifurcation sequenc-es which appear in an RTD chaos circuit have been re-ported in the past few years [1], [2], [3], andexperimental results have been obtained, showing thatthe phase noise is comparable to that of conventional di-viders. These circuits exploit the NDR region in theRTD IV characteristic to obtain autonomous nonlinearoscillators and, in general, extremely complex behav-iors with applications in diverse fields. Additionally,when an external periodic excitation signal is used, suchcircuits exhibit an increased variety of bifurcations se-quences.

The basic block for these circuits is the RTD,which consists of an emitter and a collector region anda double tunnel barrier structure. This contains a low-bandgap narrow quantum well, which allows electronsto travel through only at the resonant energy level. Thethickness of the barrier layers as well as the width of thewell are in the nanometer range. The RTD IV charac-teristic presents a typical N-shape with two positive dif-ferential resistance (PDR) and one NDR zones. Most ofthe reported working circuits have been fabricated inIII/V materials and require a technological process usu-ally expensive and difficult to compatibilize with MOSprocesses. In this paper we show an NDR device made

from MOS transistors that can be used to design a fre-quency divider circuit which operation is based on thesame principle as the RTD.

II. THE MOS-NDR STRUCTURE

Figure 1a shows the structure of the MOS-NDR de-vice we have used, which is based on the circuits de-scribed in [4]. It consists of one CMOS inverter, madeup by NMOS1 and PMOS1 and biased by VINV, and oneNMOS transistor (NMOS2) whose gate-to-source volt-age is modulated by the output voltage of the CMOS in-verter. Figure 1b shows the simulated current-voltagecharacteristic of the MOS-NDR device for transistorparameters given by WPMOS,1 = 0.16m,WNMOS,1 = 2m, and WNMOS,2 = 5.4m; channellength for all of them is 0.12m. For this case, the peakcurrent (Ip) is 2.11mA for a peak voltage (Vp) of 0.25V.Both, the PDR and the NDR zones of the IV character-istics are obtained through the current of the NMOS2transistor.

This work has been partially supported by the Spanish Government under projects TEC2007-67245/MIC and P07-TIC-02961.

-0.2-0.1 0.1 0.2 0.3 0.4 0.

-2-1

1

2iNDR(mA)

Figure 1: (a) MOS-NDR device, (b) IV characteristic, (c)Measured IV characteristics.

(b)

(c)

Ip

Vp

vNDR(V)

PMOS1

NMOS2NMOS1

INDRVNDR

VINV

(a)

Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits

Juan Nez, Mara J. Avedillo, and Jos M. QuintanaInstituto de Microelectrnica de Sevilla-Centro Nacional de Microelectrnica

Consejo Superior de Investigaciones Cientificas (IMSE-CNM-CSIC), Univ. de Sevilla (US)jnunez{avedillo, josem}@imse-cnm.csic.es



The peak voltage and current of the IV character-istic in Figure 1b can be modified by setting up properlythe sizes of the transistor. In this way, Ip is increasedwith the width of NMOS2. Assuming that all transistorshave the same gate length, the position of Vp is control-led by the ratio between the widths of NMOS1 andPMOS1. In this way, higher values of Vp are obtained bydecreasing the ratio . Additional-ly, we can obtain higher peak current values by increas-ing VINV [5]. Compared to the RTD device, the IVcharacteristic in the MOS-NDR device lacks the secondPDR zone and presents a typical -shape. Figure 1c de-picts the I-V characteristic, measured by a HP-4145Aparameters analyzer, of a MOS-NDR which we havedesigned and fabricated in a standard commercial0.13m CMOS process.

III. ANALYSIS OF THE FREQUENCY DIVIDER.

The circuit topology used for the frequency divideris shown in Figure 2. It is composed of an inductor L inseries with the parallel of the MOS-NDR device (the device) and one capacitor C. It is driven by an externalperiodic excitation signal E, with a DC bias EDC, an am-plitude EA, and a frequency f( ).

By applying Kirchoffs laws to this circuit, theequations for the voltage vC across the capacitor C andthe current iL through the inductor L are given by thefollowing set of two first-order coupled non-autono-mous differential equations:

(1)

where is the mathematical representation of thedriving point characteristic of the MOS-NDR device.The system is non-autonomous due to the explicit de-

pendence of time t in the expression for excitation sig-nal E, and periodic with period . If we chooseEM and IM as scale parameters with physical dimen-sions of voltage and current, respectively, and rescale

, , , ,, and , then variables x, y, ,

and will be dimensionless. Redefining now as t, thefollowing set of normalized equations are obtained:

(2)

where and come from thenormalization of . The dynamics of Eq. (2) nowdepends on parameters , and . As the circuit isperiodically driven, planes and can beidentified, and the 3D Euclidean phase space can be transformed into the cylindrical space

[6] by defining the new variable which transforms the non-autonomous sys-

tem of Eq. (2) into an autonomous one, now with threeequations, by adding . In this space, timeturns around the unit circle , x is represented in thehorizontal axis of the cylinder and y in the vertical one.

The dynamics of Eq. (2) has been extensively stud-ied for different parameter values. By fixing

, the frequency of the external periodic sig-nal has been used as the control parameter, and numer-ical integration using an adaptive-step Runge-Kuttaalgorithm has been carried out to build one-parameterbifurcation diagrams in the plane. These dia-grams plot the normalized output voltage x sampled ata fixed phase of the normalized input signal for eachnormalized frequency , and solutions during the first60 periods of the input signal have been discarded toavoid transient behaviour. Figure 3 shows a typical bi-furcation diagram for the circuit computed when thenormalized frequency is swept in the range (0.01,1.5)with the following values for the remaining parameters:

, , and . In circuit parameter val-ues, this could correspond, among other possible set ofvalues, to C = 4pF, L = 1H, EM = 1V, IM = 1mA; anexternal periodic signal with EDC = 0.3V, EA = 0.4V,and a frequency between 10MHz and 1.5GHz. TheMOS-NDR device is biased in the negative resistanceregion and a swing is applied. In this bifurcation dia-gram two kinds of regions are identified: those with acontinuum of points for a given value of , where thebehaviour is quasi-periodic or chaotic, and regions witha finite number of points, where a periodic solution witha period which is a multiple of the driving signal isfound.

WNMOS 1 WPMOS 1

E EDC EA 2ft sin+=

L

C

vCiL

vL

iNDR

iC

Figure 2: Frequency divider circuit using a MOS-NDRdevice (-device).

EMOS-NDR

device

dvCdt

--------- 1C---- iL iRTD 1C---- iL G vC = =

diLdt------- 1L

--- E vC =

G

T 1 f=

vC xEM= iL yIM= t LC= EDC EM=EA EM= f LC=

x 1--- y g x =y 2t sin x+ =

EM IM C L= g G

t 0= t 1 =

x y t x y R2 S1 2t=

2=S1

and

x

= 2 = 0.3 = 0.4



From Figure 3, the solution is a periodic orbit witha period equal to the one of the driving signal for up to

. From this until , the period of thesolution is the original one divided by 2. Then, until

, the division is by 3. For , frequen-cy-locking states of variable period which are separatedby quasi-periodicity regions are obtained. Additionally,it is interesting to note that the number of branches inthe periodic windows increases when the frequency in-creases: this behaviour is known as period-adding bifur-cations [7]. In these frequency-locking regions we canobtain frequency division from the driving signal, withthe division factor being the number of points in such aregions. Thus, between and the fre-quency-locking state has period-4, for has period-5, period-6 for , etc. Over

, the bifurcation diagram is mainly formed by re-gions of quasi-periodicity. Examples of numerical re-sults for (period 4) and (quasi-periodic behaviour) are shown in Figure 4 and Figure 5,respectively. In particular, a period-4 trajectory in thecylindrical space is shown in Figure 4a, while Figure 4bplots this trajectory in plane , and the corre-sponding Poincar map with four points is shown inFigure 4c. The quasi-periodic trajectory motion for

is on the surface of the torus shown in Figure5a (cylindrical space). Figure 5b shows such a trajecto-ry in plane . Figure 5c shows the correspondingPoincar section, which is composed of an infinite set ofpoints which belong to an invariant closed curve, whichis typical in a quasi-periodic behaviour.

In addition to the period-adding sequences, Figure3 also shows that periods of some of the windows satis-fy the Farey sequence [8]. Between the period- and pe-riod- windows, there exists a period-(+) window.Some examples of such Farey sequences in the bifurca-tion diagram of Figure 3 are shown in Figure 6: whenthe input normalized frequency increases in the range

(period-6 to period-7), we find a fre-quency locked window of period-13 (=6+7) in the re-gion . Farey sequences also appearwhen finer regions are considered, as is also shown inFigure 6, where a period as high as 19 (6+13) appears inthe region . Finally, we have alsoperformed some simulations to confirm our previoustheoretical study. Figure 7 shows the obtained resultsfor the circuit parameters in Section III (C = 4pF,L = 1H, EM = 1V, IM = 1mA, EDC = 0.3V, andEA = 0.4V). Figure 7a shows a division by 3 of a exter-nal periodic signal of frequency 125MHz ( = 0.25),and Figure 7b the division by 5 of a signal which fre-quency is 10MHz ( = 0.38).

IV. CONCLUSIONS

We have shown an all-MOS device with an IVcharacteristic exhibiting NDR which can be used tobuild a frequency divider. One difference with previ-ously reported RTD-based circuits is the possibility ofusing a simple MOS process for its implementation. Inan analog way to these previous circuits, the frequencydivision is also obtained from the period adding se-quences which appear in its bifurcation diagram. Addi-tionally, we have shown the Farey sequences whichappear in the dynamic behavior of the circuit.

References[1] Y. Kawano, Y. Ohno, S. Kishimoto, K. Maezawa, and T.

Mizutani, 50 GHz frequency divider using resonant tun-nelling chaos circuit, IEE Electronics Letters, Vol. 38,no. 7, pp. 305-306, 2002.

[2] Y. Kawano, Y. Ohno, S. Kishimoto, K. Maezawa, T. Mi-zutani, and K. Sano, 88GHz dynamic 2:1 frequency di-vider using resonant tunnelling chaos circuit, IEE Elec-tronics Letters, Vol. 39, no. 21, pp. 1546-1548, 2003.

[3] J.M. Quintana and M.J. Avedillo, Analysis of frequency di-vider RTD circuits, IEEE Trans. on Circuits and Systems I:Regular Papers, vol. 52, no. 10, 2005, pp. 2234-2247.

[4] C. Wu, and K.-N. Lai, Integrated -type differential nega-tive resistance MOSFET device, IEEE J. Solid-State Cir-cuits, Vol. SC-14, pp. 1094-1101, Dec. 1979.

[5] W.-L. Guo, CMOS-NDR transistor, 9th InternationalConference on Solid-State and Integrated-Circuit Technolo-gy, (ICSICT), pp. 92-95, Oct. 2008.

[6] T. S. Parker and L. O. Chua, Practical Numerical Algo-rithms for Chaotic Systems. New York: Springer-Verlag,1989.

[7] L.-Q. Pei, F. Guo, S.-X. Wu, and L. Chua, Experimentalconfirmation of the period-adding route to chaos in a nonlin-ear circuit, IEEE Trans. on Circuits and Systems, Vol.33, no. 4, pp. 438-442, April 1986.

[8] K. Kaneko, Collapse of Tori and Genesis of Chaos in Dissi-pative Systems. Singapore: World Scientific, 1986.

Figure 3: Bifurcation diagram for circuit in Figure 2( , , and ) = 2 = 0.3 = 0.4

x

0.12 0.21 0.28 0.30

0.30 0.350.37 0.42

0.44 0.50 1

0.32= 0.64=

x y

0.64=x y

0.45 0.53 0.508 0.514

0.503 0.505



Figure 4: Trajectories from the numerical results for diagram for , ( , , and ).(a) in thecylindrical space, (b) in the plane , and (c) Poincar map.

= 0.32 = 2 = 0.3 = 0.4x y

Figure 5: Trajectories from the numerical results for diagram for , ( , , and ).(a) in the cylin-

drical space, (b) in the plane , and (c) Poincar map.

= 0.64 = 2 = 0.3 = 0.4x y

6 719 13

Figure 6: Bifurcation diagrams illustrating Farey sequencesfor the circuit in Figure 2.

Figure 7: Simulation results giving a frequencydivision of (a) 3, and (b) 5.

(a)

(b)

vC(V)

vC(V)

t (s)

t (s)



Prediction of Energy Transfer in Implantable Devices

Romulo Volpato

INATEL

Santa Rita do Sapucai, Brazil

Tales Pimenta, Filipe Ramos, Michel Santana and Paulo Crepaldi

UNIFEI

Itajuba, Brazil

AbstractThis work presents an approach for the evaluation of energy transfer in implantable device for medical applications.

By using the inductive coupling it is possible to predict the

voltage in the powerless tag inside the human body. The

measurement result indicates that it is possible calculated the

influence of the meat in magnetic field between the reader and

the tag.

Keywords-RFID, inductive coupling, RF, Implantable device

I. INTRODUCTION

The demand for Radio-Frequency Identification RFID technology has been constantly increasing in various areas of knowledge and applications, including human health. Biomedical data, such as blood levels of cholesterol, urea, oxygen and sugar (glucose), among others, could be measured by using tag sensors inside the human body. The data measurements are sent out by RFID technology and the power is send in also by the RF link. This process uses the magnetic field link between two inductors, one in the reader and the other in the implantable device (tag). Here, the main challenge is to find the best intensity of magnetic field by the reader for the perfect tag operation. According to [1] [2], variations in distance and misalignment between the inductors results in variations of the coupling factor, which in turn causes a voltage variation on the tag that. It could promote improper or even lack of operation.

This work presents an approach to find the voltage in implantable tag by using the classic magnetic theory and measurements conducted in actual experiments. Figure 1 presents the simplified coupling between reader and tag [2].

Fig. 1. Simplified coupling between reader and tag.

II. ENERGY TRANSFER MODELING USING THE CLASSIC MAGNETIC THEORY

The energy is transferred from the reader to the tag by magnetic coupling. In free space, the magnetic field generated by inductor L1 induces a current in inductor L2. From the classic magnetic theory, the equivalent circuit is show in Figure 2.

Fig. 2. Equivalent circuit to inductive reader-tag coupling.

The analysis can be greatly simplified by using the series equivalent circuit for the tag load Rtag. Thus the quality factor of the capacitor C2 can be expressed in terms of capacitive and resistive parameters, as indicated in Figure 3.

Fig. 3. Capacitive equivalent circuits.

In order to find equivalence between the series and parallel representation, the real and the imaginary parts of each other must be the same. Therefore, from basic circuit theory:

ppp CjGy (1)

22 )( pp

p

sCG

GR

(2)



p

pp

sC

CGC

2

22 )(

(3)

where:

pp

RG

1 (4)

That approach allows taking the tag load as Rp, as show by expression (2), since the quality factor of the capacitor is very high. Observe also that the capacitor value in equation (3) is frequency dependent. Based on this approach, the equivalent circuit is presented in Figure 4.

Fig. 4. Equivalent circuit modified to inductive reader-tag coupling.

The circuit presented in Fig. 4 can be equated as:

pt RRR 2 (5)

Thus:

MjI

CjLjRIV s

2

1

1111 )1

(

(6)

where M is the mutual inductance between L1 and L2.

)

1`(0

22221

CjLjRIMjI s

(7)

Equations (6) and (7) yield:

2

1

11

2

222

12

)]1

)(1

'()[( CCj

LjRCj

LjRM

MVV

ss

(8)

It can be observed from equation (8) that it is possible to obtain the voltage tag, in free space conditions. Nevertheless, in implantable applications, the tag is placed inside the human body. Usually a device used to measure blood glucose level is placed in the abdomen (belly) whose tissues offer an electrical behavior similar of pig tissue. Therefore we have used pork meat in our experiments.

III. COMPARISON BETWEEN SIMULATION AND MEASUREMENTS UNDER FREE SPACE CONDITIONS

We have used the measurement set up shown in Figure 5 where L1=1.77 H and L2=5.4 H. Note that it is implemented axial alignment. This orientation was chosen due to the higher induced magnetic flow, considering the relationship between the length and diameter of the inductors. The series resistances obtained from the network analyzer are R1=1.14 and R2=2.2 at 13.56 MHz.

Fig. 5. Free space set up measurement.

The measurement and simulation were conducted considering the voltage of generation as 1 V, the parallel load of tag as 1k and the generator resistance as 50 .

The voltage at the tag is approximately 1V, but the resonance frequency varies along with the mutual inductance. Therefore, for each mutual inductance, capacitors C1 and C2 can be adjusted for the maximum voltage at the tag. Table 1 shows the comparison between simulated and measured results. The adjustments of C1 and C2 are very difficult, therefore the voltage at the tag will vary along the measurements. The amount of energy transmitted from the reader to the tag can be easily obtained, since power is the squared voltage divided by the tag load (1k).

TABLE 1 COMPARISON RESULT FOR SIMULATION AND MEASUREMENT

Distance Measurement Simulation M

25mm 769mV 1001mV 0.287H

20mm 943mV 1061mV 0.370 H

15mm 1038mV 1063mV 0.532 H

10mm 1026mV 1055mV 0.692 H

5mm 1007mV 1052mV 0.917 H

Observe that the simulated and measured values are very

close when the reader and the tag are between 5 to 15 mm apart.



IV. MEASUREMENTS COMPARISON IN FREE SPACE AND WITH TISSUE

It was observed the tag voltage difference between measured and simulated results for free space conditions. The results are now compared to new measurements considering the presence of pig tissue between the tag and reader. Figure 6 and 7 show the measured set up.

Fig. 6 Measurement set up between tag and reader for free space.

Fig. 7. Measurement set up with tissue between tag and reader.

Tables 2 shows the tag voltage values at free space and with pig tissue. The tissue is about 10mm thick and long enough to cover the tag completely, as shown in Figure 6.

TABLE 2 COMPARISON OF FREE SPACE AND TISSUE CONDITIONS

Distance Free space Pork tissue

10mm 1932mV 1869mV

15mm 1869mV 1787mV

20mm 1671mV 1549mV

25mm 1247mV 1202mV

As can be observed, there is a small difference on the voltage at the reader under the presence of pig tissue. Table 3 presents the tag voltage error at free space and with pig tissue. The error is usually smaller than 5% and reaches 7.3% only at 20mm.

TABLE 3 MAXIMUM ERROR

Distance Error

10mm 3.26%

15mm 4.39%

20mm 7.3%

25mm 3.61%

This result suggests that the tissue changes the magnetic

permeability relative to free space conditions.

V. CONCLUSIONS

The presence of pig tissue between the reader and the tag causes a voltage tag reduction and a consequently reduction of power. This power reduction is, in the worst case of 14%. Therefore, the voltage (or power) drop is known, it should be taken into consideration during RFID systems design.

It also can be inferred the small influence of any tissue at 13.57 Mhz. It is very important to know the maximum voltage in the tag, mainly for implantable devices, so that the designer can take the proper precautions.

ACKNOWLEDGMENT

The authors acknowledge CAPES, CNPq and FAPEMIG for their financial support.

REFERENCES

[1] M. Kiani and M. Ghovanloo, An RFID based Closed Loop Wireless Power Transmission System for Biomedical Application, IEEE trans on circuits and system II- Express Brief, Vol 57, NO 4, April 2010.

[2] K. Finkenzeller, RFID Handbook Fundamental and Application in Contactless Smart Cards and Identifications, 2010, John Wiley & Sons.

[3] F. Ramos, M. Santana, R. M. Volpato, R. L. Moreno and T. C. Pimenta, Front End of an Implantable Medical Device, Wireless Systems International Meeting, May 26-28, 2010, Campina Grande , Brazil

[4] Frederick Emmons Terman and Joseph Mayo Pettit, Electronic Measurements, McGraw-Hill 1952.

[5] K. Kenneth and T. Donald, Communication Circuits Analysis and Design, 1971.

[6] W. E. Everitt e G. E. Anner, Communication Engineering, McGraw-Hill, 1956.

[7] Simon Haykin and Barry Van Veen, Signals and Systems, John Wiley & Sons, 1999.

[8] Johnson I. Agbinya,Nitthya Selvaraj, Arthur Ollett, Stephane Ibos, Yasmin Ooi-Sanchez, Mark Brennan and Zenon Chaczko, Size and Characteristics of the Cone of Silence in Near Field Magnetic Communications, MILCIS, Canberra, 10-12 November 2009.

[9] Andr Kurs, Aristeidis Karalis, Robert Moffatt, J. D. Joannopoulos, Peter Fisher and Marin Soljacic, Wireless Power Transfer via Strongly Couplet Magnetic Resonances, Sience Vol 317, july 2007



Schottky Barrier Diodes (SBD)

in Standard CMOS Process

David Cabral, Leonardo Zoccal, Paulo Crepaldi and Tales Pimenta

UNIFEI

Itajuba, Brazil

Abstract This paper discusses the implementation of a Schottky Barrier Diode SBD in standard CMOS process as a way to optimize the overall performance of a passive Radio-

Frequency Identification RFID based biomedical implant. For this kind of systems, it is essential that the transmitted power is

kept within acceptable levels so there is no damage in human

tissues.

Keywords-Schottky Barrier Diode, RFID, Implantable device

I. INTRODUCTION

Cost, size, lifetime and safety are important parameters when designing a RFID based biomedical system, especially if the receiver is an implanted device.

For size reduction and extended lifetime the receiver can be implemented without batteries, thus characterizing a passive tag. Therefore, it is necessary an RF link to make the communication path between the base unit and the transponder. Through the link and a proper protocol, information can be exchanged and energy can be delivered to the implant for its activation. Fig. 1 shows a typical RFID topology for biomedical applications [1].

Base Unit

Sensors +

Aquisition

+

Signal

Conditioning

+Processing

Energy + Information

Information

RF

DC

Transponder (tag)

Implanted Device

Skin

RF to DC

Rectification

Antennas

Figure 1. Typical RFID system.

The energy is transmitted by a pair of coupled coils. For patient safety it is important to keep the induced electromagnetic fields at lower levels, to avoid tissues damages by raising the local temperature. The Specific Absorption Rate (SAR) represents direct measurements of the electric field (indirect measurement of the magnetic field) and induced current density over the human tissue at the implant

location. The temperature variation over the time indicates the local heating factor. Both relations are given by [2]:

KgW

ESAR

2

(1)

s

Cc

SAR

dt

dT 0 (2)

where , and c represent the conductivity, the human tissue mass density and specific heat capacity, respectively, at the implant location. E is the incident electric field intensity (RMS). Based on equations (1) and (2), a safe value for the power transferred by the RF link is 10mW/cm

2 [2].

Besides cost and size reduction, microelectronics also allows the implementation of the transponder circuits into a single die. The lowest prices can be achieved by using low cost standard CMOS technology.

Transponder front-end circuits include a rectifier to make the AC-DC conversion to provide unregulated power supply to the tag. In CMOS technology, NMOS and PMOS (more often than one of each type) transistors are used in different topologies to implement the rectifier circuit. These devices, however, have the disadvantage of presenting a turn on threshold voltage (Vth) that may require larger induced voltage in the receiver coil. Although the CMOS technology has been minimizing the transistors geometries, the Vth voltage does not scale down at the same rate. The use of a Schottky Barrier Diode SBD is an alternative way to design the rectifier circuit in order to improve its efficiency. A more efficient rectifier will reduce the voltage drop between the tag input and the rest of the circuitry, thus reducing the power demand from the transmitter. For low currents levels, typically found in this kind of application, the SBD voltage drop can be lower than a CMOS Vth voltage.

The SBD is not readily implemented on a standard CMOS technology but after a few adjustments in the masking process, it can be implemented. In this work, a mask sequence is



presented to implement SBDs in CMOS processes and a simple model for this device is discussed.

II. SCHOTTKY BARRIER DIODE

The metal-semiconductor contact has some features that allow its use in high frequency applications and systems that must operate at low voltage levels. These features are, basically, the low level of minority charge accumulation during commutation, which leads to high switching speeds and the low voltage drop between its terminals [3].

Low turn on voltage, fast recovery time and low junction capacitance are advantages that SBD offer over other types of PN diodes. These are the main reasons that SBD are so popular in RF applications. As a consequence of high switching speed, ability to operate at high frequencies and low turn on voltage SBD are applied to RF mixer and detector diodes [4].

SDB are also used in rectifiers for high and low voltage because of their high current density and low voltage drop. For solar cell applications, any voltage drop will result in a reduction in efficiency and therefore a low voltage drop diode is essential [5].

Fig. 2 shows the energy band diagram for this kind of contact at thermal equilibrium. In this work, since we have used TSMC process, the metal is aluminium and the semiconductor is N-type, moderately doped, obtained by N Well diffusion.

MBN qq biqV

WFE

CE

VE

Metal

Semiconductor

Figure 2. SBD finger structure.

As can be seen, there is a build in contact potential Vbi, expressed by:

D

CBNbi

N

Nln

q

kTV (3)

where kT/q is the thermal voltage (25.9mV at T=300K), NC is the effective state density (constant for a given temperature) in the conduction band, ND is the donor doping level and BN is maximum height of the potential barrier[6].

Eq. (3) shows that the built in voltage can be reduced if a moderate to low doping semiconductor is used. Considering ideal values for metal work function (M4.28V) and semiconductor electron affinity (4V), the barrier BN can be

as low as 280mV. Considering eq. (3), the built in voltage Vbi can be further reduced by controlling the doping level ND.

In practice, however, there will be imperfections in the boundary between metal-semiconductor contact (like surface states) that contributes to raise that voltage.

It must be necessary to evaluate the doping concentration ND in order to use eq. (3) to obtain Vbi. For this procedure a C-V curve for a Metal-Insulator-Semiconductor (MIS capacitor)) structure is used. Fig 3 and Fig. 4 show a typical MIS capacitor (with N type semiconductor) and a C-V curve, respectively.

Metal

N type Semiconductor

Insulator

Figure 3. MIS capacitor.

Low frequency

High frequency

Inversion Depletion Accumulation

Figure 4. MIS capacitor C-V curve.

The C-V curve can be obtained by simulating a PMOS transistor with TSMC model parameters as indicated in Fig. 5.

R1 R2

M1W=100m

L=100m

Fig. 5. PMOS transistor used to obtain C-V behavior.

In this simulation, resistors R1 and R2 are very large in order to restrict the action of PMOS in the channel area. The DC source is swept from negative to positive voltage values, to validate all regions of operation of the MOS capacitor formed by the gate, insulator and channel. The AC source can



be set into low or high frequencies; therefore, it is possible to obtain the C-V curve behaviour as illustrated in Fig. 4.

The capacitor area (A) is determined by the geometric aspects W and L.

The following equations are used to extract the doping concentration ND in a recursive way:

C

CC

Wmax

S0

min

max

D

A1

(4)

W

N 2D

FS

Dq

4 (5)

nN

i

D

Fln

q

kT

(6)

III. MASK FLOW

Ideally, the SBD would be implemented by a metal layer

deposition over a low doping N or P type semiconductor well.

In order to reduce the series resistance to improve the

efficiency, the SBD, actually, is an arrangement of fingers as

can be seen in Fig. 6 and Fig. 7.

In this design we have used 0.5m CMOS TSMC process

through MOSIS educational program.

The whole SBD structure is surrounded by a guard ring,

which is used basically to avoid latch-up and to separate the

SBD from the other tag circuits that present different analog

and/or digital functions.

Figure 6. SBD finger structure.

N+

Nwell

P+

P+

Substrate P

Figure 7. SBD cross section view.

In order to implement the metal-semiconductor junction it

is necessary the following mask sequence. First, an NWELL

(layer #42, TSMC) and an ACTIVE (#43) are used to delimit

the area that will contain the multi-finger SBD and guard

ring. Then an NPLUS layer (#45) is used to indicate N+

regions that will be the SBD ohmic contacts (cathode). The

next step is the CONTATCT layer (#48) that will be filled

with METAL 1.

It is necessary to define the Schottky and guard ring

contacts, and the contacts must reach the N well and the

active regions directly. Others contacts must coincide with

the previous N+ diffusions to effectively make the ohmic

contacts. With the METAL1 layer (#49), the SBD is

complete. Additionally, a VIA layer (#50) is used to provide

interconnections between the metal levels. Finally, the

METAL 2 layer (# 51) is applied to metal 2 to provide access

to the ring guard. Fig. 8 shows a 3D view of layers and Fig 9

a 2D view of the basic SBD structure without PADS and

interconnections (MASK #42 to #49).

Figure 8. 3D layers view for the complete SBD structure.



P type wafer

Silicon Dioxide

N type silicon

(MASK #42)

P+ diffusion

(MASK #43)

N+ diffusion

(MASK #45)

Via oppening

(MASK #48)

Metal deposition

(MASK #49)

Figure 9. 2D layers view for the basic SBD structure.

It is important to observe that it is not necessary to modify the

CMOS process in terms of doping levels, metal type or other

process parameters.

IV. SBD SMALL-SIGNAL MODEL

The most important difference between Schottky and PN

structures is the lack junction capacitance that eliminates the

electrons recovery time.

From the previous explanations, it is now possible to

construct the equivalent small signal circuit model of the

SBD, as shown in the Fig. 10.

CT

RD

RS

CGEOM

LS

Figure 10. Small-signal SBD equivalent circuit.

In this equivalent circuit there is a capacitance (CGEOM)

that arises from the device geometry. It can be calculated

from expression (7).

L

AC

s

GEOM

(7)

where L is the length of the device of cross-sectional area A,

and s is the silicon electric permittivity (11.7 0).

There is a Rd resistance and a CT capacitance both from

the depletion region, respectively equated by:

dI

dVRd (4)

and

2/1

2

VV

qNAC

bi

sD

T

(5)

where q is the electric charge and the V is the voltage applied

across the SBD.

Finishing the model, the resistance (Rs) in series with the

components represents the depletion region, corresponding to

the contacts resistance and the neutral region of the

semiconductor. A parasitic impedance (Ls) influences the

device operating at high frequencies [7].

V. MEASURED RESULTS

The SBD was diffused in three different versions; with 5

fingers, 10 fingers and 15 fingers. Table I shows the

calculated small-signal parameters from a set of DC



measurements. The presented values are an average on 40

samples. These parameters will be used in future work to

optimize the final geometry of the SBD.

Table I. SBD small-Signal parameters.

CGEOM [pF] Rd [] CT [pF]

5 fingers 160 2275 0.4

10 fingers 100 1039 0.8

15 fingers 69 79 1.2

Figure 11 shows the IV characteristic for the three diffused

SBD. The curves represent an average value for 40 samples.

0,0E+00

5,0E-03

1,0E-02

1,5E-02

2,0E-02

2,5E-02

3,0E-02

3,5E-02

4,0E-02

4,5E-02

-1,0 0,0 1,0 2,0 3,0 4,0

Cu

rre

nt

(A

)

Bias (V)

SBD IV Characteristic

Average15

Avarage10

Avarage5

0,0E+00

2,0E-04

4,0E-04

6,0E-04

8,0E-04

1,0E-03

0,10 0,20 0,30 0,40 0,50

Figure 11. SBD IV characteristic.

Fig. 11 also shows that the SBD barrier is approximately

250mV, thus is in accordance with eq. (3).

The main goal at this point is to validate the fabrication

process. As can be seen it is possible to fabricate this kind of

device in a standard, and it can be optimized through its

geometric aspects.

VI. CONCLUSIONS

In this work, a diffusion of Schottky Barrier Diode in

CMOS standard process is discussed. This component is very

attractive to be used in applications such as biomedical tags,

where the cost, efficiency and power consumption are

important boundary conditions to avoid patients tissues damage as well as to keep the transmitter power at minimum.

ACKNOWLEDGMENT

The authors acknowledge CAPES, CNPq, FAPEMIG and MOSIS for their financial support.

REFERENCES

[1] Brandl, M. et all, Low-Cost Wireless Transponder System for Industrial and Biomedical Applications Information, Communications and Signal Processing, 2005 Fifth International Conference on, 06-09 Dec. 2005 Page(s): 1444-1447

[2] Pradier, A. et all, Rigorous Evaluation of Specific Absorption Rate (SAR) Induced in a Multilayer Biological Structure Wireless Technology, 2005. The European Conference on, 3-4 Oct. 2005 Page(s): 197-200

[3] Janam Ku and Seonghearn Lee, Novel SPICE Macro Modeling for an Integrated Si Schottky Barrier Diode, EGAAS 2005.

[4] Rainee N. Simons and Philip G. Neudeck, Intermodulation-Distortion Performance of SiliconCarbide Schottky-Barrier RF Mixer Diodes, Microwave Theory and Techniques: Jorunals, IEEE Transactions Volume 51, ISSue 2, February 2003 Page(s): 669 - 672.

[5] S. V. Averin, Fast-Response Photo-detectors with a Large Active Area, Based on Schottky-Barrier Semiconductor Structure", Kvantovaya Electronika, vol. 23(3), 284, (1996).

[6] Streetman, Solid State Eletronic Devices, Vol.2, pp. 185-190 (1980).

[7] Pascal Philippe, Walid El-Kamali and Vlad Pauker, Physical Equivalent Circuit Model for Planar Schottky Varactor Diode, Microwave Theory and Techniques: Jorunals, IEEE Transactions Volume 36, ISSue 2, August 2002 Page(s): 250 - 255.



Performance of a MOHOS-type Memory by

Using Different Tunneling Oxide Thickness

Joel Molina, Rafael Ortega, Wilfrido Calleja, Pedro Rosales, Carlos Zuniga and Alfonso Torres. National Institute of Astrophysics, Optics and Electronics (INAOE), Electronics Department.

Luis Enrique Erro #1, C.P. 72000, Tonantzintla, Puebla. Mxico. [email protected]

Abstract- In this work, we present the use of HfO2 nanoparticles

(np- HfO2) embedded in a spin-on glass oxide matrix as an active

charge trapping layer for a metal/oxide/high- oxide/tunneling oxide/silicon (MOHOS) type-memory structure. The active

trapping layer of high oxide is deposited on a thin layer of chemical silicon oxide (SiOx) of less than 5nm. According to the

chemical oxide thickness, we could observe some differences in

figures of merit for memories like writing/erase time and

retention time.

I. Introduction

The technological progress and the scaling down of electronic

devices have carried out to new research in nonvolatile memory

industry. The typical silicon-oxide-nitride-oxide-silicon (SONOS)

charge trapping-based nonvolatile memories [1] have been widely

studied in past years. According to the International Technology

Roadmap for Semiconductors, the main problem of SONOS devices

is the prohibitive scaling down of tunneling oxide thickness due to

high leakage currents [2]. There are a wide variety of films with

higher dielectric constant values () than SiO2 which seems to solve the leakage current problem. However, many of these films are not

thermodynamically stable on silicon or are lacking in other properties

such as high breakdown voltage, low deposition temperature and

compatibility with MOS process. Currently interest is centered on

films such as HfO2 with dielectric constant () value of 25 [3] which seem to be a promising candidate to replace Si3N4 films as the charge

trapping layer of SONOS-type memory devices. These high- materials lead to a new type of memory structure silicon/oxide/high-/oxide/silicon (SOHOS)-type memory [4].

The active trapping layer based on HfO2 nanoparticles (np-

HfO2) embedded in a SiO2 matrix layer, deposited by spin-on glass,

is deposited on thin chemical oxide. After some thermal annealing

treatments, a final oxide is deposited by a sol-gel method in order to

block the generated charge toward the gate. This layer is called

blocking oxide. The high oxide acts as a charge storage which can develop memory effects by modulating the density of trapped charge

according to the applied gate voltage. The thickness of the active

oxide layer is limited by the grain size of the np-HfO2 which is about

100 nm in diameter. It is expected that, by using a high quality

blocking oxide, the density of trapped charge present by the active

high layer can be retained and get wider hysteresis window because of its ability for charge retention. Measurements of capacitance-

voltage and current-voltage are performed in order to extract the

performance of these devices. Also, figures of merit like

program/erase time and retention time are obtained.

II. Experimental procedure

The fabrication of the MOHOS-type memory devices started

with chemical oxide growth on n-type (100) 7-10-cm resistivity silicon substrate. This thin chemical oxide is obtained by exposing

substrates to H2O2 heated at 85C. Different chemical oxide

thicknesses are obtained when samples are removing from H2O2 at

4min, 16 min and 32 min. The thickness of the chemical oxide is

measured by ellipsometry. The charge trapping layer is prepared

using the sol-gel spin-coating method. HfO2 nanopowder of

American Elements PN HF: OX-03-NP with purity concentration of

99.9% is used as the precursor of the high-k dielectric nanoparticles

(np-HfO2). Initially, np-HfO2 and DI water are mixed with reactive

acetic acid (CH3COOH) in order to dissolve the nanoparticles. This

first solution is heated at temperature of 40C by one hour. Then, the

Filmtronics spin-on glass (SOG) 15A, of silicate family, is added to

the first solution and it is h

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