Polymer Poster SymposiumCenter for Hierarchical Manufacturing ● University of Massachusetts Amherst

The NASIC Computational Fabric: Opportunities and DirectionsPritish Narayanan, Lin Zhang, Michael Leuchtenburg, Prachi Joshi, Csaba Andras Moritz

Department of Electrical and Computer Engineering, University of Massachusetts in Amherst

Semiconductor NanowiresOur Fabric: Nanoscale Application Specific ICs (NASICs)

Nanoscale Application Specific ICs Opportunities

Summary and DirectionsCircuit Level SimulationsxnwFET DevicesIntegrated Device-Circuit Explorations

Manufacturing Pathway for NASICs: A Perspective

The NASIC Manufacturing Pathway Nanowire Growth and Alignment TechniquesLithography Requirements for Nanogrid Functionalization

• Nanowires shown with different materials: Si, Ge, InSb etc.

• Control of composition, structure, size, doping

• Crossed Nanowire Field Effect Transistor (xnwFET) behavior observed

How do we build computational fabrics with xnwFETs?

Silicon Nanowires on SOI

Melosh et.al. Science (300) pp. 112

xnwFET arrayZhong et.al. Science (302) pp. 1377

• Semiconductor NW grids with xnwFETs

• Logic implementation on nanowires

• External CMOS Control (dynamic) for streaming data

• Cascaded 2-level logic implementation• NAND-NAND logic with single-type FETs

• Built-in fault tolerance techniques

a0

a0

b0

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c0

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c1 s0

c1 s0

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veva

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NA

ND

NAND

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a0

b0

b0

c0

c0

c1 s0

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veva

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NA

ND

NAND

veva

vpre

a0b0c0

VSS

VDD

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VSS VDDDynamic

NAND logic

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preveva eva

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• High Density and Parallelism (NASICs can be 33X denser than projected 16nm CMOS)

• Cheaper Manufacturing• Partial self-assembly based• Fewer Lithography masks• Built-in Hierarchical fault tolerance

• Low Power Consumption• Small capacitances, local interconnects

• Address challenges across device and circuit levels in a tightly integrated fashion• Devices must be tailored to meet

circuit requirements• Circuit simulations must account

for detailed device behavior

• Methodology for integrated exploration developed• Simulations at circuit level built on

accurate 3-D physics based device models

Characterization of xnwFETs using 3D

simulations – Synopsys Sentaurus

Id vs. (Vgs, Vds)

Data

Capacitance vs.

Vgs

Regression analysis

and curve-fit using

DataFit S/W

Behavioral model in HSPICE

Circuit Simulations and Experiments using

HSPICE: Dynamic stages, cascading,

noise evaluation

10 nm

Gate

Material

Top

Dielectric

Channel

Bottom

Insulator

Substrate

• 3D physics based simulations of xnwFET electrostatics

• Capacitance extracted as function of gate voltage

• I-V characteristics tuned using gate underlap and substrate bias• Modulate ION/IOFF ratios• Adjust VTH

Device I-V Characteristics

TABLE 1. Devices Explored

Device

Gate &

channel

NWsNch NG/S/D/Sub Ulap Vsub

#1

10x10nm2 1019 1020

0nm 0V

#2 7nm 0V

#3 7nm -1V

diy

eva1

pre1

dix

diy

eva1

pre1

dix

eva2

pre2

eva3

pre3

do11

do12

do21 do31

Stage1:

Generate

imperfect

outputs

Check Output Integrity at

Stages 2 and 3

Threshold Voltage

DC Sweep Analysis Test Circuit for Cascading and Nois Evaluation

3rd Stage Output

2nd Stage Output

3rd Stage Output

2nd Stage Output

Simulation of Single NASIC Dynamic Stage Noise Evaluation Results

• Regression based methodology for integrated device-circuit explorations presented• Generic methodology, applicable to other fabrics

(e.g. CMOL)

• NASIC dynamic circuits extensively evaluated using accurate 3D physics based device models• xnwFET with 7nm underlap, -1V substrate bias meets

circuit requirements• No new manufacturing challenges

• Future Work• Device/circuit explorations targeting key system level

metrics• Evaluation of performance, power for NASIC architectures

and associated optimizations

• What criteria should a manufacturing pathway for nanodevice based systems achieve?

• Scalability: Large scale simultaneous assembly of nano-structures/nano-devices on a substrate

• Interconnect: Interconnection of nanodevices in prescribed fashion for signal propagation

• Interfacing: for communication with the micro/macro-worlds

• Sequence of steps to realize a computational fabric as a whole• Self-assembly for realizing nanostructures• Lithography for parallel functionalization of devices,

interconnectKey Challenges include growth and alignment of nanowires, nanogrid functionalization

Manufacturing pathway for NASIC 1-bit full adder

Technique Description Pros and Cons

In-situ

Aligned nanowires synthesized directly on substrate (e.g. gas flow, electric field guiding)

No separate transfer required

Concurrent control over all parameters difficult

Dependent on catalyst engineering and patterning, compatibility with substrate

Ex-situ

Nanowires separately grown and then transferred to substrate (e.g. fluidic alignment, organic self-assembly)

Wide variety of material choice and synthesis process

Tighter distribution of diameters

Alignment depends upon ability to pattern the substrate

Nano-lithography based pattern & etch

Pre-formed semiconductor layer is patterned and etched (e.g. NIL, SNAP)

Excellent control over pitch and diameter demonstrated

Choice of material very limited

Only bottom layer of nanowires can use this technique

2p-w

2p

-w

FET

Channel

Protected

RegionMetallized

Crosspoints

What is the smallest feature required?(2×pitch – width) squares, with perfect registration with otherlayersE.g. 20nm pitch and 10nm width requires 30nmX30nm squares

Lithographic requirements are much simpler than CMOS

• Precise shaping or sharp edges not required

• Built-in fault tolerance further ameliorates lithography requirements

• Fewer masks implies lower manufacturing costs

Lithography masks for NASIC functionalization