Preparation and Characterization of CdTe Solar...

95

Chapter 6

Preparation and Characterization of CdTe Solar Cells _____________________________________________________________________

6.1 Solar Cell Basics

A Solar cell is a semiconductor diode that converts sunlight into

electrical energy based on photovoltaic effect. Understanding the

fundamental theory behind the design of solar cells is very important

to fabricate high efficiency solar cells.

6.1.1 The p-n Junction Diode

Fig. 6.1 shows energy band diagram for n-type and p-type

semiconductors [244].

When n-and p-type semiconductors are brought in contact, free

electrons move from n-type to p-type and holes from p-type to n-type.

This movement of charge carriers occurs by diffusion and its direction

is from higher concentration to lower. As the diffusion process

96

proceeds an electric field starts to induce due to the

accumulation of static charges on both sides of the junction. A net

negative charge on the p-side and positive charge on the n-side built

up. This charged area is called the space charge region or depletion

region. The diffusion process stops when the effect of concentration

gradient of carriers is balanced by the electric field at the junction

region. In thermodynamic equilibrium, the Fermi levels in both sides

of the junction are forced to line up, causing the valence and

conduction bands to bend as shown in Fig. 6.2 [244].

This electric field (depletion region) plays a very important role

in the photovoltaic effect. When a light with photon-energy higher

than the band gap is incident on the material, it generates electron-

hole pairs. These extra generated carriers will recombine at the same

rate at which they are generated, unless they are separated by a force-

field. If these carriers can diffuse to the depletion region before they

recombine, then they are separated by the electric field, causing one

quantum of charge to flow through an external load. This is termed as

photovoltaic effect. The current thus produced is termed as photo

current. In a solar cell device, the p-n junction can be a homo-

Preparation and Characterization of CdTe Solar Cells

97

junction (both sides of the junction are made of same material)

or a hetero-junction (two sides of the junction are made of different

materials). Both of them have their own merits and demerits regarding

the design issues of solar cells. Hetero-junction devices have an

inherent advantage over homo-junction devices. Homo-junction

devices require materials that can be doped both p- and n-type. Many

PV materials can be doped to obtain p- or n-type. Consequently,

hetero-junctions allow us to use many promising PV materials that

might otherwise be excluded. For a solar cell the absorption coefficient

and band gap of the absorber layer is very important. Hetero-junction

solar cells have significant advantages in this respect.

In the case of hetero-junction solar cells, a careful material

selection is important to avoid lattice mismatch and interface traps.

However, in the case of CdTe/CdS hetero-junction solar cells, inter-

diffusion across the layers due to CdCl2 activation process helps to

reduce the lattice mismatch. It forms CdTe1-ySy graded ternary layer

and thus helping for the better device performance. CdCl2 activation

process and CdS-CdTe inter-diffusion will be discussed in detail in the

following section. This inter-diffusion can also occur when the CdTe

layer is deposited at high substrate temperature [245]. Fig. 6.3 shows


98

CdTe/CdS hetero-junction energy band diagram before and after

activation [246]. From the point of band alignment CdTe/CdS contact

found to be ideal for solar cell [164]. Neglecting the polycrystalline

nature of CdTe, the important interfaces in the CdTe thin film solar

cell are [164], i) the CdS/TCO front contact which should have a small

barrier in the conduction band for good electron collection, ii) the

CdTe/CdS contact, which should also exhibit a low barrier in the

conduction band and iii) the ohmic back contact.

Fig. 6.4 shows the proposed band energy diagram of a complete

CdTe solar cell based on the experimental results [224].

6.1.2 Physics of Solar Cell Device

General expression for the current produced by an ideal solar

cell is given as [22],

)12/()1/( 0201 −−−−= kTqVeIkTqVeIII SC (6.1) Where, Isc – short circuit current


99

I01 – dark saturation current due to recombination in the

quasi neutral region

I02 – dark saturation current due to recombination in the

space charge region (depletion region)

k – Boltzman’s constant

T – Kelvin temperature

q – magnitute of electron charge

V – applied voltage

This situation is shown in the Fig. 6.5. When the applied voltage

is negative or small the diode current is negligible and the current is

just short-circuit current (i.e., at V=0, I=ISC) and when I=0, all the light

generated current, ISC, is flowing through diode 1, thus the open

circuit voltage can be written as,

01lnII

qkTV SC

OC ≈ (6.2)

where ISC>>I01.

Open-circuit voltage is the voltage at zero current, i.e, the voltage

across the solar cell when there is no load connected.

The open circuit voltage is equal to the difference in quasi-Fermi

levels for electrons and holes between the two sides of the device, and


100

its maximum is determined by the absorber band-gap [247]. Typical

current-voltage curve will be as shown in the Fig. 6.6.

The open circuit voltage is logarithmically proportional to the

short-circuit current and to the reciprocal of the reverse saturation

current, I01 (Eq. 6.2). Therefore, reducing the saturation current will

increase the open-circuit voltage. The design and the operation of an

efficient solar cell have two basic goals: minimization of recombination

rates throughout the device and maximization of the absorption of

photons.

Another defining term in the over all behaviour of a solar cell is

the fill factor (FF). To identify inefficiency in solar cells FF is the most

commonly used parameter. FF is also used to compare the

performance of solar cells. The fill factor is defined as the ratio of the

area of the two rectangles shown in Fig. 6.6.

SCOC

MPMP

SCOC

MP

IVIV

IVPFF

××=

×= (6.3)


101

Solar cell power conversion efficiency, η defined as,

in

SCOC

in

MP

PIVFF

PP ××==η (6.4)

The incident power, Pin is determined by the properties of the light

spectrum incident upon the solar cell. Cell efficiency is a measure of

the amount of usable electric energy that a solar cell produces relative

to the amount of light striking the surface of the solar cell. However

the real solar cell will have parasitic resistance effects namely, series

(Rseries) and shunt resistances (Rshunt) (Fig. 6.7), therefore incorporating

these resistances into the circuit model yields [22],

Shunt

SeriesSeriesSC

RIRVkTAIRVqeIII +−−+−′= )1)/)(( 0

0 (6.5)

Where, I'SC is the short circuit current when there are no parasitic

resistances and A0 is the diode ideality (quality) factor and typically

has value between 1 and 2.

There are several physical mechanisms responsible for these

resistances. Rseries is composed of the bulk resistance of the

semiconductor materials and that of the front and back contacts.

Rshunt is caused by leakage across the p–n junction, grain boundaries

and around the edge of the cell. An ideal cell will have high shunt

resistance (Rshunt = ∞) and low series resistance (Rseries = 0). Modest

Rseries affects mostly the far–forward voltage region above Vmp, but the

open–circuit voltage is not affected by Rseries, because no current flows

at Voc. The influence of Rshunt is visible in the low voltage range (near

zero voltage). Fig. 6.7 shows the effect of Rseries and Rshunt in the solar

cell performance. Both, Rseries and Rshunt can reduce the FF by a

considerable amount (Fig. 6.7). High values of Rseries and low values of

Rshunt can also reduce Jsc and Voc, respectively. For more detailed


102

information regarding the solar cell device physics the reader is

referred to [22, 247, 248].

6.2 Basics of CdTe Device Structure

In general CdTe solar cells are composed of four important

layers, 1) front contact (TCO), 2) window layer (n-CdS), 3) p-CdTe layer

which is absorber layer made on top of CdS and 4) back contact. Thin

film CdTe/CdS hetero-junction solar cells can be fabricated in two

different configurations, referred to as substrate and superstrate[47,

128]. In the substrate configuration, the CdTe film is typically

deposited first on a suitable substrate, followed by sequential

deposition of CdS and the TCO. In the superstrate configuration, the

layer deposition sequence is reversed. The superstrate structure is the


103

most commonly used structure for high efficiency cells [41, 249]. Fig.

6.8 presents SEM cross-section of the real device in superstrate

structure [53].

CdTe solar cells in superstrate configuration require a

transparent substrate because the incident light has to pass through

the substrate before reaching to the CdTe/CdS layers. Any absorption

in the substrate would be detrimental to the current generation of the

cell. Normally glass (soda-lime or borosilicate) is used as substrates

because it is transparent, cheap and withstands relatively high

temperatures.

Numerous articles can be found in the literature regarding the

investigation of superstrate CdTe solar cells. Current status of the

superstrate CdTe research is presented in the following. The TCO

material properties and its requirement for the CdTe solar cell have

been discussed in detail in the chapters 2,4 and 5.


104

Buffer or Window Layer - CdS

In CdTe solar cell device CdS layer is called window layer or

buffer layer. Since direct contact of TCO material with CdTe forms bad

contact for solar cell [132], CdS buffer layer is necessary to prepare

high efficiency CdTe solar cell. CdS thin films have good optical

transmittance and wide band gap of 2.43 eV. CdS thin film is the most

commonly used material in many applications [237]. Normally CdS

films can be deposited by a variety of techniques such as MOCVD

[249], chemical bath deposition (CBD) [250], vacuum evaporation

[251], electro deposition [252, 253], molecular beam epitaxy [254],

sputtering [55, 255] and spray pyrolysis [256, 257]. CBD is proved to

be simple and inexpensive technique to deposit good quality CdS

layers. Highest efficiency of CdTe solar cells was achieved using CdS

layer prepared by CBD [41, 258]. Alternatively, high efficiency CdTe

solar cells can also be prepared by CSS-CdS thin film. In CdTe solar

cell device, light absorption in CdS layer does not contribute to

photocurrent, therefore reduction of CdS film thickness is necessary

to avoid quantum efficiency and short-circuit current losses [54]. But

reducing the film thickness increases the possibility of local shunting

or excessive forward current.

Absorber Layer - CdTe

CdTe absorber layer is deposited on the CdS layer. Several

methods have been used to deposit CdTe, namely vacuum

evaporation, electrodeposition [259], sputtering [260] and CSS [152,

153, 261, 262]. All these techniques are able to produce cells with

efficiency larger than 10%. However, the highest efficiency of (>14%)

with large area solar cells have been prepared by CSS [41, 44, 151,

230, 249, 263, 264]. Due to the low conductivity of the CSS–CdTe

layers, reduced film thickness may result in a low series resistance of

the CdTe film and thus lead to a higher fill factor [153]. Further, to

improve the solar cell performance and to reduce production cost, it is


105

necessary to reduce the CdTe film thickness [164]. But thinner films

(<3 µm) have higher probability for pinholes and shunts which could

considerably reduce the production yield on large area devices. p-type

doping of the CdTe layer will also help to improve device performance.

But, it is difficult to dope CdTe film for the better conductivity [57,

265].

6.2.1 CdCl2 Activation and CdTe/CdS Intermixing

Regardless of the deposition techniques, the so called CdCl2

activation or CdCl2 treatment has become a standard and critical

processing step in fabrication high-efficiency CdTe-based photovoltaic

devices [53, 266]. Prior to back contact formation, the CdCl2 activation

is normally done either by vapour deposition of CdCl2 or by wet

chemical treatment. The vapour CdCl2 treatment involves evaporating

CdCl2 on CdTe and then heating in air at any temperature in the

range of 380-410 °C [152, 267]. The wet chemical CdCl2 treatment

[268] consists of soaking the CdTe films in methanol containing

dissolved CdCl2 and then heating the sample in air atmosphere at

same temperature range. Recent results show that the CdCl2

treatment improves CdTe device performance. However, the effect of

activation of the CdTe film using CdCl2 is not well understood. When

the CdTe/CdS/TCO structure is subjected to CdCl2 heat treatment,

several simultaneous changes occur. Many researchers have analysed

the influence of activation process on the CdS/CdTe layers and the

most important observations are [269-271]:

1. The grain size increases after the CdCl2 -annealing treatment,

especially increase of grain size is more effective for the

smaller grain CdTe layers (re-crystallization)[269].

2. Optical band gap of films become sharper. 3. Non-uniform stress introduced during film deposition is

believed to be relaxed [270].


106

4. There is 10% lattice mismatch between CdS and CdTe.

Activation causes inter-diffusion between the CdS and CdTe

layer and reduces the lattice mismatch between the layers by

forming a graded layer (CdS1-xTex and CdTe1-ySy ) at the

interface[271].

5. Sulfur diffusion due to activation passivates grain boundaries

and relive lattice mismatch between CdS and CdTe and thus

reduces grain boundary recombination.

Furthermore, it has been reported that during the activation

process in the presence of oxygen (air), the oxidation of CdTe results

in formation of CdTeO3, CdTe2O5, CdO and TeO2 [268, 272]. These

native oxides form a low-melting liquid phase [273] and thus playing

essential role in the CdTe re-crystallization process. Therefore the

presence of oxygen during annealing is found to be beneficial.

Diffusion of Te into the CdS layer side forms CdS1-xTex and diffusion of

sulfur into CdTe layer side forms CdTe1-ySy. The formation of CdS1-xTex

and CdTe1-ySy solid alloys (intermixing) at the CdTe/CdS interface is

considered to be crucial for device performance. The extent of

intermixing is based on the chloride concentration, oxygen

concentration in the ambient [274] and the duration of the heat

treatment [274]. In cells, the alloy formation has both beneficial and

detrimental effects. In general intermixing between CdTe and CdS

layers reduces the interfacial strain and thus reduces dark

recombination current [275]. Formation of CdS1-xTex in the CdS base

layer deteriorates the short wavelength optical transmission of the

window. This causes reduction in the CdS window-layer transmission

and lowers the short wavelength quantum efficiency [269, 276]. The

formation of CdTe1-ySy intermediate layer has attracted more attention

in the recent CdTe solar cell research since it has beneficial effects in

solar cell [277-279]. Many research groups have analysed CdTe1-ySy

thin films to understand its properties [280]. This narrows the


107

absorber-layer band gap, resulting in higher long wavelength

quantum efficiency. Also due to inter-diffusion the thickness of CdS

film is reduced [281], which can be beneficial for window

transmission, however non-uniform inter-diffusion can result in

lateral junction discontinuities. The diffusion of CdS into CdTe is

faster process and is more difficult to control, especially for cell

structures with ultrathin, <100nm, CdS films. In addition it has been

reported that inter-diffusion can significantly improve device adhesion

after CdCl2 treatment for the CdTe solar cell with zinc stannate as

buffer layer [101].

6.2.2 Back contact

The back contact material is a metal on the bottom of the

absorber whose role is to collect the carriers from the absorber and

deliver them to the external load. High performance CdTe-based solar

cells require the formation of a low-barrier, low-resistance stable back

contact. Since CdTe has a high electron affinity, many metals will

form a Schottky barrier, resulting in a significant limitation to hole

transport from the p-CdTe. Most commonly a Te-rich surface is

formed by selective chemical etching and then by applying copper or

copper-containing material. Copper will react with Te to form p+ -layer

that can be contacted with a metal or with graphite. Cu acts as a

relatively shallow donor in CdTe and can be diffused into CdTe from a

doped contact material such as graphite paste[151] or ZnTe:Cu [282].

Cu can be incorporated as elemental Cu, followed by a metal or

carbon paint to form the electrode [283]. In general, the back barrier

is minimized, and the VOC is increased, with the application of an

optimal amount of Cu. Doped ZnTe can also be used as a back

contact interface layer for CdTe solar cells [282]. However, such solar

cells with Cu are not suitable for widespread terrestrial applications,

because of a degrading cell performance due to instable Cu containing

back contacts [284, 285]. To avoid this problem a new contact namely,

Sb2Te3, was developed to make better ohmic contact with CdTe [286].


108

Another possibility to form ohmic contact is making highly p-doped

interlayer on top of CdTe layer before metal deposition. This could be

achieved by depositing thin layer of Te on top of CdTe, because Te is

degenerate p-type material with a band gap of 0.33 eV[164, 287].

6.3 CdTe Device Fabrication Three different TCO coated glass substrates were used to

prepare solar cells whose properties were discussed in the chapter 4

and chapter 5. The TCO substrate was cleaned in ultrasonic bath

using soap solution, isopropyl alcohol and de-ionized water. CdS layer

was deposited on these substrates using CSS technique. CdS layer

deposition details are given in chapter 5. CdS layer deposited at 0%

substrate heating power (max. 250 °C) on TCO is named as 0%CdS

layer and similarly for the film deposited with 10% substrate heating

power (max. 540 °C) is named as 10%CdS layer (Table 5.1).

The source and substrate temperature was used as mentioned

in the (Table 5.1) for 0%CdS and 10%CdS. The thickness of the CdS

layer was adjusted by changing the deposition time. The CdS layer

thickness is ~140nm unless otherwise mentioned.

Optimized solar cell preparation parameters (in TU-Darmstadt,

Materials Science Department, Germany) were used for CdTe layer

deposition, CdCl2 activation, etching and back contact to fabricate the

device. Details of these processes are explained in the following

sections.

6.3.1 Deposition of CdTe Layer on CdS/TCO/Glass

After deposition of the CdS layer without breaking the vacuum

the samples were transferred to CSS-CdTe chamber to deposit the

CdTe layer. A substrate temperature of 520 °C was used to deposit the

CdTe layer for all the samples. As the filling of the crucible was

decreasing with increasing number of experiments the source


109

temperature was adjusted to maintain the nominal vapour pressure

as it was measured for a maximum filling [153]. All the layers were

deposited with similar thickness of 5-6µm. Therefore, for a given

source temperature the deposition time had to be accordingly

adjusted. More detailed information regarding the preparation and

nature of CdTe thin films in different growth regimes could be found

in reference [153, 288].

6.3.2 CdCl2 Activation

CdTe/CdS/TCO/Glass structure was dipped into the saturated

CdCl2 solution in methanol and dried. It forms a thin layer of CdCl2 on

top of the CdTe layer. Then the sample was heated in air atmosphere

for 20 minutes at 400 °C and cooled down slowly to room

temperature. After the activation process the sample was

ultrasonically cleaned using distilled water.

6.3.3 Etching and Formation of Back Contact

Since CdCl2 activation is done in air atmosphere, oxide

formation cannot be avoided on the surface of the CdTe layer. Oxides

on CdTe always result in a Fermi level close to the conduction band

minimum, which is unfavourable for contact formation [289].

Therefore the chemical etching procedure with nitric/phosphoric acid

(NP-etch) [290] was employed before making back contact. It helps to

remove the oxide from CdTe surface which is mainly formed during

the activation process. The etching solution consists of 1.3125 ml

HNO3, 70ml H3PO4, and 28ml distilled H2O. CdCl2 activated

CdTe/CdS/TCO/Glass structure was immersed into the etching

solution. Before etching the CdTe surface was dark grey. After a

certain period (8-15 seconds) small bubbles were formed on the film

surface. First some small islands with a silvery grey colour were

formed. These islands expand rapidly, become to contact with each

other and eventually covers the whole surface. At this stage

immediately the sample was taken out and rinsed with distilled water.


110

The samples were dried with nitrogen gas. The complete change of

colour from the dark grey to the silvery grey took place within a few

seconds. The bubbling indicates that the reaction liberates gaseous

by-products [290]. The predicted chemical reactions are [289, 290],

3CdTe(s) + 8HNO3(aq) 3Te(s) + 3Cd(NO3)2(aq) + 2NO(g) + 4H2O (6.6)

∆G(25 °C) = -488kJ/mol

CdTe(s) + 4HNO3(aq) Te(s) + Cd(NO3)2(aq) + 2NO2(g) + 2H2O (6.7)

∆G(25 °C) = -128kJ/mol

Therefore from the equation it is concluded that the formation of

elemental Te layer occurs by preferential etching of Cd. Finally the

back contact is formed by sputtering gold on top of CdTe. The total

area of the sample is 2 × 2 cm2. The sample was structured using a

stainless steel knife and 16 small solar cells of 4 x 4 mm2 were made.

Schematic diagram of the device structure is shown in Fig.6.9.

Fig. 6.10 shows front and back side view of the prepared CdTe

solar cell.


111

6.3.4 Solar Cell Preparation Using Spray Deposited Cadmium Stannate Thin Films

Cadmium stannate thin film with the sheet resistance of 15 Ω⁄

was used to prepare solar cells. 10%CdS layer is deposited on the

Cd2SnO4 thin film. Fig.6.11 shows SEM image of 140nm thick CdS

layer deposited on top of cadmium stannate thin film. 10%CdS is the

optimized standard parameter and hence the solar cells were prepared

only with 10%CdS layer to check the performance of the device with

the spray deposited cadmium stannate films.


112

CdTe layer was deposited on CdS layer without breaking the

vacuum. Fig.6.12 shows that the grains of the CdTe layer are not

uniform. The size of the bigger grain is in the range of 3-4µm and of

the smaller grains in the range of 1-2µm. The CdCl2 activation process

increases the CdTe grain size. The coalescence of small grains into

larger ones was caused by the CdCl2 sintering flux. The over all

increase in grain size by 1µm (Fig.6.12) is observed. Fig.6.13 shows

AFM topograph of the same samples before and after activation. The

morphology and grain size before and after CdCl2 activation is

consistent with SEM observation.


113

Fig. 6.14 shows the J-V characteristics of the best solar cell

device based on the spray deposited cadmium stannate thin film. The

performance of the device is poor. As discussed in the chapter 4 the

Cd2SnO4 layer is not uniform, therefore among the 14 solar cells made

with 2 × 2 cm2 sample, 5 of them are short. The maximum efficiency

of 4.5 % was obtained.

To improve the device performance it is necessary to improve

quality of the cadmium stannate thin film. In addition to this it is

important to use high resistive TCO buffer layer on top of the Cd2SnO4

thin film (for example zinc stannate) to get better device performance

[41].


114

6.3.5 CdTe Solar Cell Device Fabrication Using ITO and ITO/SnO2

CdTe Surface morphology

As-deposited CdTe/CdS/ITO films contain a mixture of smaller

and larger CdTe grains. The size of the larger grains is in the range of

3-4µm (Fig.6.15).

Activation leads to re-crystallization and smaller grains become

larger. CdCl2 acts like a sintering flux in CdTe, small grains grow and

coalesce together [291]. The morphology of the CdTe layer deposited

on 0%CdS and 10%CdS layer is nearly same for the ITO substrate.


115

But for the CdTe layer deposited on 0%CdS/SnO2/ITO has

relatively bigger grains (in the range of 4-5 µm along with small

grains) as compared to 10%CdS/SnO2/ITO (Fig.6.16). After the

activation process the grains become larger than 5µm.

Fig.6.17 shows the SEM image after NP-etching for the sample

shown in Fig. 6.15b. Etching process removes the small CdCl2 crystals

which are formed on top of the grains and the grain boundaries

become clear. The SEM images indicate that depending on the CdS

deposition temperature the grain size of the CdTe layer varies.


116

However the morphology of the grains remains nearly same. AFM

topography of the samples is shown in Appendix B.

In the case of ITO substrates, before depositing the CdTe layer on

CdS, the sample was taken out and CdS surface was cleaned using

hot water or acetone to remove the diffused indium atoms from the

surface of the CdS layer (Fig. 5.8). Also samples were prepared

without cleaning the CdS surface. However, solar cells prepared with

ITO substrate result poor device performance (η= ~2 %) and it is not

reproducible. One of the main reasons for the poor device performance

is attributed to low thickness of the ITO layer.

ITO and SnO2/ITO substrates were purchased from different

vendors. The preparation method for these TCOs is different. The

thickness of ITO layer is ~120nm and for the SnO2/ITO is ~290nm

(40nm/250nm). Hence, it is important to mention here that solar cell

device performance with ITO and SnO2/ITO substrates are not

comparable.

Fig. 6.18 shows the J-V characteristics of the solar cells with

0%CdS and 10%CdS layer with the standard solar cell preparation

procedures using SnO2/ITO substrates. In the case of 0%CdS solar


117

cells, among the 16 cells about half of them were not working. The

maximum efficiency of 7.2% was measured. 10%CdS solar cells

results better device performance with maximum efficiency of 9.5%.

As the grain boundary area for the 0%CdS thin film is larger.

The poor device performance with 0%CdS is attributed to the excess

inter-diffusion between CdS-CdTe and more charge carriers recombine

at the junction. It has been already reported that larger grain

boundary area will increase the diffusion rate and CdS-CdTe

intermixing will be relatively high [271].


118

6.3.6 CdS Double Layer

SEM images show that 10%CdS layer deposited at higher

substrate temperature has relatively larger grains and pin holes as

compared to 0%CdS layer.

However, 10%CdS gives better efficiency with the thickness of

>120nm. Solar cell prepared with 10%CdS film thickness of ~140nm

results η=9.5 % (Fig. 6.18). To improve the solar cell efficiency it is

necessary to reduce the CdS layer thickness [53, 54]. But reducing the

10%CdS layer thickness to ~70 nm reduces the efficiency of the solar

cell to 4.3 % with large number of short cuts. This can be ascertained

due to the presence of pin holes in the thin 10%CdS layer (Fig. 6.19).

.

Nevertheless, an alternative approach has been proposed to

reduce the CdS layer thickness with relatively better surface

morphology and less pin hole defects. Since the 0%CdS layer has

smaller grains, it was expected that depositing very thin 0%CdS (20-

30 nm) layer on top of 10%CdS (50-60 nm) layer may fill the voids and

pin holes. Further, it may lead to optimum CdS-CdTe inter-diffusion

due to larger grain boundary area of 0%CdS. Optimum inter-diffusion

may also reduce lattice mismatch between the CdS and CdTe.

Further, it is expected to reduce the recombination of the charge


119

carriers. Therefore, a modified device structure with CdS double layer

has been proposed to enhance the efficiency.


120

Fig. 6.20 shows the modified device structure. It consists of two

CdS layers (CdS double layer) deposited at high (10%CdS) and low

substrate (0%CdS) temperatures. After depositing the 10%CdS layer

the sample was cooled down to room temperature and then the

0%CdS layer was deposited on 10%CdS layer. The total thickness of

CdS layer is ~70 – 80 nm. A solar cell efficiency of η=11% was

obtained in this structure and the results are reproducible (Fig. 6.21).

The increase in short circuit current is attributed to the reduced CdS

film thickness with improved surface morphology which has relatively

less voids and pin holes. Among the 16 solar cells 6 cells were not

working due to shortcut. This is mainly due to over activation.

However, it cannot be ruled out that there might also be shortcuts due

to mechanical scribing (to make solar cells of 4 × 4 mm2). With the

thinner CdS, inter-diffusion between the CdS-CdTe layers will be fast.

Therefore it is necessary to optimize activation process to get better

results. A good solar cell without any short cuts was prepared by

reducing the CdCl2 activation time from 20min to 15min. Further

optimization of the CdS double layer thickness, CdCl2 activation time

and temperature may result in solar cell efficiency higher than 11%.

6.4 Summary

CdTe solar cells have been fabricated by employing spray

deposited cadmium stannate thin films and the commercial TCO

substrates of ITO and SnO2/ITO films. Device prepared with cadmium

stannate thin films has efficiency of 4.5%. The use of high resistive

buffer layer with cadmium stannate film may also help to increase the

efficiency of the device.

To improve the performance of the cell it is necessary to improve

the cadmium stannate film quality. Since the commercial TCOs of ITO

and SnO2/ITO are purchased from different companies, the glass

thickness and preparation methods are different. Therefore the device

performance based on these TCOs could not be compared.


121

Solar cells prepared using ITO substrates have poor device

performance since the layer thickness of the ITO is not enough for the

device fabrication. The efficiency of solar cells prepared using

CdS/SnO2/ITO with 0%CdS and 10%CdS are η=7.2% and η=9.5%,

respectively. The thickness of the CdS layer is kept ~140nm. Reducing

the 10%CdS layer thickness to ~70nm led to poor device performance

with η=4.8%. But solar cells prepared using the proposed CdS double

layer structure with decreased film thickness (~70-80nm) resulted in a

good device performance (η=11%) with increased short circuit current.

Preparation and Characterization of CdTe Solar...

Documents

Transcript of Preparation and Characterization of CdTe Solar...