Predictive versus Experimental

Approach for the Evaluation of Global

Robustness of Digital Apparatus

Piero Belforte, Paolo Fogliati

Luca Giacomello, Flavio Maggioni CSELT

Luigi Bragagnini Hewlett Packard

Carla Giachino, Emmanuel Leroux High Design Technology

Flavio Canavero Polytechnic of Turin

Outline

• Hardware robustness issues

• Tool requirements for testing hardware robustness

• Validation requirements for predictive tools

• The THRIS environment

• Validation examples

• THRIS application examples

Achieving Hardware Robustness: Key Issues

Hardware design phase

- signal integrity optimization (ringing, crosstalk, ground bounce, power supply distribution analysis), timing problem control

- filtering/shielding optimization (EMI simulations)

- reliability evaluation (components, architectural conceps, thermal analysis)

Hardware/Software Integration phase

- fault insertion, noise injection, experimental EMI precompliance tests

EMC qualification phase

- emission/susceptibility conformity tests

Overall Fault Tolerance Verification phase

- fault insertion

Installation phase

- environment interaction evaluation (grounding, shielding, EMI tests)

Signal Integrity

• Most critical to manage:

– modeling for high speed/EMI

– simultaneous switching noise

• Less critical to manage:

– ringing/reflection control

– propagation delay evaluation

– crosstalk control

References:

A High-Performance Environment for Modelling and Simulation of Digital Systems - 1993 HP

High Speed Digital Systems Design & Test Symposium

Advanced Simulation and Modeling for Telecom System Hardware Design - 1994 HP

ATM/Broadband Design Symposium

Fault Insertion / Noise Injection

– Typical procedure for physical fault insertion:

• put the system in normal operation

• introduce the fault: verify the system behavior (alarms, reconfiguration, etc)

• remove the fault: verify the system behavior (manual/automatic recovery)

Fault Insertion: is a procedure to verify the behavior of an apparatus

in case of hardware faults

Noise Injection: is a procedure to verify noise margins within the

apparatus

Hardware Reliability Prediction

Prediction methodology applicable to existing

products, when complete data about electronic

devices used in the system are available in the CAD

environment

A “parts count” methodology applicable at early stage

of the project, for reliability fast predictions“Early” evaluation

Accurate prediction

Requirements for a Reliable SI/EMI

Simulation

• Accurate modelling techniques

• Real exploitability of the simulation tool:

• powerful simulation engine (speed and complexity

management)

• integrability in the design flow

• customizability

• Experimental validation

Accurate Modelling

A good prediction requires accurate models of components

Data supported by

IBIS standard

Enough for low-speed

(< 100MHz) applications

IBIS

BTM*

+ Necessary for high-speed

( > 100MHz), EMI

* BTM= Behavioral Time Modelling

Why Accurate Models are

Required for EMI Prediction?

Driver waveform spectrum Radiated spectrum

Requirements of the Simulation Tool

• Simulation speed

• Taking into account all the effects at the same time

• Customizability and customer support

• Transparency on the applied methods

Requirements for EMI aspects

• Adequate validation environment

• Knowledge of the physical basis of the predictive algorythm

adopted inside the software

• Knowledge of the occurring EM phenomena

Considerations on the Choice of the

EMI Prediction Method

complex PCB configurations

can be idealized and analyzed

with efficient methods in the

spectral domain

SIMPLIFIED

models leads to

approximations

simple PCB configurations

can be fully analyzed with

rigorous 3D full-wave

methods as MoM, FDTD,

finite elements method

RIGOROUS models require

long computational times

and are difficult to extend

to complex situations

BUT

BUT

A unique method is

not available yet

Numerical method ( PEEC)

where necessary

Analytical formulation

where enough Good trade-off

between accuracy

and simulation time

Solution adopted;

HYBRID METHOD

Considerations on the Choice of the

Method: Possible Solution

Knowledge of the Occurring Phenomena When

Comparing Simulated and Measured Radiated Field

knowledge of the

simulation algorithms limitations

evaluation of the systematic errors of the simulation

Definition of the best

simulation setupsexperience of

the designer +

CSELT’s EMC Laboratory Layout

Objective of an EMC Laboratory

ACCURATEACCURATERIPETIBLERIPETIBLE

TEST ENVIRONMENTTEST ENVIRONMENT

TESTTEST

RESULTSRESULTS REPEATABLE

NSA: Basic Principles

Ideal test site

Semi Anechoic

Chamber (SAC)

NSA: Volumetric Measurement Method

4 m

1 mh1

h2

d

D

Ar

At

30

25

20

15

10

5

0

- 5

- 10

- 15

- 20

NSA

30 40 50 70 90 120 160 200 300 500 700 900

Frequency ( MHz )

5

4

3

2

1

0

-1-2

-3

-4

-5

30 100 200 1000

FREQUENCY [MHz]

DEVIATI

ON [dB

]

THEORETICAL NSA OF AN IDEAL SITE SAC MEASURED NSA

SAC PerformanceMeasured NSA

Commonality Requirements

The tool must implement a common test

methodology for both manufacturers and their

clients

- design and integration tool for manufacturers

- incoming qualification and quality monitoring tool for clients

THRIS

• Hardware/Software test environment

• Hardware: standard workstation, standard instrumentation.

Partner: HP

• Software: integration/customization of commercial software for both

predictive and experimental issues.

• Custom Front-end (CSELT patented)

• THRIS validation is performed in CSELT laboratories

• New specifications from THRIS User Group (TUG)

• During „97: New functionalities added (reliability,thermal,EMC)

THRIS Functionalities (today)

• Modeling environment (including TDR)

• Signal integrity prediction

• EMI prediction (radiated/conducted emission,conducted susceptibility)

• EMI performance optimization (What-If analysis)

• Reliability evaluation (RAPSODIA, METRICA)

• Fault injection (pin forcing technique)

• Noise injection

• Electrical/thermal monitoring

• EMI precompliance analysis (near-field, common mode currents,

conducted susceptibility)

Some THRIS Validation Examples

- Radiated emissions (differential/common modes)

- Conducted susceptibility

- Fault insertion

- Noise injection

Radiated Emission Tool Validation(Test vehicle #1)

Top view

Bottom view

Copper tape

Termination

Shielded oscillator

Battery

pack

Oscillator PCB

50 ohm coax cableConnector

Line length = 20 cm

Line imped. = 50 ohm

pcb thickness=1.6mm

Er = 4.5

PCB size = 20x30 cm

Ground plane

ECL Oscillator Model

GND

Package

VoSTF DTF

S_param

Output stage of the

ECL driver

V

I

Logic “1”

Logic “0”

Constant R

zone

Varying R

zone

Static VI characteristic

-1

-0.85

Dynamic characteristic

Equivalent Thevenin

circuit of the driver

Validation of ECL Oscillator Model

Comparison between the spectra of

measured and simulated output

waveform V(2) of the ECL driver

with a 50ohm termination

50

1 2

V(2)Vo

S param.

Electrical model

of the ECL driver

0

20

40

60

80

100

120

68

,8

20

6,4

34

4

48

1,6

61

9,2

75

6,8

82

5,6

frequency [MHz]

dB

uV

/m

simulation

measure

10 m

h

H

shielded

oscillator

Typical Measurement Set-up

H=1m

h=1-4m with a 0.5m step

ECL shielded oscillator

Microstrip load = open

Frequency [MHz] Measurements [dBuV/m] Simulation [dBuV/m]

68,8 22,47 21,67

206,4 37,38 35,87

344 41,73 42,22

481,6 38,61 38,40

619,2 31,88 35,60

756,8 32,61 30,05

894,4 N.A.* 26.82

Comparison Between

Measurements and Simulations

H

h

frequenza misura simulazione mis+4 mis-4 misura

68,8 22,47 21,67 22,47

206,4 37,38 35,87 41,38 33,38 37,38

344 41,73 42,22 45,73 37,73 41,73

481,6 38,61 38,40 42,61 34,61 38,61

619,2 31,88 35,60 35,88 27,88 31,88

756,8 32,61 30,05 36,61 28,61 32,61

894,4 26,7 2,4

Esempio in cui:

0

10

20

30

40

50

68,8

206

,4

344

481

,6

619

,2

756

,8

894

,4

Freq(MHz)

dB

uV

/m

simulation

measure

* Measure under noise level

Common Mode Case Study: PCB alone

H=1.36m

h=1-4m with a 0.5m step

CMOS 10MHz shielded oscillator

Microstrip load = open

Antenna polarization = horizontal

Hh

0,00

5,00

10,00

15,00

20,00

25,00

30,00

35,00

50

60

70

80

90

10

0

11

0

12

0

13

0

14

0

15

0

16

0

17

0

18

0

frequency [MHz]

dB

uV

/m

simulationmeasure

frequency (MHz) Simulation Measurement

50 10,30 12,23

70 18,64 20,01

90 21,52 21,82

100 22,83 23,76

120 27,15 31,71

140 35,92 36,27

160 34,29 29,98

180 34,04 28,24

H=136cm

h=1-4m with a 0.5m step

CMOS 10MHz shielded oscillator

microstrip load = open

Cable length = 60cm

Cable termination = open

Antenna polarization = horizontal

0,00

5,00

10,00

15,00

20,00

25,00

30,00

35,00

40,00

50 70 90 110

130

150

170

frequency [MHz]

dB

uV

/m

Hh

simulation

measure

Common Mode Case Study: PCB + attached cable

Susceptibility Analysis Example

+

-

P1_8

P3_2

P3_8

P3_1

U1

Distributed ground

5

6

N

Measurement Setup

Power

splitterHP8648Cadded ground plane

TR3 2 1

HP54750 DSO

TD

R

flexible coax. cable

PCB under test

Measurement/Simulation Comparison

25.00 25.50 26.00 26.50 27.00 27.50 28.00 28.50 29.00 29.50 30.00 TIME[nS]-200.00

-150.00

-100.00

-50.00

0.00

50.00

100.00

150.00

200.00V [mV]U1_6 meas.

U1_6 simul.

U1_5 simul. U1_5 meas.

900MHz residual noise on comparator inputs

Pin Forcing: Why Simulation is Needed

Driver Receivers

3

12

1 cm

Actual signal at location 1

and 2 in normal conditions

0TIME[nS]

-2 V-1 V0 V

1 V

2 V3 V

4 V

5 V

6 V

7 V

10 20 30 40 50 60

0TIME[nS]

-1 V

0 V1 V

2 V

3 V

4 V

5 V

6 V

7 V

10 20 30 40 50 60

Residual noise measured at

location 1 and 2 when a THRIS

stuck_at_0 is applied in 1Actual signal at location 1 and 2

after one inverter stage

location 1

location 2

location 1

location 2

10 20 30 40 50 600-1 V0 V1 V2 V3 V4 V5 V6 V7 V

TIME[nS]

Pin Forcing: High Speed Systems

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

TIME[uS]

-1.30 V

-1.30 V

-1.30 V

-2.00 V

0.00 V

-2.00 V

0.00 V

-2.00 V

0.00 V

-2.00 V

0.00 V

FAULT CONTROL

ON OFFOFF ON

STM1 INPUT STREAM (155 Mbit/s)

FAULTY NODE (FIRST STAGE OUTPUT)

FAULTY OUTPUT STREAM

32 155Mbit/s

output streams

32 155Mbit/s

input streams

Fault

Stage A Stage B Stage C

Description:

3 Boards + backplane

32 155Mbit/s streams

6 16x16 switching matrices

THRIS simulation model:

50000 circuit elements

35000 nodes

20000 timepoints

20‟ simulation time on typ. ws.

Noise Injection: Noise Margin Evaluation

0.0 2.0 4.0 6.0 8.0 10.0 12.0

TIME[nS]

-1.9 V

-1.7 V

-1.5 V

-1.3 V

-1.1 V

-0.9 V

-0.7 V

-0.5 V

0.0 2.0 4.0 6.0 8.0 10.0 12.0

TIME[nS]

-1.9 V

-1.7 V

-1.5 V

-1.3 V

-1.1 V

-0.9 V

-0.7 V

-0.5 V

0.0 2.0 4.0 6.0 8.0 10.0 12.0

TIME[nS]

-1.9 V

-1.7 V

-1.5 V

-1.3 V

-1.1 V

-0.9 V

-0.7 V

-0.5 V

Normal operation

5mA current injection

12mA current injection

ecl interconnection

N

output testpoint

Pre-compliance Near-Field Testing

HP 8590EM EMC Analyzer

PreamplifierHP-IB cable

to THRIS

ROM card

Near field probe

DUT

Pre-compliance Common Mode

Current Testing

HP8590EM EMC Analyzer

PreamplifierHP-IB cable

to THRIS

ROM card

CABLE

UNDER

TEST

HP 11967A

Thermal Monitoring

Conclusions

• EMI behavior of electronic equipment must be optimized in early design

stage. Simulation is the key.

• The simulation tool should be accurately validated versus measurements in

suitable site (e.g. accreditated EMC labs).

• Reliable EMI simulations require accurate SI models based on wide -band

measurements on components (e.g.: TDR, network analyzer, ecc).

• Measurements are still mandatory for the certification phase. If some

problems are detected, corrective actions can be experimented by means of

simulation (e.g. What-if analysis)

• Specific EMI measurements executed after installation can identify

problems due to the environment impact, even if the device under test has

been already certified.

THRIS Solutions

THRIS_SI

THRIS_IG

THRIS_EMC

Designers, R&D

engineers

Hardware/software

system integration

engineers

Designers, R&D

engineers, EMC

specialists

Optimized design,

redesign cycle reduction

Increased tests

coverage,

increased system level

robustness

EMI problems found and

fixed at design stage

WHO BENEFITS

THRIS Resources

THRIS_SI THRIS_IG THRIS_EMC

Workstation x x x

VEE x x

VXI, Front_end x

EMC instruments x

THRIS manager x x x

Fault insertion test suite x

Post-layout analysis package x x x

Crosstalk, bouncing analysis x

EMI radiated emissions analysis x

What-IF analysis opt. opt. opt.

Modeling development suite opt. opt.

THRIS Application Example

Design of a high speed board (ATM switch)

THRIS Application Example

Fault injection probes

THRIS Application Example

Qualification trials on a digital exchange

THRIS Application Example

Design verification of a telecom auxiliary apparatus

THRIS Application Example

Fault insertion trials on a SDH apparatus

THRIS Application Example

Signal monitoring inside a public telecom terminal