Practicals SEM I
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Transcript of Practicals SEM I
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 1/22
Q1> All Logic gates – And,OR,NOT,NAND,NOR XOR & XNOR.---------------------------------------------------- AND gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune--------------------------------------------------library ieee;use ieee.std_logic_1164.all;
--------------------------------------------------entity AND_ent isport( x: in std_logic;
y: in std_logic;F: out std_logic
);end AND_ent;--------------------------------------------------architecture behav1 of AND_ent isbegin
process(x, y)begin
-- compare to truth tableif ((x='1') and (y='1')) then
F <= '1';else
F <= '0';end if;
end process;end behav1;
architecture behav2 of AND_ent isbegin
F <= x and y;
end behav2;
--------------------------------------------------
Waveform simulation :
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 2/22
---------------------------------------------------- OR gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune--------------------------------------------------library ieee;use ieee.std_logic_1164.all;--------------------------------------
entity OR_ent isport( x: in std_logic;
y: in std_logic;F: out std_logic
);end OR_ent;---------------------------------------architecture OR_arch of OR_ent isbegin
process(x, y)begin
-- compare to truth tableif ((x='0') and (y='0')) thenF <= '0';
elseF <= '1';
end if;end process;
end OR_arch;
architecture OR_beh of OR_ent isbegin
F <= x or y;
end OR_beh;
--------------------------------------- Waveform simulation :
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 3/22
---------------------------------------------------- NOT gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune--------------------------------------------------
--import std_logic from the IEEE librarylibrary ieee;use ieee.std_logic_1164.all;
----------------------------------------------------ENTITY DECLARATION: name, inputs, outputsentity notGate is
port( x: in std_logic;F: out std_logic);
end notGate;
----------------------------------------------------FUNCTIONAL DESCRIPTION: how the NOT worksarchitecture func of notGate isbegin
F <= x;end func;
------------------------------------------------------
Waveform simulation :
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 4/22
--------------------------------------------------- NAND gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune--------------------------------------------------library ieee;use ieee.std_logic_1164.all;
------------------------------------------entity NAND_ent isport( x: in std_logic;
y: in std_logic;F: out std_logic
);end NAND_ent;
------------------------------------------
architecture behv1 of NAND_ent isbegin
process(x, y)
begin-- compare to truth tableif (x='1' and y='1') thenF <= '0';
elseF <= '1';
end if;end process;
end behv1;
-----------------------------------------architecture behv2 of NAND_ent isbegin
F <= x nand y;
end behv2;
----------------------------------------- Waveform simulation:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 5/22
---------------------------------------------------- NOR gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune--------------------------------------------------library ieee;use ieee.std_logic_1164.all;--------------------------------------------------
entity NOR_ent isport( x: in std_logic;
y: in std_logic;F: out std_logic
);end NOR_ent;--------------------------------------------------architecture behv1 of NOR_ent isbegin
process(x, y)begin
-- compare to truth table
if (x='0' and y='0') thenF <= '1';else
F <= '0';end if;
end process;
end behv1;--------------------------------------------------architecture behv2 of NOR_ent isbegin
F <= x nor y;
end behv2;--------------------------------------------------
Waveform simulation:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 6/22
-------------------------------------------- XOR gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune------------------------------------------library ieee;use ieee.std_logic_1164.all;
--------------------------------------entity XOR_ent isport( x: in std_logic;
y: in std_logic;F: out std_logic
);end XOR_ent;--------------------------------------
architecture behv1 of XOR_ent isbegin
process(x, y)
begin-- compare to truth tableif (x/=y) then
F <= '1';else
F <= '0';end if;
end process;
end behv1;
architecture behv2 of XOR_ent isbegin
F <= x xor y;
end behv2;--------------------------------------
Waveform simulation:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 7/22
-------------------------------------------- XNOR gate -- two descriptions provided-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune------------------------------------------
library ieee;use ieee.std_logic_1164.all;
--------------------------------------entity XNOR_ent isport( x: in std_logic;
y: in std_logic;F: out std_logic
);end XNOR_ent;
---------------------------------------architecture behv1 of XNOR_ent isbegin
process(x, y)
begin-- compare to truth tableif (x/=y) then
F <= '0';else
F <= '1';end if;
end process;
end behv1;
architecture behv2 of XNOR_ent isbegin
F <= x xnor y;
end behv2;---------------------------------------
Waveform simulation:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 8/22
-------------------------------------------- Full Adder-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-- function of adder:-- A plus B to get n-bit sum and 1 bit carry-- we may use generic statement to set the parameter
-- n of the adder.
--------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;
--------------------------------------------------------
entity ADDER is
generic(n: natural :=2);port( A: in std_logic_vector(n-1 downto 0);B: in std_logic_vector(n-1 downto 0);carry: out std_logic;sum: out std_logic_vector(n-1 downto 0)
);
end ADDER;
--------------------------------------------------------
architecture behv of ADDER is
-- define a temparary signal to store the result
signal result: std_logic_vector(n downto 0); begin
-- the 3rd bit should be carry
result <= ('0' & A)+('0' & B);sum <= result(n-1 downto 0);carry <= result(n);
end behv;
--------------------------------------------------------
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 9/22
Schematic of Full Adder:
Waveform simulation:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 10/22
-------------------------------------------------------- Full Subrtactor-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-------------------------------------------------------
library IEEE;use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------entity full_sub isport ( res, borrow_out: out std_logic;
a, b, borrow_in: in std_logic);
end entity full_sub;
-------------------------------------------------------
architecture full_sub_behave of full_sub is
signal sub_res : unsigned (1 downto 0);
beginsub_res <= ('0' & a) - ('0' & b) - (b"0" & borrow_in);borrow_out <= sub_res(1);res <= sub_res(0);
end architecture full_sub_behave;
-------------------------------------------------------
Schematic of Full Subtractor:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 11/22
Waveform simulation for full subtractor:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 12/22
-------------------------------------------------------- 4:1 multiplexor-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-- Multiplexor is a device to select different-- inputs to outputs. we use 3 bits vector to-- describe its I/O ports-------------------------------------------------
library ieee;use ieee.std_logic_1164.all;
-------------------------------------------------
entity Mux isport( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);I1: in std_logic_vector(2 downto 0);I0: in std_logic_vector(2 downto 0);S: in std_logic_vector(1 downto 0);O: out std_logic_vector(2 downto 0)
);end Mux;
-------------------------------------------------
architecture behv1 of Mux isbegin
process(I3,I2,I1,I0,S)begin
-- use case statementcase S is
when "00" => O <= I0;when "01" => O <= I1;
when "10" => O <= I2;when "11" => O <= I3;when others => O <= "ZZZ";
end case;
end process;end behv1;
architecture behv2 of Mux isbegin
-- use when.. else statementO <= I0 when S="00" else
I1 when S="01" elseI2 when S="10" elseI3 when S="11" else"ZZZ";
end behv2;--------------------------------------------------
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 13/22
Schematic of 4:1 multiplexor:
Waveform simulation for 4:1 multiplexor :
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 14/22
-------------------------------------------------------- 2:4 Decoder-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-- decoder is a kind of inverse process-- of multiplexor-------------------------------------------------
library ieee;use ieee.std_logic_1164.all;
-------------------------------------------------
entity DECODER isport( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0));end DECODER;
-------------------------------------------------
architecture behv of DECODER isbegin
-- process statement
process (I)begin
-- use case statement
case I iswhen "00" => O <= "0001";when "01" => O <= "0010";when "10" => O <= "0100";
when "11" => O <= "1000";when others => O <= "XXXX";
end case;
end process; end behv;
architecture when_else of DECODER isbegin
-- use when..else statement
O <= "0001" when I = "00" else"0010" when I = "01" else"0100" when I = "10" else"1000" when I = "11" else"XXXX";
end when_else;
--------------------------------------------------
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 15/22
Schematic of 2:4 Decoder:
Waveform simulation for 2:4 Decoder:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 16/22
-------------------------------------------------------- 4-bit counter-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-- this is the behavior description of 4-bit counter-- another way can be used is FSM model.----------------------------------------------------
library ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
port( clock: in std_logic;clear: in std_logic;count: in std_logic;Q: out std_logic_vector(3 downto 0)
);end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(3 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
beginif clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;elsif (clock='1' and clock'event) then
if count = '1' thenPre_Q <= Pre_Q + 1;
end if;end if;
end process;
-- concurrent assignment statementQ <= Pre_Q;
end behv;
-----------------------------------------------------
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 17/22
Schematic of Counter:
Waveform simulation for Counter:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 18/22
-------------------------------------------------------- D Flip-Flop-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-- Flip-flop is the basic component in-- sequential logic design-- we assign input signal to the output-- at the clock rising edge
------------------------------------------------------library ieee ;use ieee.std_logic_1164.all;use work.all;---------------------------------------------entity dff isport( data_in: in std_logic;clock: in std_logic;data_out: out std_logic
);end dff;----------------------------------------------architecture behv of dff is
beginprocess(data_in, clock)begin
-- clock rising edge
if (clock='1' and clock'event) thendata_out <= data_in;
end if;
end process;
end behv;----------------------------------------------
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 19/22
Waveform simulation for D Flip-Flop:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 20/22
-------------------------------------------------------- JK Flip-Flop with reset-- Author - Jeetendra.L.Singh-- Roll No: 9 ; DPCE - Pune-- the description of JK Flip-Flop is based-- on functional truth table-- concurrent statement and signal assignment-- are using in this example
----------------------------------------------library ieee;use ieee.std_logic_1164.all;----------------------------------------------entity JK_FF isport ( clock: in std_logic;
J, K: in std_logic;reset: in std_logic;
Q, Qbar: out std_logic);end JK_FF;-----------------------------------------------architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;signal input: std_logic_vector(1 downto 0);
begin -- combine inputs into vector
input <= J & K;
p: process(clock, reset) isbegin
if (reset='1') then
state <= '0';elsif (rising_edge(clock)) then
-- compare to the truth tablecase (input) is
when "11" =>state <= not state;
when "10" =>state <= '1';
when "01" =>state <= '0';
when others =>null;
end case;end if;
end process;
-- concurrent statementsQ <= state;Qbar <= not state;
end behv;-------------------------------------------------
7/30/2019 Practicals SEM I
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Waveform simulation for JK Flip-Flop:
7/30/2019 Practicals SEM I
http://slidepdf.com/reader/full/practicals-sem-i 22/22