Power Management Reference Guide for Altera FPGAs and CPLDs · Field Programmable Gate Arrays...

Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD)

Power Management Reference Guidefor Altera® FPGAs and CPLDs

4Q 2004

R E A L W O R L D S I G N A L P R O C E S S I N GTM

Powering Your FPGAs/CPLDs With TI’s Power Management Products

FPGA/CPLD

DC/DCConverters

DC/DCConverters

DC/DCConverters

Supply VoltageSupervisor

SD RAMand

DATA CONV.

VCCINT

VCCIO

Input

Supply

Power Design Library 2

Stratix™ IIStratix® GXStratix™

Cyclone™

Max® II

Altera Power Requirements 3

Recommended DC/DC Converters 4

Product Selection Guides 20-21

Active Bus Termination 22-23

Inside➔

www.ti.com/alterafpga

Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide

2 Power Management FPGA and CPLD Reference Guide

TI’s Power Management Reference Designs for Altera FPGAs and CPLDs

2

Design Library

➔

Complete schematics, bills of materials and additional designs available at:www.ti.com/alterafpga

Questions? [email protected]

Important Design Considerations..............................................................................................................................................................................................................5

Stratix II FPGA Core and I/O Power Solutions

3.3-V or 5-V Input Supplies

6-A Core and I/O (Two TPS54610 DC/DC Converters) Solution; 8-A, 9-A Adaptable ....................................................................................................................................5

6-A Core and I/O (Two PTH05050 Modules) Solution; 10-A, 15-A, 22-A, and 30-A Adaptable ....................................................................................................................6

20-A Core (TPS40007 DC/DC Controller) and 6-A I/O (TPS54610 DC/DC Converter) Solution; 8-A, 9-A I/O Adaptable ..............................................................................6

12-V Input Supplies

26-A Core (PTH12030 Module) and 12-A I/O (PTH12010 Module) Solution; 6-A, 10-A, 18-A Adaptable.....................................................................................................7

15-A Core and I/O (Two TPS40055 DC/DC Controllers) Solution ..................................................................................................................................................................7

Stratix GX/Stratix/Cyclone FPGA Core and I/O Power Solutions


800-mA Core and I/O, Dual Low Dropout (LDO) Linear Regulator (TPS70402) Solution................................................................................................................................8

1-A Core and I/O, Independent LDOs (Two TPS725xxs) Solution ..................................................................................................................................................................8

1.5-A Core (TPS54110 DC/DC Converter), 1.5-A I/O (TPS786xx LDO) Solution; 3-A Core Adaptable ...........................................................................................................9

3-A Core (TPS64203 DC/DC Controller), 1.5-A I/O (TPS78633 LDO) Solution................................................................................................................................................9

3-A Core and I/O (Two TPS64203 DC/DC Controllers) Solution ...................................................................................................................................................................10

6-A Core and I/O (Two TPS54610 DC/DC Converters) Solution; 8-A, 9-A Adaptable ..................................................................................................................................10

6-A Core and I/O (Two PTH05050 Modules) Solution; 10-A, 15-A, 22-A, 30-A Adaptable .........................................................................................................................11

20-A Core and I/O (Two TPS40021 DC/DC Controllers) Solution .................................................................................................................................................................11

12-V Input Supplies

3-A Core and I/O (Two TPS54350 DC/DC Converters) Solution....................................................................................................................................................................12

6-A Core and I/O (Two PTH12050 Modules) Solution; 10-A, 12-A, 18-A, 26-A Adaptable .........................................................................................................................12

15-A Core and 10 A I/O, (Two TPS40055 DC/DC Controllers) Solution........................................................................................................................................................13

Stratix II VCCPD Power Solution

TPS73633 LDO Solution.................................................................................................................................................................................................................................13

PLL and Transceiver Power Solutions

Stratix II/Stratix GX/Stratix PLL Supply.........................................................................................................................................................................................................14

Cyclone PLL Supplies .....................................................................................................................................................................................................................................14

Stratix II/Stratix GX/ Stratix PLL OUT Supply ...............................................................................................................................................................................................15

Stratix GX Transceivers Supplies...................................................................................................................................................................................................................15

Max II CPLD Power Solutions


150-mA Core and I/O (Two TPS731xx LDOs) Solution; 250-mA, 400-mA Adaptable...................................................................................................................................16

1.5-A LDO (TPS78633) Powering Both Core and I/O.....................................................................................................................................................................................16

400-mA Core (TPS736xx LDO) and 1.2-A I/O (TPS62042 DC/DC Converter) Solution..................................................................................................................................17

12-V Input Supplies

3-A DC/DC Converter (TPS54350) Powering Both Core and I/O...................................................................................................................................................................17

Appendices

Texas Instruments Power Management Products Selection Guide..............................................................................................................................................................20

Active Bus Termination Solutions (DDR/QDR/GTL/SSTL/HSTL) ...................................................................................................................................................................22

Stratix II FPGA Power Requirements1

VCCINT (core voltage) 1.15 V min, 1.2 V typ, 1.25 V max ICCINT (core current) EP2S15: 5 A maxInrush to start-up included EP2S30: 7 A max

EP2S60: 9 A maxEP2S90: 11 A maxEP2S130: 15 A maxEP2S180: 20 A max

VCCPD (internal buffer voltage) 3.3 V typ, 300 mA maxICCIO (input/output voltages) 3.3 V, 2.5 V, 1.8 V and/or 1.5 V ICCID (input/output current) Up to 8 I/O banks @ up to 1.25 A eachTransient Response Requirements VCCINT shall remain within 1.15 V to 1.25 V

under these transient conditions:ICCINT < 8 A, load transient - 25% of ICCINT/µsICCINT ≥ 8 A but <12 A, load transient - 4 A/µsICCINT ≥ 12 A, load transient - 2 A/µs

VCCD_PLL 1.15 V min, 1.2 V typ, 1.25 V maxVCC_PLL_OUT 3.3 V, 2.5 V, 1.8 V, and/or 1.5 V ICC_PLL_OUT 50 mA (max)Digital(2) voltages above Analog voltages belowVCCA_PLL 1.15 V min, 1.2 V typ, 1.25 V max ICC_PLL 200 mA max per PLL,

Up to 12 each with separate VCC and GNDStratix and Stratix GX FPGA Power RequirementsVCCINT (core) 1.5 V ± 5%ICCINT (core) 250 mA to 10 AICCINT inrush to start-up EP1S10, EP1SGX10: 250 mA typ, 700 mA max

EP1S20: 400 mA typ, 1,200 mA maxEP1S25, EP1SGX25: 500 mA typ, 1,500 mA maxEP1S40, EP1SGX40: 650 mA typ, 2,300 mA maxEP1S60: 800 mA typ, 2,600 mA maxEP1S80: 1,000 mA typ, 3,000 mA max

VCCIO (I/O) 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICCIO (I/O) Up to 8 I/O banks @ 50 mA to 1.5 A eachVCC_PLL_OUT 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICC_PLL_OUT 50 mA (max)Digital2 voltages above Analog voltages belowVCCA_PLL 1.5 V ± 5%ICC_PLL 200 mA (max) per PLL

Up to 12 each with separate VCC and GND

33

➔

➔


Power Management FPGA and CPLD Reference Guide

Introduction

Texas Instruments (TI) works closely with Altera to recommend robust power solutions. On this page you will find a summary of the FPGA/CPLDpower requirements. On page 3 is a comprehensive library of power designs. A listing of the TI DC/DC converter products that have been testedand endorsed by Altera® to power the listed devices is on page 4; schematics begin on page 5. Complete schematics and bill of materials(BOMs) are available at www.ti.com/alterafpga. Please send questions to [email protected].

This information is intended to provide the designer with a general understanding of the power requirements of Altera FPGA/CPLD families in typical applications. Please refer to the Altera Power Estimators, available at www.altera.com, for closer approximations specific to individualFPGA/CPLD devices and applications.

Power Requirements of Altera FPGAs and CPLDs

Additional Stratix GX Power RequirementsDigital Transceiver Voltage: VCCP, VCCG 1.5 V ± 5%ICC_Transceiver 250 mA (max) per transceiver

4 transceivers per blockUp to 5 blocks per device

Analog Transceiver Voltage: VCCR, VCCT 1.5 V ± 5%ICC_Transceiver 250 mA (max) per transceiver

4 transceivers per blockUp to 5 blocks per device

Analog Transmitter Voltage: VCCAQ 3.3 V ± 5%50 mA (max) per transceiver block

Cyclone FPGA Power RequirementsVCCINT (core) 1.5 V ± 5%ICCINT (core) 300 mA to 5 AICCINT inrush to start-up EC1C3: 300 mA max

EP1C4: 400 mA maxEP1C6: 500 mA maxEP1C12: 900 mA maxEP1C20: 1,200 mA max

VCCIO (I/O) 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICCIO (I/O) Up to 4 I/O banks (50 mA to 1.5 A each)Digital(2) voltages above Analog voltages belowVCCA_PLL (two) 1.5 V ± 5%ICC_PLL 200 mA (max) per PLLMax II CPLD Power RequirementsVCCINT (core voltage) 2.375 V min, 2.5 V typ, 2.625 V max(2.5 V or 3.3 V supported on all Max II 3.00 V min, 3.3 V typ, 3.6 V maxwithout “G” ordering code. 1.8 V 1.71 V min, 1.8 V typ, 1.89 V maxsupported with “G” ordering code.)ICCINT (core current) EPM240: 30 mA typ, 75 mA max

EPM570: 40 mA typ, 125 mA maxEPM1270: 55 mA typ, 250 mA maxEPM2210: 75 mA typ, 400 mA max

ICCINT (inrush to start-up) 65 mA maxICCSTANDBY 12 mA typVCCIO (input/output voltages) 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICCIO (input/output current) 25 to 50 mA each typ, 75 to 225 mA each max(up to 4 I/O banks)

1Stratix II advance information is based on Altera’s initial characterization of silicon, as of August 2004.2Digital voltages can be powered by linear or switching DC/DC converters. Linear regulators are recommended for analog voltages, for minimal noise.

4 Power Management FPGA and CPLD Reference Guide

TI Recommended DC/DC Converters For Powering Altera FPGAs and CPLDs➔

➔


Complete schematics available at: www.ti.com/alterafpga

DC/DC Converter Selection Considerations

These recommended DC/DC converter products have been tested and endorsed by Altera to power the listed FPGAs. Max II CPLDrecommendations are preliminary pending testing. Digital voltages can be powered by either linear or switching DC/DC regulators. Linear regulators are recommended for analog voltages, for minimal noise. Please see the selection guides on pages 20 and 21 for electrical specifics of the recommended devices.

Stratix GXFPGA

Stratix IIFPGA

StratixFPGA

CycloneFPGA

Max IICPLD

compensation, resulting in a smaller solution due to the ability to minimize the inductor and use ceramic capacitors

- Exhibit switching noise- Up to 95% efficient, giving a much cooler solution than

a linear regulator, but due to the power dissipation inthe internal FETs, switching DC/DC converters supportonly up to about 9 A

• Switching DC/DC Controllers

- More cost-effective than DC/DC converters, but consume more board space and are more challenging to implement as they require the addition of externalFETs

- Can support high-current applications, limited only by the controller’s drive and the external FET’s powerdissipation capabilities

• Modules

- Easiest switching DC/DC solution available. The modulesolution is complete, needing only the addition of aninput and output capacitor for increased transientresponse

- Double-sided modules save board space- Full environmental qualification and EMI reports

are available

• Low Dropout (LDO) Linear Regulators

- Easiest, smallest, and most cost-effective type of DC/DCconverter to implement

- Typically just require the addition of a small inputcapacitor and output capacitor for stability

- Exhibit low noise and therefore are ideal for poweringanalog voltages

- Recommended for low power applications only due togenerally low efficiency (LDO Eff = VOUT/VIN x 100%) andresulting heat. Ensure the application does not violatethe regulator’s maximum allowable power dissipation.Refer to TI Application Note SLVA118 ‘Digital Designer’s

Guide to Linear Voltage Regulators and Thermal

Management’ for guidance.- Low dropout performance needed to support small

VIN to VOUT voltage differential

• Switching DC/DC Converters

- Easiest, smallest, discrete IC, switching DC/DC solutionto implement due to integration of the FETs

- Require the addition of an inductor and capacitors forthe output filter

- Use fixed output voltage, internally compensateddevices to minimize component count and simplifyimplementation

- Using adjustable output voltage TPS54xxx devicesinstead of fixed output options allows for external

Digital Voltages Analog VoltagesLow Dropout Switching Switching Low Dropout(LDO) DC/DC Converters DC/DC Controllers Switching (LDO) Linear Regulators (Integrated FET) (External FET) DC/DC Modules Linear Regulatorsto 1.5 A to 9 A to 20A to 30 A to 1.5 A

TPS79xxx TPS79xxxTPS786xx TPS54xxx TPS6420x PTH Series TPS786xxTPS725xx TPS400xx TPS732/6xxTPS703/4xx




TPS736xx TPS62042 Max II is low power. Max II does not haveTPS786xx TPS54xxx LDOs and Switching Converters are recommended. Analog Supplies


Important Design Considerations 5

➔

Stratix II 6-A Core and I/O3.3-V or 5-V Input DC/DC Converters (Two TPS54610) Solution ➔

• Highly efficient VCCINT railsup to 6 A

• Drop-in replacement of U1/U2 with TPS54810 orTPS54910 (VIN = 3.3 V) gives 8-A or 9-A solution, respectively

• SWIFT™ (Switcher withIntegrated FET) TPS54610adjustable design allows:•• Use of smaller inductor,

ceramic capacitors•• Flexibility to recompensate

depending on thebulk/bypass capacitorsused for the FPGA

• Fixed TPS5461x output voltage options available

• SWIFT design software isavailable for further customization

• UVLO and integrated soft-start of U1/U2 eliminate the need for an external SVS to monitor the input voltage• Sequencing of VCCINT, then VCCIO, then PLL minimizes the demand on the input supply• Additional rails easily added and sequenced using TPS54xxx PWRGD feature and enable• Adapt to 3.3-V supply:

•• Omit U2 circuit

U2TPS54610PWP

C24 C25

C21 C23C22L2

R6 R7 C16

R9R8C20

C18 C17

C19

3.3 V @ 6 ADIGITAL_VCCIO

PLL_ENABLE

12

456789

1011121314

3

2827

2524232221201918171615

26

RTSYNCHSS/ENAVBIASVINVINVINVINVINPGNDPGNDPGNDPGNDPGND

ANAGNDVSENSE

COMPPWRGD

BOOTPHPHPHPHPHPHPHPHPH

PwrPd

U1TPS54610PWP

C11 C12 C13 C14 C15

C6 C9C10L1

R2 R3 C1

R5 R4

C5

C3 C2

R1

C4

1.2 V @ 6 ADIGITAL_VCCINT

12

456789

1011121314

3

2827

2524232221201918171615

26


ANAGNDVSENSE

COMPPWRGD


PwrPd

R10

5 V_Input

Input capacitors C6 - C8, C10, and output capacitors C11 - C15 enhance loadtransient response(see page 2, Stratix IIPower Requirements)

C7 C8


• The shown power solutions are for applications guidance.Please visit the TI website for the latest updated information.

• Although Altera FPGAs do NOT require it, TI’s referencedesigns employ sequencing when possible, as well as a Supply Voltage Supervisor (SVS) to monitor the inputsupply. This practice is consistent with good power supplydesign and prevents the input power supply from beingpulled down due to in-rush currents for charging largecapacitive loads.

• VCCG_PLL powers the guard ring, which isolates the PLLfrom the rest of the device. VCCG_PLL should be connected to the quietest digital 1.5-V supply on the board, which is typically the device’s VCCINT supply.

• These designs meet Altera’s VCCINT and VCCIO start-up profile requirements, where applicable, including monotonic voltage ramp.

• Only the minimum input and output capacitors for eachIC are given in the schematics. Larger bulk and/or bypasscapacitors will be required between the input supply andDC/DC converters depending on the placement of theinput supply relative to the converters. Each FPGA alsorequires a minimum amount of bypass capacitance oneach power rail as specified by Altera.


6-A Core and I/O Stratix II

Modular (Two PTH05050) Solution 3.3-V or 5-V Input

6

➔

➔

• Cost-effective high-currentsolution using U1 synchro-nous buck controller

• Predictive Gate Drive™ N-channel MOSFET drivers ofU1 provides high efficiency

• Drop-in replacement of U2with TPS54810 or TPS54910(VIN = 3.3 V) gives 8-A or 9-Asolution, respectively

• Soft-start feature and UVLOof U1/U2 eliminate the need for an external SVS tomonitor the input voltage

• Adapt for 3.3-V supply:•• Omit U2 circuit•• U1 has reduced current

drive•• Use TPS40021 for 20-A

drive capability with 3.3-Vinput

R3

R2

C10

C14

R3

R5

R4

C13

R6

C12

5 V_Input

C4

C11

Q2 Q1

Q3 Q4

U2TPS54610PWP

U1TPS40007DGQ

C23 C24

C20 C22C21L2

L1

R7 R8 C15

R10R9C19

C17 C16

C18


PLL_ENABLE

12

456789

1011121314

3

2827

2524232221201918171615

26


ANAGNDVSENSE

COMPPWRGD


PwrPdR11

ILIMFBCOMPSS/SDGND

12345

109876

BOOTHDRV

SWVDD

LDRVPwrPd

C5

C1 C2 C3

C6 C7 C8 C9

DIGITAL_VCCINT1.2 V @ 20 A

Output capacitors C5 - C9 enhance load

transient response(see page 2, Stratix II

Power Requirements)


20-A Core and 6 A I/O Stratix II

DC/DC Converter (TPS40007) and DC/DC Converter (TPS54610) Solution 3.3-V or 5-V Input

• Simple-to-use, plug-in modules

• Highly efficient VCCINT andVCCO rails

• Additional VCCO rails easilyadded

• Interchange modules to support:•• 6 A to 30 A (page 21)•• Minimum input and output

capacitors may change • Minimum external

components• Auto-TrackTM sequencing• Small solution size for

output current• External SVS provides noise

immunity to start-up glitcheson 5-V supply

• Adapt to 3.3-V supply:•• Omit U1, U2, R1, C1, C2•• Change U3 to PTH03050W

U2PTH05050W

U3PTH05050W

C9

C4

C2

C3


R1

R2


5 V_Input

1 GND

TRACK

VIN

Inhibit

VOUT

VoAdj

6

2

3

4 5

1 GND

TRACK

VIN

Inhibit

VOUT

VoAdj

6

2

3

4 5

Output capacitors C4 - C8 enhance load


Power Requirements)

C5 C6 C7 C8

C1U1

TPS3808G50

GNDSNS/NCCT

123

654

RSTGND

MR


Stratix II 26-A Core and 12-A I/O

12-V Input Modular (One PTH12030, One PTH12010) Solution

7

➔

C24

D3

R15 C34 R16

R14

C33

C32

R12

R10

R13

C25

C27

C26

C22U2

TPS40055PWP

C23R11

12345178

161514131211109

C31

R9

Q4 D4

Q3C20 C21

C30 C28 C29

L23.3 V @ 15 ADIGITAL_VCCIO

KFFRTBP5SYNCSGNDSSVFBCOMP

ILIMVIN

BOOSTHDRV

SWBP10LDRV

PGNDPWP

C7

D1

R7 C19 R8

R6

C18

C16

R4

R2

R5

C8

C10

C9

C5U1

TPS40055PWP

C6R3

12345178

161514131211109

C17

R1

Q2

Q1

D2

C1 C4

C11 C12 C13 C14 C15

L11.2 V @ 15 ADIGITAL_VCCINT


ILIMVIN

BOOSTHDRV

SWBP10LDRV

PGNDPWP

12 V_Input

Output capacitors C11 - C15

enhance loadtransient response

(see page 2, Stratix IIPower Requirements)

C2 C3

• Flexible synchronous buckcontroller design allowsoptimization for size, powerdissipation, and cost

• High efficiency: 92% @ 6 A• 8-V to 40-V input voltage

range• 2.8"x 2.5" solution size• UVLO keeps output off until

input is greater than 9.2 V• Soft-start feature and high

UVLO of U1/U2 eliminatesthe need for an external SVSto monitor the input voltage

Stratix II 15-A Core and I/O 12-V Input DC/DC Controllers (Two TPS40055) Solution

➔






components• Auto-Track™ sequencing• Small solution size for



U3PTH12010W


12345

109876

245

1113

131298710

Output capicitors C7 - C13 enhance load


Power Requirements)

C13C12C11

C6C5C4

C10C9C8C7

U1TL7712ACD

U2PTH12030W

VINInhibitVoAdjTrackGNDGND

MgnUpMgnDwn

VOUTVOUTGNDGND

VoSense6

REFRESINCTGND

8765

1234

VCCSNSRSTRST

12 V_Input

C14 C15 C16

GNDVINInhibitVoAdjVoSns

MgnUpMgnDwn

TrackGND

VOUT

R1C17


C3

C1 C2

R2



800-mA Core and I/O Stratix GX/Stratix/Cyclone

Dual LDO (TPS70402) Solution 3.3-V or 5-V Input

8

➔

1-A Core and I/O Stratix GX/Stratix/Cyclone

Independent LDO (TPS725xx) Solution 3.3-V or 5-V Input➔

• Independent linear regulators allow higherpower dissipation than anintegrated, dual-channelsolution

• Linear regulator solutionssave cost and space over a switching DC/DC solution

• U1 monitors the input rail to make sure that it is upand stable before enablingthe U2 regulator

• Sequencing VCCINT, thenVCCIO, then PLLs minimizesdemand on the input supply

3.3 V_Input

U1TLC7733QD

U2TPS72515KTT

U3TPS72525KTT

C1 C2 1.5 V @ 1 ADIGITAL_VCCINT


PLL_ENABLE

C3

C6

C7C4

C5

R1

R2

1234

8765

123

5

4

123

5

4

CRTLRESINCTGND

VDDSNSRSTRST RST

OUT

ENINGND

RST

OUT

ENINGND

• Dual-channel LDO inPowerPADTM package savescost and space

• U1 monitors the input rail to ensure that it is up andstable before enabling theregulator

• Soft-start circuit on VCCINTminimizes demand on theinput supply at start-up

• 2-A capability on channel 2of U2 supports peak start-upcurrent

• PG1 output enables PLLafter VCCIO is present;sequencing reduces demand on the input supply

• U2 is limited to 2 W @ TA = 55°C and no airflow due to power dissipation; its maximumoutput current is splitbetween the rails

3.3 V_Input

C1

C6 C4 C5

C9

C2R31

234

8765

U1TLC7733QDCRTLRESINCTGND

VDDSNSRSTRST

GNDVIN1VIN1NCMREN1EN2RESETGNDVIN2VIN2GND/HS

GND/HSVO1VO1

VSNS1/FB1NC

PG1PG2NC

VO2_SNS2_FB2VO2VO2

GND/HSPwrPad

U2TPS70402PWP R2

C3

C7R6

R8

R1 123456789

101112

242322212019181716151413

R4 R5

C8 R7

Q1

C10

2.5 V @ 800 mADIGITAL_VCCIO

PLL_ENABLE

1.5 V @ 800 mADIGITAL_VCCINT


U1TLC7701ID

U2TPS64203DBV


C8C7C6R5

R6

C3

R4

L1

Q1

D1

521

643

VINGNDEN

SWISENSE

FB

CRTLRESINCTGND

VDDSNSRSTRST

1234

8765

C2 R3

R2

R1

5 V_Input

C1

C4

U3TPS78633KTT

3.3 V @ 1.5 ADIGITAL_VCCIO

C5

154

6

23

ENINGND

BYPS/FBOUT

GND

• Tiny SOT-23 switchingDC/DC (U2) delivers up to 3 A at ultra-low cost

• VCCINT soft-starts from internal soft-start of U2

• Current Sense resistor R1gives more precise currentlimit; can be omitted

• External SVS provides noiseimmunity to start-up glitcheson 5-V supply

• TPS78633 LDO provideslow-cost 3.3-V VCCIO

• Adapt to 3.3-V supply:•• Omit U3•• Change R1, R2, R3

Stratix GX/Stratix/Cyclone 3-A Core , 1.5-A I/O3.3-V or 5-V Input DC/DC Controller (TPS64203) and LDO (TPS78633) Solution ➔


Stratix GX/Stratix/Cyclone 1.5-A Core, 1.5-A I/O3.3-V or 5-V Input DC/DC Converter (TPS54110) and LDO (TPS78633) Solution

9

➔

• Up to 90% efficient switching DC/DC converter(U1) minimizes heating

• U1’s integrated switch minimizes external components

• Drop-in replacement of U1with TPS54310 gives 3 A

• Sequencing of VCCINT andVCCIO reduces demand oninput supply

• High UVLO (Under VoltageLockout) and integrated softstart of U1 eliminates theneed for an external SVS tomonitor the input voltage

• Start-up is programmable by C4

• Adapt to 3.3-V supply:•• Omit U2, C10, C11

U2TPS78633KTT

U1TPS54110PWP

1.5 V @ 1.5 ADIGITAL_VCCINT

3.3 V @ 1.5 ADIGITAL_VCCIO

C11

C8 C9

C7

C10

C6C5C4

C1 R2

R5

R1

R3 C2

C3

R4R6

L1

154

6

23

17811920

161514131211

4321

56789

10

21

ENINGND

BYPS/FBOUT

GND

RTSYNCSS/ENAVBIASVINVINVINPGNDPGNDPGND

AGNDVSENSE

COMPPWRGD

BOOTPHPHPHPHPH

PwrPd

5 V_Input


➔

U2TPS54810PWP

C19 C20

C16 C18C17L2

R5 R6 C11

R8R7C15

C13 C12

C14


PLL_ENABLE

12

456789

1011121314

3

2827

2524232221201918171615

26


ANAGNDVSENSE

COMPPWRGD


PwrPd

U1TPS54610PWP

C9 C10

C6 C8C7L1

R1 R2 C1

R4 R3

C5

C3 C2

C4


12

456789

1011121314

3

2827

2524232221201918171615

26


ANAGNDVSENSE

COMPPWRGD


PwrPd

R9

5 V_Input


DC/DC Converters (Two TPS54610) Solution 3.3-V or 5-V Input• Highly efficient VCCINT rails

up to 6 A • Drop-in replacement of

U1/ U2 with TPS54810 orTPS54910 (VIN = 3.3 V)gives 8-A or 9-A solution,respectively

• SWIFT™ (Switcher withIntegrated FET) TPS54610adjustable design allows:•• Use of smaller inductor,

ceramic capacitors•• Flexibility to recompensate

depending on thebulk/bypass capacitorsused for the FPGA

• Fixed TPS5461x output voltage options available

• SWIFT design software isavailable for further customization

• UVLO and integrated soft-start of U1/U2 eliminate the need for an external SVS to monitor the input voltage• Sequencing of VCCINT, then VCCIO, then PLL minimizes the demand on the input supply• Additional rails easily added and sequenced using TPS54xxx PWRGD feature and enable• Adapt to 3.3-V supply:

•• Omit U2 circuit



DC/DC Controllers (Two TPS64203) Solution 3.3-V or 5-V Input

10

➔

• Tiny SOT-23 switchingDC/DC controller (U2, U3)delivers up to 3 A at ultra-low cost

• VCCINT soft-starts from internal soft-start of U2, minimizing inrush due tocharging capacitors

• Current Sense resistor R1and R4 give more precisecurrent limit; omit and connect ISNS to drain of Q1,Q2 to save cost and space

• External SVS provides noiseimmunity to start-up glitcheson 5-V supply

• Adapt to 3.3-V supply:•• Change R1, R2, R3•• Omit 3.3-V TPS64203

U3TPS64203DBV

U1TLC7701ID


C10C8C6R8

R9

C24

R5

L2

Q2

D2

521

643

VINGNDEN

SWISENSE

FB

U2TPS64203DBV


C9C7C5R6

R7

C3

R4

L1

Q1

D1

521

643

VINGNDEN

SWISENSE

FB

CRTLRESINCTGND

VDDSNSRSTRST

1234

8265

C2

R3

R2

R1

5 V_Input

C1



Stratix GX/Stratix/Cyclone 6-A Core and I/O

3.3-V or 5-V Input Modular (Two PTH05050) Solution

11

➔

C18 C19 C20 C21 C22R10

R11

U2TPS40021PWP

R13 R14C24

R15IO_ENABLE

C26 R16C33

R19R18C34 R17

12345678

161514131211109

17

C31C27 C28 C29 C30

C32

R12C25


PLL_ENABLE

C23 Q3

Q4

L2ILIM_SYNSVDDOSNSFBCOMPSS/SDRTSGND

BT1HDRV

SWBT2

PVDDLDRV

PGNDPGD

PWP

C1 C2 C3 C4 C5R1 U1

TPS40021PWP

R3 R4C7

R5 C9R6C16

R9R8C17 R7

12345678

161514131211109

17

C14C10 C11 C12 C13

C15

R2C8


IO_ENABLE

C6 Q1

Q2

L1ILIM_SYNSVDDOSNSFBCOMPSS/SDRTSGND

BT1HDRV

SWBT2

PVDDLDRV

PGNDPGD

PWP

5 V_Input• Cost effective high-currentsolution

• Powers one or moreCyclone/Stratix FPGAs

• High efficiency: 88% @ 20 A• 2.25-V to 5.5-V input voltage

range• Good transient response• Flexible synchronous buck

controller design allowsoptimization for size, powerdissipation, and cost

• Use TPS40K™ design soft-ware to customize design

• Soft-start feature of U1 andU2 eliminates the need foran external SVS to monitorthe input voltage

• Sequencing of VCCINT, thenVCCIO, then PLL minimizesdemand on the input supply

• Adapt to 3.3-V supply:•• Omit U2 circuit

Stratix GX/Stratix/Cyclone 20-A Core and I/O3.3-V or 5-V Input DC/DC Controllers (Two TPS40021) Solution ➔









• Adapt to 3.3-V supply:•• Omit U1, U2, R1, C1, C2•• Change U3 to PTH03050W

C1U1

TPS3808G50

GNDSNS/NCCT

123

654

RSTGND

MR

U2PTH05050W

U3PTH05050W

C5

C4

C2

C3


R1

R2


5 V_Input

1 GND

TRACK

VIN

Inhibit

VOUT

VoAdj

6

2

3

4 5

1 GND

TRACK

VIN

Inhibit

VOUT

VoAdj

6

2

3

4 5




DC/DC Converters (Two TPS54350) Solution 12-V Input

12

➔


(Two PTH12050 Modules) Solution➔









C3

C1 C2U1

TL7712ACD

U2PTH12050W

U3PTH12050W

C7

C6

C4

C5


R2


12 V_Input

1 GND

TRACK

VIN

Inhibit

VOUT

VoAdj

6

2

3

4 5

REF

RESIN

CT

GND

1

2

3

4

8

7

6

5

VCC

SNS

RST

RST

1 GND

TRACK

VIN

Inhibit

VOUT

VoAdj

6

2

3

4 5

R3

R1

U2TPS54350PWP

12345678

17

161514131211109

Q2R9

C16

C13 C14

C20C18

R11

R10

R8C12

R15R14

R12

C19

C17 R13

C15

C11 L2VINVINUVLOPWRGDRTSYNCENACOMP

BOOTPHPH

LSGVBIASPGNDAGND

VSENSEPWRPD

1.5 V @ 3ADIGITAL_VCCINT

PLL_ENABLE

U1TPS54350PWP

12345678

17

161514131211109

Q1R2

C6

C3 C4

C10

C8

R3

C2

12 V_Input

R7R6

R1

R4

C9

C7 R5

C5

C1 L1VINVINUVLOPWRGDRTSYNCENACOMP

BOOTPHPH

LSGVBIASPGNDAGND

VSENSEPWRPD

3.3 V @ 3ADIGITAL_VCCIO


• Low-cost solution with integrated pass FET

• High efficiency: 86% @ 3 A• 4.5-V to 20-V input voltage

range• Excellent transient response• UVLO keeps output off until

input is greater than 9.0 V• Sequencing of VCCINT, then

VCCIO, then PLL minimizesdemand on the input supply

• Slow/soft-start on both U1and U2 using R3, C8, R11,and C18


Stratix GX/Stratix/Cyclone 15-A Core and I/O

12-V Input DC/DC Controllers (Two TPS40055) Solution

13

➔

Stratix II VCCPD 400-mA VCCPD

5-V Input LDO (TPS73633) Solution

➔

• Tiny 3x3 mm package• Thermally enhanced QFN

package allows high powerdissipation (1.38 W at 70°C)

• Connect VCCPD to 3.3-V I/Orail if one is available

• Adapt to lower currents byusing:•• TPS731xx 150 mA, SOT23

package (DBV) •• TPS732xx 250 mA, SOT23

(pin-for-pin to TPS731xx)and SOT223 (DCQ)

•• TPS736xx 400 mA, SOT23(pin-for-pin to TPS731xx),SOT223 (DCQ), and QFN(DRB)

U1TPS73633DRB

C1 C2

IN

NC

EN

GND

8

7

5

4

1

2

6

3

OUT

NC

NC

NR/FB

3.3 V @ 400 mAVCCPD

PwrPd

5 V_Input

Optional Input/Output capacitors enhance transient response.

• Flexible synchronous buckcontroller design allowsoptimization for size, powerdissipation, and cost

• Low-cost high-current solution

• Powers one or moreCyclone/Stratix FPGAs

• High efficiency: 92% @ 6 A• U1, U2 capable of 8-V to

40-V input voltage (designoptimized for 12 V)

• 2.8"x 2.5" solution size• Excellent transient response• UVLO keeps output off until

input is greater than 9.2 V• Soft-start feature and high

UVLO of U1/U2 eliminatesthe need for an external SVSto monitor the input voltage

C20

D3

R15 C30 R16

R14

C29

C27

R12

R10

R13

C21

C23

C22

C18U2

TPS40055PWP

C19R11

12345178

161514131211109

C28

R9

Q4 D4

Q3C16 C17

C26 C24 C25

L23.3 V @ 15 ADIGITAL_VCCIO


ILIMVIN

BOOSTHDRV

SWBP10LDRV

PGNDPWP

C5

D1

R7 C15 R8

R6

C14

C12

R4

R2

R5

C6

C8

C7

C3U1

TPS40055PWP

C4R3

12345178

161514131211109

C13

R1

Q2 D2

C1 Q1

C2

C11 C9 C10

L11.5 V @ 15 ADIGITAL_VCCINT


ILIMVIN

BOOSTHDRV

SWBP10LDRV

PGNDPWP

12 V_Input



Stratix II/Stratix GX/Stratix PLL Supply

LDO (TPS786xx) Solution

14

➔

• High PSRR, low-noise RFLDO provides noise immunity

• Individual LDOs used foreach PLL for increased isolation

• Small MSOP-8 PowerPAD™package

• Ferrite beads (FB1, FB2) andC1, C12 provide additionalfiltering

• 2.7-V to 5.5-V input voltagerange

• Low cost

U2TPS79401DGN

1234

8765

9C10

C7

R4

R3 C6

C8C9

VINNCENGND

VOUTNCFB

BYPPwrPd

PLL2_GND

VCCA_PLL2FB2

U1TPS79401DGN

1234

8765

9C5

C2

R2

R1 C1

C3C4

VINNCENGND

VOUTNCFB

BYPPwrPd

PLL1_GND

VCCA_PLL1FB1

PLL_ENABLE

1.5 V @ 250 mA

1.5 V @ 250 mA

5 V_Input

• Powering multiple PLLs with a single LDO minimizes size

• High PSRR, low-noise RF LDO provides noise immunity

• Ferrite beads and capacitorson each PLL rail provides additional filtering


• U1 can support up to 2.4 Adepending on power dissipation

• Stratix II Digital PLL (VCCD_PLL)may be connected to the 1.2 VVCCINT rail

U1TPS78601KTT

C1C2 C3

DIGITAL_ VCCIO

PLL_ENABLE

R2 R1

15

4

6

23

ENINGND

BYPS/FBOUT

GND

1.5 V @ 1.5 A

U1TPS78601KTT

C1C2

DIGITAL_ VCCIO

PLL_ENABLE 15

4

6

23

ENINGND

BYPS/FBOUT

GND

1.2 V @ 1.5 A

STRATIX GX/STRATIX

STRATIX II

C3

VCCA_PLL1

C4

VCCA_PLL2

C5

VCCA_PLL3

C6

VCCA_PLL4

C7

VCCA_PLL5

C8

VCCA_PLL6FB6

FB5

FB4

FB3

FB2

FB1

➔


Cyclone PLL SuppliesLDO (TPS794xx) Solution

Output Spectral Noise Densityvs.

Frequency

Ripple Rejectionvs.

Frequency

Out

put S

pect

ral N

oise

Den

sity

- µV

/

Hz

Ripp

le R

ejec

tion

- dB

VI = 3.8 VCO = 2.2 µFC(byp) = 0.1 µF

100

90

80

70

60

50

40

30

20

10

0100 1 k 10 k 100

f - Frequency - Hz10 M1 M100 k10 k1 k10010

f - Frequency - Hz

IO = 200 mA

IO = 1 mAIO = 10 mA

IO = 200 mA

VI = 3.8 VCO = 10 µFC(byp) = 0.01 µF

0.3

0.25

0.2

0.15

0.1

0.05

0


Stratix II/Stratix GX /Stratix PLL OUT Supply

LDO (TPS793xx) Solution

15

➔

➔


• Individual LDOs can be used on each PLL toincrease isolation


• Low cost• Connect VCC_PLL_OUT to the

respective digital I/O voltagerail if one is available (omitU1 circuit)

U1TPS793xxDBV

C1

C2

C3

IN

GND

EN

OUT

BYPASS

1

2

3

5

4

5 V_Input 1.8 V, 2.5 V. 3.3 V @ 50 mAVCC_PLL_OUT



• Powers one or more transceiver blocks

• Individual LDOs increaseisolation


• Low cost• LDOs are recommended for

analog transceivers, but digital transceivers may beconnected to the 1.5-V VCCINTrail (omit U1 circuit)

U1TPS78601KTT

C1C2 C3

3.3 V_Input

5 V_Input

1.5 V @ 1.5 ADIGITAL_VCCP

DIGITAL_RETURN

R2 R1

15

4

6

23

ENINGND

FBOUT

GND

U2TPS78601KTT

C4

C8

C9

C5 C6

1.5 V @ 1.5 AANALOG_VCCR

ANALOG_RETURN

3.3 V @ 200 mAANALOG_VCCAQ

R4R3

15

4

6

23

1

23

5

4

ENINGND

FBOUT

U3TPS79333DBV

GND

C7

ENINGND

BYPS

OUT

Stratix GX Transceiver Supplies

LDO (TPS79xxx, TPS786xx) Solution

U2TPS73125DBV

1

2

3

5

4

3.3 V_Input2.5 V @ 150 mADIGITAL_VCCINT

U3TPS73118DBV

IN

GND

EN

OUT

NR/FB

1

2

3

5

4


Optional Input/Output capacitors enhance transient response.

C4C2

C5C3

C1

R1

U1TPS3808G33

VDD

SNS/NC

CT

6

5

4

1

2

3

RST

GND

MR

IN

GND

EN

OUT

NR/FB


150-mA Core and I/O Max II CPLD

LDO (Two TPS731xx) Solution 3.3-V or 5-V Input

16

➔

• Cap-free SOT23 LDOs savespace and cost

• Cap-free design minimizesinrush, eliminating need for SVS


• Adapt to higher currents by using:•• TPS731xx 150mA, SOT23

package (DBV) •• TPS732xx 250mA, SOT23

(pin-pin to TPS731xx) andSOT223 (DCQ)

•• TPS736xx 400mA, SOT23(pin-pin to TPS731xx),SOT223 (DCQ), and QFN(DRB)


1.5-A Powering Both Core and I/O Max II CPLD

LDO (TPS786xx) Solution 5-V Input➔

• Low-cost linear regulatorpowers both core and I/O voltages

• U1 monitors the input rail to make sure that it is upand stable before enablingthe U2

• Programmable power-ondelay time by CT pin on U1 provides flexibility

C2

C1

R1

U2TPS78633KTT

U1TPS3808G33

DIGITAL_VCCIO

DIGITAL_VCCINT

154

6

23

ENINGND

BYPS/FBOUT

GND

5 V_ Input

C4C3

VDD

SNS/NC

CT

6

5

4

1

2

3

RST

GND

MR

3.3 V @ 1.5 A

PRELIMINARY - PENDING TESTING


U2TPS73633DRB

U3TPS62042DGQ

1234

8765

9

C2 C3

C1

R1

INNCENGND

OUTNCNC

NR/FBPwrPd

3.3 V @ 400 mADIGITAL_ VCCINT

1.5 V @ 1.2 ADIGITAL_ VCCIO

5 V_Input

C5C4

U1TPS3808G50

1234

5

10987

6

654

123

11

ENVINVINAGNDFB

PGNDPGND

SWSW

MODPWP

RSTGND

MR

VDDSNS/NCCT

L1L1


Max II CPLD 400-mA Core and 1.2 A I/O

3.3-V or 5.5-V Input LDO (TPS73633) and DC/DC Converter (TPS62042) Solution

17

➔

➔

• 90% efficient synchronousbuck converter (U3) minimizes heating

• Integrated soft-start of U2minimizes capacitive inrush

• U1 monitors the input rail tomake sure that it is up andstable before enabling theregulators

• Sequencing of VCCINT thenVCCIO reduces demand oninput supply

• Adapt to 3.3-V supply:•• Replace U1 with

TPS3808G33•• Omit U2 circuit or use

TPS73601 (adjustable) for2.5 V VCCINT


• Synchronous buck convertergives high efficiency: 86% @ 3 A

• Integrated high-side FETsimplifies design

• 4.5-V to 20-V input voltagerange

• Excellent Transient Response• UVLO keeps output off until

input is greater than 9.0 V• Adjustable start-up timing

through R3 and C2

U1TPS54350PWP


161514131211109

12345678

C9

C8

Q1

3.3 V @ 400 mADIGITAL_VCCINT

Other Circuits

17

C1

C5

C6 C7

R7

R6

R8

R5

R1

R2

R3

C2

C3 R4

C4

L1

VINVINUVLOPWRGDRTSYNCENACOMP

BOOTPHPH

LSGVBIASPGNDAGND

VSENSEPwrPd

12 V_Input3.3 V @ 3 A

Max II CPLD 3-A Powering Both Core and I/O

DC/DC Converter (TPS54350) Solution 12-V Input




18 Appendices

Texas Instruments Power Management FPGA/CPLD Reference Guide➔



Appendices

Texas Instruments Power Management FPGA/CPLD Reference Guide

19

➔Complete schematics available at: www.ti.com/alterafpga


20 Selection Guides

www.ti.com/alterafpga➔

Low Dropout Regulators (LDO)Output Options Packages

VDO

IO @ IO Iq

Device1 (mA) (mV) (µA) Fixed Voltage (V)3 Adj. SOT23 MSOP SOT223 DDPAK Features2 CO4 Comments Price5

Positive Voltage, Single Output DevicesTPS731xx 150 30 400 1.2, 1.5, 1.8, 2.5, 3.0, 3.3, 5.0 1.2 to 5.5 1.7 5.5 1 ✔ EN, BP No Cap Reverse Leakage Protection 0.45TPS793xx 200 77 170 1.2, 1.8, 2.5, 2.8, 2.85, 3.0, 3.3, 4.75 1.2 to 5.5 2.7 5.5 2 ✔ EN, BP 2.2 µF C RF Low Noise, High PSRR 0.40TPS794xx 250 145 170 1.2, 1.8, 2.5, 2.8, 3.0, 3.3 1.2 to 5.5 2.7 5.5 3 ✔ ✔ EN, BP 2.2 µF C RF Low Noise, High PSRR 0.65TPS732xx 250 40 400 1.2, 1.5, 1.8, 2.5, 3.0, 3.3, 5.0 1.20 to 5.5 1.7 5.5 1 ✔ ✔ EN, BP No Cap Reverse Leakage Protection 0.65TPS736xx 400 75 300 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 1.20 to 5.5 1.7 5.5 1 ✔ ✔ EN, BP No Cap Reverse Leakage Protection 0.85TPS795xx 500 105 265 1.2, 1.6, 1.8, 2.5, 3.0, 3.3 1.2 to 5.5 2.7 5.5 2 ✔ EN, BP 1 µF C RF Low Noise, High PSRR 0.95TPS796xx 1000 200 265 1.2, 1.8, 2.5, 2.8, 3.0, 3.3 1.2 to 5.5 2.7 5.5 2 ✔ ✔ EN, BP 1 µF C RF Low Noise, High PSRR 1.05TPS725xx 1000 170 75 1.2, 1.5, 1.6, 1.8, 2.5 1.2 to 5.5 1.8 6 2 ✔ ✔ EN, SVS No Cap Low Noise 1.10TPS786xx 1500 390 265 1.2, 1.8, 2.5, 2.8, 3.0, 3.3 1.2 to 5.5 2.7 5.5 2 ✔ ✔ EN, BP 1 µF C RF Low Noise, High PSRR 1.30

1xx represents the voltage option. For example, 33 represents the 3.3-V option. 4C = Ceramic output capacitor; No Cap = Capacitor Free LDO. The adjustable output voltage option is represented by 01.

2EN = Active High Enable; BP = Bypass Pin for noise reduction capacitor; SVS = Supply Voltage Supervisor. 5Suggested resale price in U.S. dollars in quantities of 1,000.31.2 V fixed achieved by using the adjustable option and tying VOUT directly to the FB pin.

Min

V IN

Max

VIN

Accu

racy

(%)

Dual Output LDOs Output Options Features

VDO1 VDO2

IO1 IO2 @ IO1 @ IO2 Iq Fixed Voltage Accuracy PWP Min Max Low Min MaxDevice (mA) (mA) (mV) (mV) (µA) (V) Adj. (%) Package VO VO /EN PG SVS Seq Noise VIN VIN CO

1 Description Price2

TPS703xx 2000 1000 160 — 185 3.3/2.5, 3.3/1.8, ✔ 2 ✔ 1.2 5.5 ✔ ✔ ✔ ✔ ✔ 2.7 5.5 22 µF T Dual Output LDO with 2.303.3/1.5, 3.3/1.2 Sequencing

TPS704xx 2000 1000 160 — 185 3.3/2.5, 3.3/1.8, ✔ 2 ✔ 1.2 5.5 ✔ ✔ ✔ ✔ 2.7 5.5 22 µF T Dual Output LDO with 2.303.3/1.5, 3.3/1.2 Independent Enable

1T = Tantalum output capacitor.

2Suggested resale price in U.S. dollars in quantities of 1,000

Switching DC/DC Converters Features Packaging

VOUT VOUTIOUT VIN Adj Fix Efficiency Evaluation

Device (mA) (V) (V) (V) % Thermal Limit TSSOP Module Price1

SWIFT™ Step-Down (Buck) Converters — up to 9 ATPS54110 1500 3.0 to 6.0 0.9 to 4.5 — 90 700 3.6 ✔ ✔ ✔ ✔ 20 ✔ 2.15TPS54310 3000 3.0 to 6.0 0.9 to 4.5 — 90 700 6.2 ✔ ✔ ✔ ✔ 20 ✔ 2.95TPS54311 3000 3.0 to 6.0 — 0.9 90 700 6.2 ✔ ✔ ✔ ✔ 20 2.95TPS54312 3000 3.0 to 6.0 — 1.2 90 700 6.2 ✔ ✔ ✔ ✔ 20 2.95TPS54313 ˜3000 3.0 to 6.0 — 1.5 90 700 6.2 ✔ ✔ ✔ ✔ 20 2.95TPS54314 3000 3.0 to 6.0 — 1.8 90 700 6.2 ✔ ✔ ✔ ✔ 20 ✔ 2.95TPS54315 3000 3.0 to 6.0 — 2.5 90 700 6.2 ✔ ✔ ✔ ✔ 20 2.95TPS54316 3000 3.0 to 6.0 — 3.3 90 700 6.2 ✔ ✔ ✔ ✔ 20 2.95TPS54350 3000 4.5 to 20 0.9 to 12 — 85 700 9 ✔ ✔ ✔ ✔ 16 ✔ 3.35TPS54610 6000 3.0 to 6.0 0.9 to 4.5 — 90 700 11 ✔ ✔ ✔ ✔ 28 ✔ 3.90TPS54611 6000 3.0 to 6.0 — 0.9 90 700 11 ✔ ✔ ✔ ✔ 28 3.90TPS54612 6000 3.0 to 6.0 — 1.2 90 700 11 ✔ ✔ ✔ ✔ 28 3.90TPS54613 6000 3.0 to 6.0 — 1.5 90 700 11 ✔ ✔ ✔ ✔ 28 3.90TPS54614 6000 3.0 to 6.0 — 1.8 90 700 11 ✔ ✔ ✔ ✔ 28 ✔ 3.90TPS54615 6000 3.0 to 6.0 — 2.5 90 700 11 ✔ ✔ ✔ ✔ 28 3.90TPS54616 6000 3.0 to 6.0 — 3.3 90 700 11 ✔ ✔ ✔ ✔ 28 3.90TPS54810 8000 4.0 to 6.0 0.9 to 4.5 — 85 700 11 ✔ ✔ ✔ ✔ 28 ✔ 4.20TPS54910 9000 3.0 to 4.0 0.9 to 2.5 — 90 700 11 ✔ ✔ ✔ ✔ 28 ✔ 4.40TPS54974 9000 2.2 to 4.0 0.2 to 2.5 — 90 700 11 ✔ ✔ ✔ ✔ ✔ 28 ✔ 4.40

1Suggested resale price in U.S. dollars in quantities of 1,000.

Switc

hing

Fre

quen

cy(m

ax) (

kHz)

Quie

scen

t Cur

rent

(typ)

(mA)

Shut

dow

n

Pow

er G

ood

Dual

Inpu

t Bus

(3.3,

2.5 V

)

Curre

nt L

imit


Selection Guides

www.ti.com/alterafpga

21


Switching DC/DC Controllers VO VO Vref Driver Output Regulated

VIN (max) (min) Tol Current Current Outputs Device (V) (V) (V) (%) (A) Range (A) (#) Protection1 Comments Price2

Performance Processor Power Supply Controllers (Synchronous Rectification)TPS64203 1.8 to 6.5 6.5 1.2 2 0.150 0 to 3 1 OCP, UVLO Non-sync buck in SOT-23 0.50TPS40007 2.25 to 5.5 4 0.7 1.5 1 3 to10 (3.3 VIN) 1 OCP, UVLO 300-kHz switching frequency gives highest 0.99

3 to 20 (5 VIN) efficiency for lowest heatTPS40009 2.25 to 5.5 4 0.7 1.5 1 3 to10 1 OCP, UVLO 600-kHz switching frequency gives smallest 0.99

solutionTPS40021 2.25 to 5.5 4 0.7 1 1 10 to 20 1 OCP, UVLO Enhanced flexibility with user programmability 1.15TPS40055 8 to 40 35 0.7 1 1 3 to 20 1 OCP, UVLO Wide input range sync buck, source/sink 1.35TPS40061 10 to 55 45 0.7 1 1 1 to 10 1 OCP, UVLO Wide input range sync buck, source/sink 1.35

1OCP = over-current protection; UVLO = under-voltage lockout. 2Suggested resale price in U.S. dollars in quantities of 1,000.

Plug-In Power Solutions Input Bus POUT Isolated VO Range VO

Device1 Voltage or IOUT Outputs (V) Adjustable Price2

Non-Isolated Single Positive Output

PTH03010/20/30/50/60 3.3 V 15 A, 22 A, 30 A, 6 A, 10 A No 0.8 to 2.5 Yes 14.00, 18.15, 24.65, 9.10, 11.20PTH05010/20/30/50/60 5 V 15 A, 22 A, 30 A, 6 A, 10 A No 0.8 to 3.6 Yes 14.00, 18.15, 24.65, 9.10, 11.20PTH12010/20/30/50/60W 12 V 12 A. 18 A, 26 A, 6 A, 10 A No 1.2 to 5.5 Yes 14.00, 18.15, 24.65, 9.10, 11.20PTH12010/20/50/60L 12 V 12 A, 18 A, 6 A, 10 A No 0.8 to 1.8 Yes 14.00, 18.15, 9.10, 11.20

1See power.ti.com for a complete product offering.2Suggested resale price in U.S. dollars in quantities of 1,000.

Supply Voltage Supervisors (SVS)

TimeNumber of Supervised IDD Delay

Device Supervisors Voltages Packages (typ) (ms) Price2

TPS3808 1 Adj./0.9/1.2/1.5/1.8/2.5/ SOT-23 2.4 µA Prog ✔ — OD New. Adjustable delay from 1.25 ms to 10 s 0.703.0/3.3/5/0

TPS3809 1 2.5/3.0/3.3/5.0 SOT-23 9 µA 200 — — PP Small, low cost 0.29TLC77xx 1 Adj./2.5/3.3/3.0/5.0 SO-8, DIP-8, TSSOP-8 9 µA Prog — ✔ PP Universal SVS with broad voltage range and both 0.60

active-low and active-high resetTL7712A 1 12 SOIC, PDIP 1.8 mA Prog — ✔ OC For 12-V monitoring 0.50

1PP = Push-Pull; OD = Open Drain; OC = Open Collector.


Man

ual R

eset

Inpu

t/MR

Act

ive-

Hig

hRe

set O

utpu

t

Rese

t Out

put

Topo

logy

1

Comments


22 Active Bus Termination Solutions (DDR/QDR/GTL/SSTL/HSTL)

Tables➔

Active Bus Termination Plug-In Power Module Solutions Input Bus Isolated VO Range VO

Device Voltage POUT or IOUT Outputs (V) Adjustable Price1

PTH03010/50/60Y 3.3 V 6 A, 10 A, 15 A No 0.55 to 1.8 Yes 13.95, 9.95, 11.50PTH05010/50/60Y 5 V 6 A, 10 A, 15 A No 0.55 to 1.8 Yes 13.95, 9.95, 11.50PTH12010/50/60Y 12 V 6 A, 8 A, 12 A No 0.55 to 1.8 Yes 13.95, 9.95, 11.50


Active Bus Termination Converter (with Integrated FETs) Solutions IOUT VIN Adj. VOUT Switching Frequency Pin Count Evaluation

Device (mA) (V) (V) Efficiency % (max) (kHz) HTSSOP Module Price1

TPS54372 3000 3.0 to 6.0 0.2 to 4.5 90 700 20 Yes 2.95TPS54672 6000 3.0 to 6.0 0.2 to 4.5 90 700 28 Yes 3.90TPS54872 8000 4.0 to 6.0 0.2 to 4.5 85 700 28 Yes 4.20TPS54972 9000 3.0 to 4.0 0.2 to 4.5 90 700 28 Yes 4.40


Active Bus Termination Converter (with External FETs) Solutions VOUT` VOUT2 VOUT3 Switching Light

IOUT1 IOUT2 IOUT3 (VDDQ) (VTT) (buf. VREF) Frequency Load Selectable(VDDQ) (VTT) (buf. VREF) VIN Adj. Fixed Fixed Selectable Eff. Control Output

Device (A) (A) (mA) (V) (V) (V) (V) (kHz) Mode Scheme Discharge Package Price1

TPS51020 >10 >3 3 4.5 to 2.5/ 1/2 VDDQ 1/2 VDDQ 270, 360, 450 Yes Voltage Yes 30 TSSOP 3.15Switcher Switcher 28 V 1.8 V/ADJ Mode

TPS51116 >10 3 LDO 10 3 to 2.5/ 1/2 VDDQ 1/2 VDDQ 400 Yes D-CAP/ Yes 20 HTSSOP 1.20Switcher 28 V 1.8 V/ADJ Current PowerPAD™

Mode 24 QFN PowerPAD


Active Bus Termination Converter (with External FETs) Solutions VOUT` VOUT2 VOUT3

IOUT2 IOUT3 (VDDQ) (VTT) (buf. VREF) Selectable(VTT) (buf. VREF) VIN Adj. Fixed Fixed Output

Device (A) (mA) (V) (V) (V) (V) Discharge Package Price1

TPS51100 3 LDO 10 1.2 to 3.6 2.5 to 1.8 ADJ 1/2 VDDQ 1/2 VDDQ Yes 10 MSOP 0.80PowerPAD™


Texas Instruments offers a wide selection of Active Bus Termination solutions from LDOs and switching controllers to Plug-In Power. To aid in product selection, TI provides the solution recommendations in the tables below and offers various schematics as shown on page 15.


Active Bus Termination Solutions (DDR/QDR/GTL/SSTL/HSTL)

Schematics

23


VDDQ

VDDQ

VTTQ

VTT

VTTREF

S3

S5

5 V_IN

C2Ceramic0.1 µF

C1Ceramic2 x 10 µF

TPS51100_MSOP10(DGQ)

TPS554372

1

2

7

6

3 4 5

10 9 8

S5

VTT

S3

VIN

5 VIN

VDD0

PGOOD

VDDQSNS

VLD0IN

VTT

PGND

VTTSNS

VIN

S5

GND

S3

VTTREF

1PTHXX060Y(Top View)

VIN

VDDQ VREF

VTT

1 k1%

Standby

GND

1 k1%

CONhf-Ceramic

CO2CeramicOptional

CIN(Required) CO1

Low-ESRRequiredQ1

BSS138(Optional)

PTHxx060Y: Plug-In Power

TPS51116: Controller + LDO

TPS54372: SWIFT™

TPS51100: LDO

CompensationNetwork

SSTL-2Data/

AddressBus

VTT Term

ination Island

InputVDDQSNS

AGND

REFIN

VBIAS

PH

BOOT

PGND

COMP

VSENSE

TPS51116 (PWP)

VLD0INVTTVTTGNDVTTSNSGNDMODEVTTREFCOMPVDDQSNSVDDQSET

VBSTDRVH

LLDRVL

PGNDCS

V5INPGOOD

S5S3C3 C5 C4

R1R0 R2 C2

C1M0

L0

M1

C6

C0

GND

VDDQ = 2.5 V (DDR I), RDSCon Sense, Quick Discharge

GND

GND

GND

PTHxx050Y = 6 A, PTHxx060Y = 10 A, PTHxx010Y = 15 A

VINVBIAS

ENAPG

VSENSE

PGND

BOOT

LSG

PH

TPS543504.5 V to 20 V 3.3 V

SWIFT™

SOFTWARE

TOOL

R E A L W O R L D S I G N A L P R O C E S S I N GTM

Key Features• Operating input voltage range: 4.5 V to 20 V• 4.5-A peak MOSFET switch for high efficiency at 3-A

continuous output current• Uses external low-side MOSFET or diode• Output voltage adjustable down to 0.9 V with 1% accuracy• Wide PWM frequency – fixed 250 kHz, 500 kHz or adjustable

250 kHz to 700 kHz• Load protected by peak current limit and thermal shutdown• Internal slow start• Adjustable undervoltage lockout• Synchronizes to external clock• Packaging: Available in 16-pin PowerPAD™ TSSOP • Suggested resale price starts at $2.35 each in quantities of 1,000

Get samples, datasheets, app reports, EVMs and software tool at:www.ti.com/sc/device/TPS54350

TPS543504.5-V to 20-V Input, 3-A Step-Down Converter in TSSOP-16

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B070804

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms andconditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes noliability for applications assistance, customer’s applications or product designs, software performance, or infringement of patents. The publication of informationregarding any other company’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

© 2004 Texas Instruments IncorporatedPrinted in U.S.A. by (Printer, City, State)

Printed on recycled paper SLYB113

Real World Signal Processing, the black/red banner, Auto-Track, PowerPAD, Predictive Gate Drive, SWIFT and TPS40K are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.

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