Power Management on i - NXP Semiconductorssupports many advanced techniques for power management...

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TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Power Management on i.MX Lalan Mishra i.MX Systems Solutions Manager and Specialist July 2009

Transcript of Power Management on i - NXP Semiconductorssupports many advanced techniques for power management...

Page 1: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.

Power Management on i.MX

Lalan Mishrai.MX

Systems Solutions Manager and Specialist

July 2009

Page 2: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Session Objectives

►Fundamentals of Power Management►Power Management Features on i.MX

Family

►Power Management ICs►Making Power Measurement ►Conclusion

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Page 3: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Fundamentals of Power Management

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Page 4: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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A Common Hand-held device Scenario

►What do we observe?

►One main power source► Multiple power rails► Power conversion is a must► Conversion efficiency important

Page 5: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Power Conversion : The Basic Building Blocks

Regulators

Linear Switching

Standard LDO BUCK BOOST BoB

2.7

4.2

Linear Regulator

Switching Regulator

1.4V

24V

Li+ Operating Range

BUCK

BoB

BOOST

Page 6: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Power Conversion : The Basic Building Blocks

VPASS

VPASS X IL = Power Lost in Heat

Switching regulators use the energy stored in magnetic field of an inductor to achieve power transfer. If the elements involved in thisenergy transfer be ideal then alossless regulation would be possible.

Basic Buck ConfigurationBasic Linear Regulator

Standard and LDO linear regulators areequally bad when it comes to power loss.

Page 7: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Power Conversion : The Basic Building Blocks

Switched-Cap Regulator ► Switched-Cap regulators use capacitor based charge transfer technique.

► High efficiency (95%+) conversion for loads needing small current (up to 100mA)

► Efficiency = Vout/(Vin*Gain)RL

Page 8: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Power Conversion Efficiency at A Glance

SW Cap (Gain=0.5) vs. LDO

Buck

BoB

LDO is the least efficient power regulator. Yet,we can’t completely say NO to LDO. So, we better have LDOs with least drop-out voltage when needed.

Page 9: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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The Key Factor in conversion Efficiency

Keep it COOL!Minimize IR loss in all possible ways.

Page 10: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Power Losses in CMOS Circuits

Pdynamic

•Gate-oxide Tunneling Current•Source-to-drain sub-threshold conduction

•p-n junction leakage

DVFS + DPTC Process Tech. + AWB

P d y n a m i c C L V dd2

× fC L K×∝

Pstatic

Ptotal

1.

Run faster only when needed (Freq. Scaling)2.

Use minimal operating voltage (Voltage Scaling)

Page 11: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Power Management Features on i.MX

Page 12: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Advanced Power Management Features on i.MX

►Power Gating for 3 different power domains in Stand-by

►Dynamic Frequency and Voltage Scaling (DVFS)

►Dynamic Process Temperature Compensation (DPTC)

►Active Well-Biasing

► Independent Peripheral Clock Gating

►Low Power Modes

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i.MX Power Domains

ARMPlatform L2

Cache

PeripheralPLL

ONStand-byOFF

ONStand-byOFF

ActiveStand-byStopShut-down

ON

OFF

Page 14: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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System Power ModesRUN Normal operating mode. Core frequency and operating voltage can be

dynamically changed within a range.

Wait MCU clock remains gated. Operation resumes on interrupt.

Doze MCU and MAX clocks remain gated. Operation resumes on operation.

Peripherals not requiring MCU/MAX functionality can remain active. Normal operation resumes on interrupt.

State Retention MCU and peripheral clocks gated. SDRAM in self-refresh mode. Supply voltage can be dropped to minimum.

Deep Sleep Clocks gated. ARM platform power supply OFF. Normal operation resumed on interrupt.

Hibernate All power OFF. System completely dead; operation resume equivalent to cold boot.

Page 15: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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DVFS and DPTC : High Level S/W Architecture

Policy Daemon

PM & SDMA

drivers

DVFS & SDMA HW

CCM / PMIC

Policy Daemon –

controls the way in which the DVFS is performed (the way the system load is analyzed and changed), monitors the system loads and provides a human interface.

Abstraction layer -

passes configuration and data from the daemon to the DVFS controller, passes performance logs from the DVFS controller back to the policy daemon.

CCM / PMIC hardware –

set the current voltage and frequency.

DVFS & SDMA Controllers –

monitor the current load and configures the PMIC and CCM.

Software

Hardware

Page 16: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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DVFS Driver Architectural Overview

PerformanceLevel/patterns+ Configuration

New Performance

Log

PerformanceLevel/

patterns

ConfigurationPerformance

LogDVFSPolicy/ MonitorDaemon

PMDriver

DVFSHardware

CCMSDMA Driver

SDMA Controller

New PerformanceLog + Status

+ events

Configure

Status

Task hints

Embedded ModulesOS kernelUser spaceUser External hardware

PMIC

New voltage

level

Kernel hooks & handles

Page 17: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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DPTC Driver Architectural Overview

DVFSPolicy/ MonitorDaemon

DPTC Monitor

HumanInterface

Program Interface

Configuration

CCM

Embedded Modules

OS kernelUser spaceUser External hardware

PMIC

Kernel hooks & handles

DPTC Controller

Linux power management

Power aware programs SPIPMIC

Driver

SDMA Driver

Power ManagementDriver

Power ManagementDriver

Power ManagementDriver

SDMA Controller

DVFSHardware

Power ManagementDriver

Page 18: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Available Power Management ICs

Page 19: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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A Few Choices For Power Management IC

Source Part

Freescale MC13892JVK (7x7 BGA, 0.5mm pitch)

MC13892JVL (12x12 BGA, 0.8mm pitch)

MC34704, MC13783Wolfson WM8350

National Semiconductor LP3971

Others (Linear, Philips etc) LTC3455, PCF50633, xyz..

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently

are not available from Freescale for import or sale in the United States prior to September 2010: MC13783

Page 20: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Making Power Measurements

Page 21: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Suggested Power Measurement Techniques

DC

V2

V1

LoadR (Fixed)

iLoad current

i

i = V1/R ……..(1)

P = V2*i …… (2)

P = ( V2*V1 )/ R …(3)

USB 6259 from NICurrent sense-amplifier highly suggested for sensingThe load current. Ex. –

MAX4072

Page 22: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Investigating The Accuracy of the DAQ Based Measurement

V1

V2

Due to channel muxing,narrow

current spikes can be missed; causing measurement error. This issue can be addressed by multiplying V1 and V2 in the analog domain.However, this may bring the calibration issue in picture.

Page 23: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Using Analog Multiplier V1

1

1

X V3

VRef1

Use of VRef

and Mux

for calibration purpose.Scaling Factor = ( VRef1* VRef2 ) / Vmeasured

( V1*V2 )/ V3 = ( VRef1

* VRef2

) / Vmeasured

Power = ( V1*V2 )/ R = [ ( VRef1* VRef2 * V3 ) / ( Vmeasured

* R) ]

Vmeasured

V2

VRef2

Page 24: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Conclusion

Page 25: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Conclusions

► Power efficiency depends on many factors.

► High conversion efficiency of the power conversion block is very important.

► i.MX

supports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number of operating modes are supported to achieve highest possible run-hours.

► i.MX

operation has been validated for a number of PMICs.

► Accurate measurement is a must to gauge the true power numbers.

Page 26: Power Management on i - NXP Semiconductorssupports many advanced techniques for power management like DVFS, DPTC, Clock and power gating and Active-well biasing. Additionally, a number

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Q&A

►Thank you for attending this presentation. We’ll now take a few moments for the audience’s questions and then we’ll begin the question and answer session.

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