Power Distribution Studies at Fermilab

Aida Todri, FNAL

ATLAS/CMS Power WG Meeting

March 31st , 2010

Outline

Panel test stand. System setup.

DC-DC conversion powering scheme tests: Efficiency measurements. Cooling impact on converter. Pixel performance measurements.

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Panel Test Stand

3

CAPTAN DAQ system, 12bit ADC, 65MHz

Panel 21 ROCs, TBM, 40MHz, Ianalog~1.35A, Idigital~1.5A with external load

Converters AMIS2 DC-DC converters for VA and VD.

Pixel Calibration

4

Analog signal in ADC counts from all the readout chips in a panel sampled by the front-end digitizer. Decoding of analog signal.

DC-DC Converters

5

Chip: AMIS2 by CERN Vin=6-12V Iout<3A Vout=3.3V fs=600kHz..3MHz

PCB: Aachen 2 copper layers External air-core

inductor L=550nH, R=80mΩ

AMIS2

Efficiency Measurements (w/o cooling)

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DIGITALTemp Vin In Vout Iout Eff

room = 28˚C

8 0.798 3.327 1.492 77.76%8.5 0.755 3.327 1.492 77.35%

9 0.716 3.331 1.494 77.23%9.5 0.685 3.341 1.488 76.40%10 0.656 3.347 1.5 76.53%

10.5 0.632 3.355 1.503 75.99%11 0.608 3.362 1.505 75.66%

11.5 0.59 3.372 1.513 75.19%12 0.571 3.38 1.507 74.34%

ANALOGTemp Vin In Vout Iout Eff

room = 28˚C

8 0.725 3.35 1.37 79.13%8.5 0.69 3.36 1.37 78.49%

9 0.657 3.36 1.37 77.85%9.5 0.63 3.37 1.38 77.70%10 0.608 3.38 1.38 76.72%

10.5 0.583 3.38 1.38 76.20%11 0.569 3.4 1.4 76.05%

11.5 0.549 3.4 1.4 75.39%12 0.533 3.41 1.4 74.64%

8 8.5 9 9.5 10 10.5 11 11.5 1272.00%

73.00%

74.00%

75.00%

76.00%

77.00%

78.00%

79.00%

Converter Input Voltage (V)

Effi

cie

ncy

8 8.5 9 9.5 10 10.5 11 11.5 1272.00%

73.00%

74.00%

75.00%

76.00%

77.00%

78.00%

79.00%

80.00%

Converter Inputer Voltage (V)

Effi

cie

ncy

Impact of Chip Cooling

7

Observation : Cooling the converter chip ~20˚C impacts the regulator and decreases the voltage level being supplied to the panel. Cause degradation in the signal pulse.

w/ cooling

no cooling

Temperature Measurement

8

Ton_chip=70˚C

Ton_ind=88˚C

Ton_chip=69˚C

Ton_ind=106.8˚C

no cooling with air fan cooling

Efficiency w/ Cooling

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8 8.5 9 9.5 10 10.5 11 11.5 1266.00%

68.00%

70.00%

72.00%

74.00%

76.00%

78.00%

80.00%

Analog

with_coolingno_cooling

Converter Input Voltage (V)

Effi

cie

ncy

8 8.5 9 9.5 10 10.5 11 11.5 1271.00%

72.00%

73.00%

74.00%

75.00%

76.00%

77.00%

78.00%

79.00%

80.00%

Digital

with_coolingno_cooling

Converter Inputer Voltage (V)

Effi

cie

ncy

Power Supply Noise

No converter w/ DC-DC converters

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Vout=3.26V, Vin=9VTemp=62.8˚C

Vout=2.42V

∆=278mV

Performance Measurements

S-Curve Test:

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To measure the signal threshold and noise level of each pixel.

Efficiency of the pixel is derived as a function of the amplitude of the calibration signal.

Each pixel response is obtained by injecting calibration pulses with different Vcal DAC values (1Vcal=65e).

S-Curve calibration is run with and without DC-DC converters.

Noise and Threshold Dispersion

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Pixel Noise Maps

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Threshold Dispersion Maps

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Serial Powering Test Stand

SPi Chip: FNAL Vshunt=1.2 to 3V Iseries=0 to 4A

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CAPTAN sending data packets to program the SPi chip to operate at different modes.

SPi powered through a power supply source by limiting current.

Limited current output to drive a plaquette or panelUsed ~ 250mA

Next Test Setup

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CAEN A4603

DC-DC Conversion

Panel

Setup modified CAEN A4603 module to power up the chips Perform test a lower temperatures (chiller box) Perform test with a magnet 1.5T.

Conclusions Currently:

Performing power integrity tests on the panel system

Performing pixel performance measurements Characterizing the DC-DC converter and serial

powering schemes and their efficiencies Next Steps:

Continue with performance measurement studies for DC-DC powering scheme.

Complete test stand setup using: CAEN power supply, magnet, cooler temps.

Testing of serial powering scheme Efficiency comparisons between two schemes.

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