Power Distribution for the LAr calorimeters for the HiLHC Marco Riva Università degli Studi di...

Power Distribution for the LAr calorimeters for the

HiLHC

Marco Riva

Università degli Studi di Milano

M. Alderighi(1,6), M. Citterio(1), M. Riva(1,8), P. Cova (3,10), N. Delmonte(3,10), A. Lanza(3), R. Menozzi(10), A. Paccagnella (2,9), F. Sichirollo(2,9), G. Spiazzi(2,9), M. Stellini(2,9), S. Baccaro(4,5), F. Iannuzzo(4,7), A. Sanseverino(4,7), G. Busatto(7), V. De Luca(7) (1) INFN Milano, (2) INFN Padova, (3) INFN Pavia, (4) INFN Roma, (5) ENEA UTTMAT, (6) INAF, (7) University of

Cassino, (8) University of Milano, (9) University of Padova, (10) University of Parma

on behalf of the INFN-APOLLO collaboration

http://www.mi.infn.it/indexIT.shtml

http://www.unipd.it/index.htm


sLAr Electronics Meeting - M. Riva

Outlines

• APOLLO project:– Power Distribution Proposal for the LAr

Calorimeter• Design and preliminary tests of the Main

Converter and PoL• Engineering Issues:

– Thermal Design;– Magnetic Materials with High saturation;– Analog/Digital/Power Devices selection:

• Behavior in radiated environment

December 6, 2011



The APOLLO Project:LV Power Supplies For The Next

High Energy Physics Experiments

Full replacing the present systems whose design dates from early 2000 years: new and improved design possibility;

Minimization of power loss in cables used for carrying current from PS distributors to the front-end of detectors push the distributors as close as possible to the front-end;

New and more severe environment requirements: Increased rad-hard performance, because of the increased luminosity of

accelerators; Increased B-tolerance of systems getting closer to detectors and magnets;

Better reliability and controls, in order to reduce access time and increase the overall detector efficiency;

Avoiding industrial intellectual property, trying to implement the CERN Open Hardware policy;

December 6, 2011



Power Distribution Architecture for LVPS: Present status

ATLAS Experiment

Power Distribution System for the FEB of the LAr Calorimeters

19 Low drop-out regulators/FEB

December 6, 2011



Power distribution architectures

Factorized Power Architecture

• High number of long connection cables (penalty in volume and weight)• Low flexibility• High losses mainly in unique hot spot + losses in linear regulator LDO• Possible cross-talk effect between the power supply.

High Voltage Drop

• Improvement in the efficiency • Independent control of the different loads• Not optimal solution considering weight and size• High number of devices

Low Voltage Drop

Optimized Voltage Drop

High static regulation and improvement of the dynamic performances(the impact of the series resistance and inductance is reduced)

The DPA approach benefit from increased efficiency, low size and weight

1. Centralized Power Architecture (CPA): • An isolated DC/DC converter generates the whole set of regulated DC voltages (±12V, ±5V and +3.3V)

supplying the circuit subsystems. 2. Decentralized Power Architecture:• The low voltage distribution is moved close to the load by means dedicated converters;3. Distributed Power Architecture (DPA):• A single intermediate DC bus (+48V or +12V) is generated by a main converter 4. Intermediate Bus Architecture (IBA)• In addition to the generation of a main voltage bus (48V-76V), a second set of BUS voltages are provided

(8V-14V). Lower voltages are given by the point-of-load converters.5. Spot Power Architecture • Intermediate solution between CPA and DPA. In addition to the voltage bus typical of DPA, one or more

voltage lines supply the circuits directly. 6. Factorized Power Architecture (FPA) • A “factorized” bus (26V-55V) not stabilized and not galvanic insulated supply the POL by means dedicated

converters.

December 6, 2011



The APOLLO proposal – System architectures

• Rationalization of the number and level of the voltages required by FEBs– only few intermediate voltages must be supplied (one or two)– loads must be served by PoLs regulators

• Possibility of adopting non-traditional topologies:– modular approach (possible benefit for other detectors) – higher switching frequency– optimized design of magnetic devices– minor losses and heat– reduced voltage across devices

Upgrade from “Centralized Power Architecture” to

“Distributed Power Architecture”

December 6, 2011



CRATE

Proposed Power Distribution Scheme

280 Vdc

MainDC/DC

Converter

FEB #3

POLPOLLDO

Converter

POLPOLLDO

Converter

POLPOLLDO

Converter

FEB #2

POLPOLLDO

Converter

POLPOLLDO

Converter

POLPOLLDO

Converter

FEB #1

PoLPoLniPoL

Converter

PoLPoLniPoL

Converter

PoLPoLniPoL

Converter

12Vdc5%

Regulated DC bus

PoL = Point of Load

December 6, 2011

48Vdc5%

High DC conversion ratio converters



Muon Detector

Distributed Power Architecture proposal for the Moun Detector

280 Vdc

MainDC/DC

Converter

POLPOLLDO

Converter

POLPOLLDO

Converter

POLPOLLDO

Converter

POLPOLLDO

Converter

POLPOLLDO

Converter

Chamber #1

PoLPoLniPoL

Converter

PoLPoLniPoL

Converter

Regulated DC bus

Chamber #2

Chamber #3

Case study:The DC/DC Power Converter adopted for the Moun Detector could benefit from the modular approach adopted in LAr calorimeter.

December 6, 2011



Critical problems

• Electromagnetic immunity of the front-end electronics to the switching converters

• Converters Design (Main and PoLs)– Number and levels of intermediate voltages

• How many? Positive and negative?• Which levels? High for loss reduction or lower for a reasonable POL design (voltage ratio)?

– Redundancy N+1 (single failure tolerance)• Modular approach: number of modules Vs total power oversizing

– Thermal design• Power losses distribution

• Analog/Digital/Power Devices– Active switches selection

• Power and voltage level• Switching frequency• MOSFETs, SiC, GaN

– Analog/Digital Controllers• PWM Controllers• Drivers• Signal Isolators• FPGAs

– Design of magnetic parts• Coreless devices• Low permeability cores• Thermal analysis

High radiation & magnetic field tolerance

Water cooled

December 6, 2011



Preliminary FEB EM Noise Tolerance Tests with PoL Converter

December 6, 2011

• IR3841 – Integrated 8A Synchronous Buck Regulator

• Greater than 96% Maximum Efficiency• Wide Input Voltage Range: 1.5V to 16V• Wide Output Voltage Range: 0.7V to 0.9*Vin• Continuous 8A Load Capability• Programmable Switching Frequency up to

1.5MHz• Programmable Over Current Protection

• LTM4602 – 6A High Efficiency DC/DC μModule

• Complete Switch Mode Power Supply• Wide Input Voltage Range: 4.5V to 20V• 6A DC, 8A Peak Output Current• 0.6V to 5V Output Voltage• 1.5% Output Voltage Regulation• Up to 92% Efficiency• Output Over Voltage Protection

Jim Kierstead, Sergio Rescia, Hucheng Chen, Francesco Lanni (Brookhaven National Laboratory)



Summary of the preliminary EM tests

• Irradiated noise of PoL Converters– Outside FEC:

• Negligible effect on coherent noise

– Inside FEC:• Shielding is necessary to achieve good noise

performance inside FEC

• Conducted noise of PoL Converters– Negligible effect on coherent noise

December 6, 2011



The Main Converter is based upon a DC-DC Phase Shifted Converter well suited for multi-outputs, or-ed connection and constant load supply (single pole dynamic).

The whole unit is constituted by 3 modules connected in parallel:

Vin=280 VVout= 12VPout= 1.5 kWfs=100kHz

The supervisor and protections are demanded to an external interface:•current Sharing •start-up control/failure•clock, phase shift between the modules, Alarms

The APOLLO proposal - MC

December 6, 2011



Switch In Line Converter

DrawbacksHigh drain current levelsHigh number of large capacitors

MeritsHigh switching frequencyFixed switching frequencySoft switching commutation(use of parassitics elements: leakeage inductance)

Single pole dynamicsWell suited for multiple outputsSuited for or-ed outputsReduced MOS drain-source voltageNon-isolated feedback available

December 6, 2011



How SILC topology works

Vin

Cp4

Cp3

Cp2

Cp1T1

T1' IL

D4

D3

D2

D1

4

3

2

1

L

13

12

11

10

IT1

S4

S3

S2

S1

C

C

C

C

+

-

6

5

Vin-2Vo

2Vo

0

400V800W

D1

D2

D3 D4

Ts11

Ts12

C01

C02

+12V 790W

10W-12V

0

R

R

01

02

AUX

t

IL

December 6, 2011



The transformer is constituted by 2 primary windings and 1 low voltage secondary winding (5:5:1) traditional windings planar structure

XThe whole transformer has been divided in 4 subsystems

Each subsystem consists by 10 turns for each primary windings and 2 turns for the center tapped secondary.The secondary has been realized by means of the parallel connections of 2 windings in order to reduce the output leakage inductance.

Power Transformer Design

December 6, 2011



4.71mm22 layers 10 layers

2 turns for every layers

4 layers

4 layers

The windings of each subsystems are realized by means of a 22 layers PCB

“Subtransformer” Design

Thermal Layer for heat dissipation

UL94V-0

December 6, 2011



Single Module View

130 60

315

December 6, 2011



Experimental Tests

Open loop operation: Ch1) gate-source command of the lower MOS Ch2) inductor currentCh3) M1 drain-source voltage Ch4) M3 drain-source voltage

200 400 600 800 1000 1200 1400 16000.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

Output Power [W]

Eff

icie

ncy

Efficiency Vs Output Power

December 6, 2011



Dynamic measurement: Gloop

101

102

103

104

105

-20

-10

0

10

20

30

40

Mag

nitu

de [

dB]

101

102

103

104

105

-200

-150

-100

-50

0

50

Frequency [Hz]

Pha

se [

deg]

@350 W

@400 W@450 W

Control to Output (Gloop) dependency from output power

December 6, 2011



Design of PoL Converter: Synchronous Buck

• The requirement of high B (2-4T) makes mandatory the use of coreless solution (inductance in air);

• The value of the inductance is limited to few 100nH;– High current ripple (DiLpp > 2IL) -> High C in order

to limit the output ripple– High switching frequency

December 6, 2011



Interleaved Buck with Voltage Divider - IBVD

S1 S2

S3

S4

L1

CoR

C1

L2

Ug uo

+

-uC1

+

i1

i2

D<50% Uo = UgD/2 e UC1 = Ug/2

D>50% Uo = UgD2 e UC1 = Ug(1-D)

Phase shift TS/2

December 6, 2011



How IBVD works: D < 0.5

iL1

iL2

L2

L1S2

S4

S1

S3

Ug uoRoCoC1

+ +

iC1

uC1

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

oi

iL1+iL2

t

t

0

L

UUU o1Cin L

Uo

L

UU o1C L

Uo

iL2

-iL1

2

TssDT sT

0 < t < DTS

December 6, 2011




iL1

iL2

L2

L1S2

S4

S1

S3

Ug uoRoCoC1

+ +

iC1

uC1

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

oi

iL1+iL2

t

t

0

L

UUU o1Cin L

Uo

L

UU o1C L

Uo

iL2

-iL1

2

TssDT sT

DTS < t < TS/2

December 6, 2011




iL1

iL2

L2

L1S2

S4

S1

S3

Ug uoRoCoC1

+ +

iC1

uC1

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

oi

iL1+iL2

t

t

0

L

UUU o1Cin L

Uo

L

UU o1C L

Uo

iL2

-iL1

2

TssDT sT

TS/2 < t < TS/2+ DTS

December 6, 2011




iL1

iL2

L2

L1S2

S4

S1

S3

Ug uoRoCoC1

+ +

iC1

uC1

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

oi

iL1+iL2

t

t

0

L

UUU o1Cin L

Uo

L

UU o1C L

Uo

iL2

-iL1

2

TssDT sT

TS/2+ DTS < t < TS

December 6, 2011




iL1

iL2

L2

L1S2

S4

S1

S3

Ug uoRoCoC1

+ +

iC1

uC1

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

oi

iL1+iL2

t

t

0

L

UUU o1Cin L

Uo

L

UU o1C L

Uo

iL2

-iL1

2

TssDT sT

2

D

U

UM

g

o 2

1

U

U

g

1C

2

IIIIII o21o12

December 6, 2011



IBVD: experimental characterization

Cin = 100nF + 10mF Co = 2x47nF + 4x2.2 mF C1 = 2x470nF (1206)

L1 = 161nH – 58mW L2 = 169nH – 63mW S1,4 = IRF8915

Cin = 100nF + 10mF Co = 2x47nF + 2x47mF + 2x10mF

L = 90nH – 30mW Q1,2 = 2xIRF8915

IBVD

Single buck

input

output

December 6, 2011

Design @ fs = 1MHz

Input Voltage: Ug = 12 V

Output Voltage: Uo = 2.5 V

Output Current: Io = 3A

Size: L = 6cm, W = 4.2cm



Efficiency comparison @ fs = 2MHz

Efficiency comparison

0.6

0.62

0.64

0.66

0.68

0.7

0.72

0.74

0.76

0.78

0.8

0.82

0.84

0.86

0.88

32.521.51

Output current [A]

Eff

icie

nc

y

Single Buck

Interleaved Buck with Voltage Divider

December 6, 2011



High Current IBVD

Input Voltage: Ug = 12 V

Output Voltage: Uo = 2 V

Output Current: Io = 20A

Switching Frequency: fs = 280 kHz

2.2 mH (iron core inductance)Size: L = 7cm, W = 3.5cm

Co

C1

Cin

L1L2

S1

S3

S4

S2

Control circuit on the other side of the PCB

S1 S2

S3

S4

L1

CoR

C1

L2

Ug uo

+

-uC1

+

i1

i2

December 6, 2011



IBVD

0.78

0.8

0.82

0.84

0.86

0.88

5 10 15 20

IBVD

Efficiency

Output current [A]

December 6, 2011



• Water cold plate

• System Level boards and cold plate position

• Board Levelmain heating devicesmodules layoutheating convection and conduction

• Device Levelpackage definitionheating exchange between single components

Thermal Modeling – Top-Down Approach

December 6, 2011



Modeling (and Simulations) @ System Level

Outiside crate

• Outlet water temperature required 25°C• Maximum cold plate internal temperature: 35°C• (The power losses distribution have been supposed uniform !)

18°C 29°C 35°C

Liquid Internal surface

December 6, 2011

Liquid Cooled Chassis:2 mm 1510 steel case containing 3x1kW main converter modules cooled by cold plates

3D Thermo-fluidynamic FEM of working and faulty converters



Simulation in case of failure

• Maximum cold plate internal Temperature 45°C• External Wall 18°C GOOD (required: 18 °C)

Outside crate

18°C 34°C 45°C

Liquid Internal Surfice

December 6, 2011

Liquid Cooled Chassis:2 mm 1510 steel case containing 2x1.5kW main converter modules cooled by cold plates

3D Thermo-fluidynamic FEM of working and faulty converters



Modeling @ Device LevelPackages: TO-220 and D2PAK Device Model

(1) FR4 (2) IMS (3) FR4+Slcn (4) FR4 with thermal vias

Layers considered:

M. Bernardoni et al., ESREF’09, Arcachon (F), 5-9 ott. 2009.

December 6, 2011



Simulation of different packages

(1) FR4 (2) IMS

(3) FR4+Slcn

(4) Th. vias

December 6, 2011



Modeling @ Board Level: the MC prototype

Rif. N°

DevicePD [W]

1 MOSFET MC (TO247) 52 Planar Trasf. - Core 1003 Planar Trasf. – Windings 654 Diode (ISOTOP) 355 Inductor 5

6Cu traces for the

secondary 57 MOSFET AUX (TO247) 0,18 AUX Transf. – Core 0,59 AUX Transf. – Windings 0,5

10 AUX MOSFET (D2PAK) 0,511 Capacitors <0,1

Total Power Loss 217

December 6, 2011



FE Physical definition and meshing

Mesh with 265.000 freedom levels

December 6, 2011



Simulation Results

Maximum temperature acceptable (considering Text = 28 °C)

December 6, 2011



Thermal measurements Vs simulations

The experiment has been done with air cooling system

Pout = 1.2 kW (Iout 100 A)

December 6, 2011



Planar Transformer Tests in Bstat

• The behavior of the planar transformer and in particularly of the low permeability magnetic core (Koolm by Magnetics) has been tested in condition close to the normal operation : Vcc=70, fs=100kHz.

December 6, 2011



Experimental Set-up

Several values of magnetic field have been used to test the transformer: Bstaz=[789, 1295 , 1533, 1987, 2247 e 2591] Gauss.

The external Bstaz influenced the normal operation in grater way when approaching to the saturation

Zoom of the magnet gap at the INFN-LASA test facility

December 6, 2011



Transformer behavior in stationary Magnetic Field

11/16/2011 46

orange = primary winding voltage blue = secondary winding voltagemagenta = primary winding currentgreen = snubber current (proportional to the switching losses).

Bstat. 789 Gauss Bstat. 2591 Gauss

December 6, 2011



Soft ferromagnetic materials for enhanced inductor cores

• Optimization of the inductor core material for DC-DC switching power supplies– Need of high of reliability magnetic cores of devices

for extreme condition environments:• High immunity to radiations • High magnetization field and low coercive field

– High Br Low Hc

• Higher switching frequencies of the DC-DC converters • Smaller dimensions of the inductors

December 6, 2011


http://www.fnspa.it/Default.aspx


FeSi compound

• Better high-frequency inductor core performance

• Avoidance of magnetostriction phenomena

• Increase anisotropy • Enhanced soft

magnetic properties

Starting from power

Composition: Fe-6.8%Si Grain size: 20-30 micron

December 6, 2011



Fabbrication process

• Metal Injection Moulding (MIM) • FeSi powder + polymer binder (“green”

material) • Debinding at 600°C • Sintering at 1260°C

December 6, 2011



Challanges

• Cold ductility of such material makes its manufacture hard;

• Use of a hydrogen atmosphere to avoid Fe oxidation during sintering;

• Hard and time-expensive recipe tuning;

• MIM parameters set: temperature of the material, of the cylinder and mould, pressure of injection, hold pressure, injection speed and screw feeding speed, time for the injection, time for hold pressure, time of cooling.

December 6, 2011



Prototype radiation tests

• The prototype has been exposed to a dose of 5 kGy

• At a dose rate conditions of 100 Gy/h, during 2 days of exposure in the 24 hours

December 6, 2011



Preliminary ResultsI

Initial local fusion of the polymeric component and a less crystallinity

December 6, 2011



Preliminary ResultsII

Detail of the polymeric ageing

December 6, 2011



The APOLLO proposal – Rad-hard devices

• Seeking for power COTS MOSFETs radiation tolerant up to 10kGy and 1014/(s ∙ cm2) neutrons and protons:

• many components, with Vd ranging from 30V to 200V and polarized in various configurations, were tested at the 60Co g ray source in the ENEA center of Casaccia, near Roma

• same components were tested with a heavy ion beam, 75Br at 155MeV, at INFN Laboratori Nazionali del Sud in Catania

• within the end of the year same components will be tested under neutrons, at the Casaccia nuclear reactor Tapiro, and under protons, at INFN LNS

• Seeking for COTS controllers and FPGA radiation tolerant:• first irradiation was performed under 216MeV proton beam in Boston, at

Massachusetts General Hospital facility, using some of devices irradiated in Italy. Other irradiation campaigns are planned at the same facilities in the next months

Results are still preliminary and under analysis. Other irradiation campaigns are necessary in order to select good devices.

December 6, 2011


Circuit set-up for g tests

• Four parallel tests:– Vdd=0 and Vgg=const. (80%Vgg,nom)

sensitivity to the oxide bias– Vgg=0 and Vdd=const. (80%Vdd,nom)

sensitivity of the bulk (junction) of the device

– Vdd=80%Vdd,nom and Vgg switching sensitivity to the dynamic gate bias

– three leads shorted reference condition


Vgg=const. Vdd=const.

switching shorted

December 6, 2011



Switching condition effect during radiation - 30V MOSFETs –

December 6, 2011



Switching condition effect during radiation - 200V MOSFETs –

Device B1

December 6, 2011



Asym./Sym. Switching Comparison

December 6, 2011



Susceptibility to dose rate- 40Gy/h vs. 10Gy/h -

December 6, 2011

40Gy/h



VTH SiC JFETs

December 6, 2011



Ron SiC - SiC JFETs -

December 6, 2011



Combined effects: g rays and Heavy Ions

December 6, 2011

Devices under test:

30V STP80NF03L-04

30V LR7843

200V IRF630

Used doses:

I 1600 Gray

II 3200 Gray

III 5890 Gray

IV 9600 Gray

Measurements :

Breakdown Voltage @ VGS=-10V

Threshold Voltage @ VDS=5V

ON Characteristic @ VGS=10V

Gate Leakage @ VDS=10V

For each type of device 20 samples were tested, 5 for each dose value

(g rays at the ENEA Calliope Test Facility)



The device is in “OFF” state and biased at constant VDS and VGS voltages

The SEE experimental set-up

December 6, 2011Fast Sampling Oscilloscope

Parameter Analyzer

N+

Drain

P +

N +

P _

GateSource

N_

Body

N+

Cg

Cd

50 W

50 W

1 MW1 MW

Vgs

Impacting Ion DUT

Vds

0 500 1000 1500 2000-2.0

-1.5

-1.0

-0.5

0

Time [s]

Gat

e L

eaka

ge C

urre

nt [

A

]

20 40 60 80 100 120

0

5

1

15

Time [ns]

Cur

rent

[mA

]

The current pulses

The IGSS evolution during irradiation



The SEE experimental results

December 6, 2011

Device TID Bias Conditions during Irradiation

Drain Damage Gate Damage

D21 0Gy Vds=20V-110V vgs=-2V Vds=100V-110V Vds=100V-110VD06 1600Gy Vds=20V-70V vgs=-2V Vds=60V-70V Vds=60V-70VD10 3200Gy Vds=20V-50V vgs=-6V Vds=40V-50V Vds=40V-50VD16 5600Gy Vds=20V-50V vgs=-6V Vds=45V-50V Vds=40V-45VD17 9600Gy Vds=20V-45V vgs=-6V Vds=40V-45V Vds=40V-45V

The increase of the ϒ-dose causes a reduction of the critical bias condition at which drain and gate damages appear

200 V Mosfet: IRF630



Only 200V MOSFETs (IRF 630, samples from two different manufacturers) were exposed

Proton energy: 216 MeV (facility at Massachusetts General Hospital, Boston)Ionizing Dose: < 30 Krads

An “absolute” cross section will require the knowledge of the area of the MOSFET die which is unknown.

10-12

10-11

10-10

10-9

10-8

10-7

182 184 186 188 190 192 194 196

IRF630 - ST

Cro

ss S

ect

ion

[cm

-2]

VDS [Volt]

10-12

10-11

10-10

10-9

10-8

10-7

175 180 185 190 190 195

IRF630 - International Rectifier

Cro

ss S

ect

ion

[cm

-2]

VDS [Volt]

MOSFETs Exposed to Protons

December 6, 2011

The results are still preliminary.



MOSFETs Exposed to Protons• The number of SEB events recorded at each VDS was small• less then 30 events for the ST• less than 150 events for the IR devices

• Large statistical errors affect the measurements

• The cross section at VDS = 150V (“de-rated” operating voltage) can not be properly estimated– Dependence from manufacturer– “Knee” not well defined

• To effectively qualify the devices for 10 years of operation at Hi-LHC, the cross section has to be of the order of 10-17/ cm2, which puts the failure rate at <1 for 10 years of operation.

• Proton irradiation campaigns with increased fluences and more samples are planned.

December 6, 2011

Work still in progress …


GaN Devices for fast switching

• High frequency, high voltage ratio PoL criticalities:– They must operate at low duty cycle (high voltage

ratio);– The switching period is short and operations are

achievable only with fast switching commutations;

December 6, 2011 sLAr Electronics Meeting - M. Riva

GaN devices have the potential to switch ON-OFF in the MHz range (related to the driving capability and the assembly techniques)

National Semiconductor180W 1/8th Brick, Fully Regulated Converter


Studies on GaN Devices

• The tests adopt 40V and 200V GaN devices by EPC;

• Some problems in driving and prepare the test circuit (soldering the components)

• Electrical Characterizations are in progress


X-rays for checking the solder qualityX-rays for checking the solder quality

Air bubblesAir bubblesRshuntGaN

Freewheeling diode

Driver


Preliminary electrical charcterization


VDC

vc

DRIVER

DUT

L

VCC+ C1

iDUT

+

Turn on interval @ Vcc = 100V, IDS = 0A

Rshunt = 85 mW

UGS [1V/div]

UDS [20V/div]

-IDS [1A/div]

Time [10ns/div]

Turn off interval @ Vcc = 100V, IDS = 5A

UGS [1V/div]UDS [20V/div]

-IDS [1A/div]

-poff(t) Time [10ns/div]

Measured DUT voltage and current during switching intervals


Future Activities

• Update the design of the MC and realize a new prototype;

• Investigate the use of PoL made by CERN (F. Faccio) for high current loads;

• Test the IBVD PoL converter directly on the FEBs;

• Propose/Find radiation tolerant controllers– Selection of PWM – Custom made controller by using Analog

Devices or FPGAs



Power Distribution for the LAr calorimeters for the HiLHC Marco Riva Università degli Studi di...

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