Proposal Title:

Power consumption prediction based onstatistical learning technique

Abstract

Early power estimation is a critical requirement for both SoC (system-on-chip) architects and

marketing, which must provide competitive, yet realistic, power consumption RFQs (request for

quotation) to customers in order to achieve design wins. RFQs based on deterministic techniques

may work reasonably well when there is enough information, and the available data closely match

the target design. However, this approach can be strongly design dependent, and the same

model, which provided a good estimate on one design/technology, may fail on another

design/technology with different specs and operating conditions. In this talk, we will present an

innovative approach for early power consumption estimation based on statistical learning. The

proposed statistical model has been compared against existing RFQs, and validated on two

taped-out products for networking in leading-edge CMOS technology.

Proposal Description

Statistical learning (sometimes also referred as machine learning) is a set of powerful tools for

understanding and modeling data sets and for learning from data. Statistical learning builds a statistical

model for predicting a dependent (output) variable, like power consumption, from one or more

independent (input) variables, such as supply voltage, temperature, active area, working frequency, and

switching activity. Today, these techniques are successfully used in several fields such as stock markets,

artificial intelligence, pattern recognition, computer vision, bioinformatics, spam filtering, data mining,

etc. Although data interpolation and fitting techniques (i.e., least-squares) have been used in the past, a

unified theoretical framework that gives a probabilistic interpretation to data interpolation and exploits

powerful convex optimization algorithms to solve large-scale complex problems has been proposed since

only about twenty years. Only a formal probabilistic interpretation makes data interpolation and statistical

learning suitable to solve prediction and classification problems in many different domains.

To the best of our knowledge, statistical learning has never been used before for power consumption

prediction in the VLSI domain.

Previous attempts to provide realistic and consistent power consumption RFQ estimations across a wide

range of circuits and technologies have proven unreliable, with significant discrepancies with respect to

power analysis performed with standard CAD flows in the worst-power condition. Much more

importantly, the mismatch between RFQ estimations and CAD-based power analysis has put marketing

teams in a tough position with customers, since it was difficult for them to commit on the power

consumption targets set by the customers. Current RFQs are based on spreadsheets incorporating basic

formulas for power calculation that can hardly capture the increasing complexity and heterogeneity of

large SoC designs in advanced technologies. We believe that further attempts to refine these spreadsheets

are either doomed to failure or only some partial success, as they will never be able to realistically

modeling such complex designs.

The fundamental idea underlying this work was to change the perspective. Instead of tweaking by trial-

and-error basic formulas in order to capture the design complexity and advanced technological effects,

we decided to start from a sample space of power analysis results obtained with our CAD (computer-aided

design) flow, and to consider that sample space as the training set for statistical learning. Therefore, our

contribution was to exploit statistical learning techniques to develop a model to predict the power

consumption and the related scaling factors. In particular, our approach is based on multiple linear

regression and power transformations, as outlined in this flow chart shown below.

Of course, developing a model that satisfies all the statistical significance hypotheses is not a

straightforward procedure, and finding the optimal data transformations requires a careful data analysis

and inspection. The methodology outlined in the flowchart has been developed and tested using the most

popular statistical and numerical analysis frameworks, such as R, Mathematica, and Matlab, and the

resulting model and equations can be implemented into an Excel spreadsheet.

We trained our model on the set of power consumption data obtained from the sub-blocks of an ASIC for

networking in a leading edge CMOS technology, and we tested the model on the sign-off power

consumption data of two SoC designs for networking in the same silicon technology. Although this model

was obtained and tested on a specific technology/design architecture, we believe that the general

theoretical foundations of statistical learning make our approach suitable for different design

architectures and technology nodes, and it can effectively complement deterministic RFQ estimations.

Speaker's Bio:

Davide Pandini, Ph.D.,STMicroelectronicsR&D Manager and Senior Member of the Technical Staff

Davide Pandini holds a Laurea Degree (Summa cum Laude) in Electronics Engineering from the University

of Bologna, Italy, a Ph.D. in Electrical Engineering and Telecommunications from the University of Padova,

Italy, and a Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, U.S.

He was a research intern at Philips Research Labs. in Eindhoven, the Netherlands, and at Digital Equipment

Corp., Western Research Labs. in Palo Alto, CA.

He joined STMicroelectronics in Agrate Brianza, Italy, in 1995, where he is a R&D manager and a senior

member of the technical staff. His current research interests include signal and power integrity, variation-

tolerant design, design for manufacturing, statistical design, and EMC-aware design.

Dr. Pandini has authored and coauthored more than fifty papers in international journals and conference

proceedings, and during the academic years from 1998 to 2000, he was a visiting professor at the

University of Brescia, Italy. He is a work-package manager in several funded European projects, and he is

on the program committee of several international conferences.

In 2008 Dr. Pandini was the recipient of the ST Corporate STAR 2008 Gold Award for leading the R&D

excellence team on EMC-aware design.

Since June 2015, Dr. Pandini is the Chairman of the Steering Committee of the ST Italy Technical Staff.

In September 2015, Davide Pandini served as Volunteer at EXPO2015 "Feeding the Planet, Energy for Life",

in Milano, Italy.