Powe Efficient Pll

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002 51

A Power-Efficient Wide-Range Phase-Locked LoopOscal T.-C. Chen, Member, IEEE, and Robin Ruey-Bin Sheen

AbstractThis work presents a phase-locked loop for clock

generation that consists of a phase/frequency detector, chargepump, loop filter, range-programmable voltage-controlled ring os-cillator, and programmable divider. The phase/frequency detectorand charge pump are designed to reduce the dead zone and chargesharing for enhancing the locking performance, respectively.In the design of the range-programmable voltage-controlledoscillator, the original inverter ring of a delay line is divided intoseveral smaller ones, and then they are recombined in parallelto each other. Programming the number of paralleled inverterrings allows us to generate the wide-range clock frequencies. Thisdesign shuts off some inverters that are not in use to reduce powerconsumption. To allow the phase-locked loop to shut off inverters,the feasibility of using controllable inverters by the output-switchand power-switch schemes is explored. Theoretical analyses indi-cate that power consumption of the voltage-controlled oscillatordepends on transistors sizes rather than operating frequencies.

By applying the TSMC 0.35- m CMOS technology, the proposedphase-locked loop that uses the power-switch scheme can yieldclock signals ranging from 103 MHz to 1.02 GHz at a supplyvoltage of 1.8 V. Moreover, power dissipation that is proportionalto the number of paralleled inverter rings is measured with 1.32 to4.59 mW. The phase-locked loop proposed herein can be used invarious digital systems, providing power-efficient and wide-rangeclock signals for task-oriented computations.

Index TermsClock generator, low power, phase-locked loop,voltage-controlled oscillator.

I. INTRODUCTION

ADVANCES in microelectronic technologies have led to

the integration of millions or billions of transistors ina single chip capable of operating at a high clock frequency

to provide large computation capabilities [1]. When utilized

to enhance multimedia computing and communications, this

microelectronic chip or processor must manipulate various

media such as image, video, speech, audio, graphics, and

text. The computational complexities markedly differ for

various media applications and network transmission rates. The

availability of a processor capable of operating at distinct clock

frequencies to fulfill the real-time requirements of various

media applications would make it feasible to efficiently use

power to accomplish desired tasks. In addition, when portable

devices and mobile phones operating at idle, stand-by, and

active modes are considered, the clock generator must provide

different output frequencies in a low-power operation manner.

To implement an on-chip clock generator, the charge-pump

phased-locked loop (PLL), which is easily realized by integrated

Manuscript received November 7, 2000; revised June 21, 2001. This workwas supported in part by the National Science Council, Taiwan, under ContractNSC 88-2736-L-194-003.

The authors are with Signal and Media Laboratories, Department of Elec-trical Engineering, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C.(e-mail: [email protected]).

Publisher Item Identifier S 0018-9200(02)00133-6.

circuits as having low power dissipation, is widely adopted [2],

[3]. The modifiedphase detector and charge pump have been ex-tensively used to enhance the performance of the PLL [4][7].

To reduce phase noises, Young proposed a tri-state phase/fre-

quency detector that can detect lead or lag of the phases and

frequencies of two signals, thus lessening the locking time [4].

Kaenel et al. developed a circuit to reduce the dead zone of a

phase/frequency detector [5]. The charge sharing during transis-

tors switching of the charge pump can lead to a large jitter of

the PLL. Some studies have modified the charge-pump circuits

to minimize the jitter [6], [7]. The voltage-controlled oscillator

(VCO) is an integralpart of the PLL forproducing clock signals.

In the on-chip PLL design, the inverter ring with a controllable

delay is popularly used [8][10]. Due to a low supply voltage,

the frequency range controlled by the output from the loop filteris also decreased, thereby limiting the output range of the VCO.

Hence, some researchers enlarged or programmed the driving

capabilities, loading capacitors, or number of inverter stages for

changing the delays to generate output signals of the VCO with

wide-range frequencies [11][14].

An efficient design in the generation and synthesis of clock

signals is essential to generate different clock frequencies. The

PLL with a programmable divider, shown in Fig. 1(a), is most

widely adopted to generate clock signals [2], [5]. Selecting the

division factor of a programmable divider allows the PLL to

generate the required output frequency. When the supply voltage

becomes lower, the frequency range of the VCO is also reduced.

To provide a sufficient output frequency range, designing thePLL with a wider range is more difficult. In addition, a wide

range of the output frequencies versus a small range of the con-

trolled voltage could produce a loop with a wide bandwidth that

is sensitive to noise disturbances. This effect can make the loop

systemunstable, thereby increasing the design cost. Another ap-

proach uses a phase-locked loop and a frequency-synthesizing

unit, as shown in Fig. 1(b) [15]. The phase-locked loop gener-

ates the highest clock frequency that is then synthesized by the

frequency-synthesizing unit to generate different clock signals.

This approach can yield anyclock frequencyfrom themaximum

frequency of the PLL to zero. However, when a low clock fre-

quency is required, power consumption is wasted, as the VCO

needs a large amount of current to generate the maximum clock

frequency.

This work develops an approach that incorporates the

range-programmable voltage-controlled oscillator in a

phase-locked loop to generate wide-range clock frequencies in

a low-power dissipation manner, as shown in Fig. 2. Various

wide-range output frequencies of the PLL can be achieved

by using the range-programmable VCO and programmable

divider. The range-programmable VCO is composed of many

paralleled inverter rings. The output frequency range is deter-

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52 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002

Fig. 1. Conventional clock generators. (a) PLL with programmable divider.(b) PLL with frequency synthesizer.

mined by programming the number of paralleled inverter rings.

To allow the phase-locked loop to shut off inverters, this study

also examines the feasibility of adopting two types of control-

lable inverters that use the output-switch and power-switch

schemes. Our theoretical analyses demonstrate that power

consumption of the VCO depends on the size of the VCO

transistors rather than the operating frequency. In addition to

the range-programmable VCO, the phase/frequency detector

and charge pump are improved as well. By using the TSMC

0.35- m CMOS technology, the proposed phase-locked loop

using the power-switch scheme at a supply voltage of 1.8 V can

generate output signals ranging from 103 MHz to 1.02 GHz.Depending on and proportional to the number of paralleled

inverter rings of the range-programmable VCO, the power con-

sumption of the proposed PLL ranges from 1.32 to 4.59 mW.

Therefore, it can generate wide-range clock frequencies for

various industrial applications in a power-efficient manner.

II. ANALYSES OF POWER CONSUMPTION AND FREQUENCY

RANGES OF VCOS

In the CMOS technology, a ring oscillator structure is fre-

quently used as the basis for the VCO design because it does not

Fig. 2. Proposed wide-range clock generator.

require any inductor. This ring oscillator can be implemented by

an odd number of inverters with voltage-controlled delay ele-

ments each of which includes a voltage-controlled nMOS tran-

sistor and a capacitor as shown in Fig. 3. This nMOS transistor

acts as a voltage-controlled resistor that can adjust the RCtime

constant between two inverter stages. Hence, controlling the de-

lays among inverter stages allows us to generate the required os-

cillation frequency. To understand the VCO, this study analyzes

the operational principle of an inverter. Generally, the CMOS

inverter includes two transistors of the pMOS and nMOS types.

In addition to that the static power dissipation of an inverter is

close to zero, its symmetric architecture is easily implemented

and widely used.

When switching between on and off, the MOS transistor

transfers the operations among saturation, triode, and cutoff

regions. Based on the current equation of the MOS transistor,

the period of an inverter changing from logic-1 to logic-0

can be analyzed in two parts. First, the output voltage ischanged from to , where the nMOS transistor

is at a saturation mode and is the threshold voltage. The

relationship between and time can be described as

(1)

where isthe loading capacitor, and the gainfactor isequal

to . In addition, is the electron mobility and

is the oxide capacitance. and are the width and length

of a transistor, respectively. Hence, this period can be easily

derived as

(2)

The second part is the period of the transistor operating at the

triode region. The relationship between the output voltage and

time can be illustrated as

(3)


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CHEN AND SHEEN: POWER-EFFICIENT WIDE-RANGE PHASE-LOCKED LOOP 53

Fig. 3. Voltage-controlled oscillator.

According to (3), when the output voltage is changed from

to , the period can be derived as

(4)

According to the above equation, the output voltage can be

derived as

(5)

The falling time of the inverters output from to sums

and to become

(6)

In the same manner, the rising time of the inverters output

from logic-0 to logic-1 can be formulated. Usually, is se-

lected to be the same as , thereby making equal to .

Herein, is used to represent or in the following equa-tions.

Major power dissipation in the CMOS circuits can be clas-

sified as dynamic and short-circuit ones. The dynamic power

dissipation originates from the charging and discharging of the

loading capacitor. If the period of signals is , the dynamic

power consumption of an inverter can be represented by

(7)

Fig. 4. Three inverters in a ring structure and their operations. (a)Three-inverter ring. (b) Simulated operations.

where and are the transient currents of nMOS and pMOS

with values of and , respectively.

In the charging and discharging modes, the output voltages are

changed from to , and from to , respectively, where

is the maximum value of the output voltage, and is the

minimum. Equation (7) can be modified to

(8)

The short-circuit power dissipation occurs at the transient

period of nMOS and pMOS transistors being active simulta-

neously. This power consumption, although not related to the

loading capacitor, is related to transistors sizes. It can be inter-

preted by [16]

(9)

Fig. 4 shows three inverters in a ring structure and their sim-

ulated operations. When the output signal of the first inverter

is changed from to 0.5 , the second inverter starts to

be activated for charging. According to (2) and (4), this period

equals plus where is the time of the inverters

output changing from to 0.5 . When the second

inverters output is charged from 0 to 0.5 , the third inverter

begins tobe discharged. Thisperiod isdenoted by . The rising

and falling time of these inverters are adjusted to be the same

such that is equal to . In the same manner, the output of

the third inverter becomes smaller than 0.5 , and the first
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TABLE ICHARACTERISTIC COMPARISON OF THE PROPOSED AND CONVENTIONAL APPROACHES TO DESIGN THE WIDE-RANGE VCOS

respectively. When the rising time is equal to the falling time,

(9) can be modified to

(13)

Hence, theshort-circuit powerconsumption of an inverter is also

proportional to the gain factor and inversely proportional to the

number of inverter stages. The total power consumption of the

VCO can be expressed as

(14)

Power consumption of a ring oscillator depends on , and is

independent of and . Once the transistors sizes of inverter

stages are selected, power dissipation of the ring oscillator is

determined. In other words, the operational frequency does not

affect power consumption of the ring oscillator.

The proposed range-programmable VCO includes many con-

trollable inverter rings in parallel. For a high oscillation fre-

quency, all inverter rings are used to increase the value of ,

whereas for a low oscillation frequency, some inverter rings

are shut off to decrease the value of . Hence, the power con-

sumption of the proposed VCO to generate a low oscillation

frequency can be minimized according to (14). Table I com-

pares the characteristics of the proposed and conventional ap-

proaches to design the wide-range VCOs. The total delay of all

inverter stages, which determines the output frequency of the

VCO, is related to the driving capabilities, equivalent loading

capacitors and number of inverter stages. Therefore, designing

a wide-range output frequency either involves changing or pro-

gramming the driving capabilities, equivalent loading capaci-

tors, and number of inverter stages. Table I reveals that although

directly enlarging the driving capability and loading capacitorof each stage could increase the output frequency range of the

VCO, the gain of the VCO becomes larger. This effect makes

the VCO sensitive to noise, thereby worsening the jitter perfor-

mance. Hence, these two approaches are inadequate in a low-

voltage operation system. To operate at a low supply voltage, the

wide frequency range can be partitioned into many small por-

tions that are individually addressed by the control voltages. In

such an approach, the gain of the VCO can be adequately mini-

mized to stabilize the system. Hence, programming the driving

capabilities, equivalent loading capacitors, and the number of

inverter stages are the preferred approaches. In programming

the number of inverter stages, the larger the number of inverter

stages utilized implies a smaller output frequency. More hard-ware components are necessary to realize more inverter stages

for programmable operations. The approach of programming

the loading capacitors among inverter stages may require a lot

of areas to implement these capacitors. In addition, the power

consumption cannot be minimized when using a small capac-

itor. The proposed approach uses many paralleled inverter rings

that can be viewed as programming driving capabilities of in-

verter stages. In addition, a fairly low hardware complexity is

needed. In particular, the power consumption can be reduced

due to the VCO operating at a low oscillation frequency. There-

fore, the proposed range-programmable VCO can be applied in

a low supply voltage with a power-efficient operation.


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Fig. 6. Proposed phase/frequency detector.

III. PROPOSED PHASE-LOCKED LOOP

The proposed phase-locked loop consists of a phase/fre-

quency detector, charge pump, second-order passive loop

filter, range-programmable voltage-controlled oscillator, and

programmable divider, as shown in Fig. 2. The phase/frequency

detector identifies the phase and frequency differences betweenthe external reference signal and the internal signal from the

programmable divider. When the charge pump and loop filter

are used, these differences are converted into a control voltage

to adjust the output frequency of the voltage-controlled oscil-

lator. Until the frequency and phase of the external reference

signal are the same as those of the internal signal from the

programmable divider, a fixed value of the output signal from

the loop filter is not generated to control the VCO for yielding

a constant output frequency. The detailed functional units of

the proposed PLL are described as follows.

A. Phase/Frequency Detector

In addition to the phase difference, the proposed phase/fre-

quency detector compares the external reference signal and

the signal from the programmable divider to determine their

frequency difference; doing so would reduce the lock-in time.

Owing to the size of the dead zone determining the phase

noise of the PLL, this study also proposes a modified tri-state

phase/frequency detector with the asynchronous race-free

characteristic as shown in Fig. 6. In this design, signal edges are

detected by the flip-flops capable of providing a high-accuracy

detection and performing at a high-frequency operation. The

state switching of the proposed phase/frequency detector

uses a NOR gate to reset the flip flops in order to minimize

the dead zone. In addition, a XNOR and two AND gates areapplied to eliminate two output signals and being logic-1

simultaneously. Hence, the short-circuit effect in the charge

pump can be avoided. Fig. 7 shows the operations of the

proposed and conventional phase/frequency detectors [5]. Two

input signals of and are shown in Fig. 7(a)

where is leading . In the operations of the

conventional phase/frequency detector as shown in Fig. 7(b),

the signals of and may yield the periodical step and pulse

functions, respectively. Of which overlapping periods lead to

a short circuit in the charge pump. In the operations of the

proposed phase/frequency detector as shown in Fig. 7(c), there

is no the pulse in the signal , thus preventing a short circuit

Fig. 7. Operations of the proposed and conventional phase/frequencydetector. (a) Two input signals. (b) Simulated output signals of conventionalphase/frequency detector. (c) Simulated output signals of the proposedphase/frequency detector. (d) Simulated output voltages of the charge pumpusing the proposal and conventional phase/frequency detector.

in the charge pump. Fig. 7(d) shows the simulated output

voltages of the charge pump using the proposed and conven-

tional phase/frequency detectors. This figure indicates some

ripples in the output signal of the charge pump when using the

conventional phase/frequency detector. By using the proposed

phase/frequency detector to eliminate the short-circuit effect,
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Fig. 8. Proposed charge pump.

the charge pump yields the output signal without any ripple,

thereby stabilizing the PLL system relatively easily.

B. Charge Pump

In the proposed charge pump shown in Fig. 8, the transistors

of M1 and M2 are used to discharge and charge the nodes of

and when transistors M3 and M4 are inactive, respectively. In

such a design, the charge sharing is minimized. The transistors

of M3 and M4 addressed by signals of and act as switches,

respectively. Despite the on/off controls of these two transistors,

the charge pump can charge or discharge the capacitor of the

loop filter to convert the phase and frequency differences into

a relevant control voltage. The transistors of M5 and M7 and

of M6 and M8 individually form the current mirrors to pull the

output node up and down quickly, respectively. To minimize the

power consumption, these two current sources are controlled bytransistors of M9 and M10 which are addressed by signals of

and , respectively. Compared to the conventionalcharge pump

that has the switch in source [7], the proposed charge pump

can have the full-swing output of that is applicable in a low-

voltage operation. By setting the and nodes to and

, respectively, the transistors of M3 and M4 can be operated

at the saturation region to eliminate a large instantaneous current

during the transition. Hence, the output voltage of can be

generated more stably.

C. Loop Filter

The loop filter performs like a filter function in terms of elim-inating undesired high-frequency noise signals and providing a

stable control voltage to the VCO. Herein, adequately selecting

the characteristic parameters of two capacitors and a resistor of

the passive second-order loop filter allows us to optimize the

performance of the phase-locked loop and maintain its stability

efficiently [17].

D. Voltage-Controlled Oscillator

The VCO is the most important functional unit in a PLL.

Its output frequency determines the effectiveness of the PLL.

In addition to operating at the highest frequency, this unit con-

sumes the most power in the system. Obviously, this unit is of

Fig. 9. Proposed VCO using paralleled inverter rings.

particular focus to reduce power consumption for the proposed

PLL. Equation (14) clearly reveals that power dissipation of the

VCO becomes constant and does not vary with the output fre-

quencies once the transistors sizes of the inverter stages are

determined. The output frequency of the VCO is that

depends on the transistor sizes and loading capacitances of in-

verter stages according to (10). Hence, the transistor sizes and

loading capacitances of original inverter stages are determined

to have capability of generating the required highest oscillationfrequency. From Fig. 9, this framework breaks down the orig-

inal inverter that can yield the highest oscillation frequency into

several smaller ones and recombines them in parallel to each

other. When all the rings of these small inverters are parallel,

power dissipation is the same as that of the original ring oscil-

lator structure in generating the highest oscillation frequency.

When not requiring a high oscillation frequency, the system can

shut off some of the small inverter rings to reduce the output

frequency generated by the VCO.

In such an approach, each inverter must be designed to be

controllable. The control signals decide on the number

of paralleled inverter rings needed in the voltage-controlled os-

cillator, which subsequently generates only the required clockfrequency as demanded by the system. In addition to not re-

quiring an additional synthesizing unit to generate wide-range

clock frequencies, this design would also shut off some unused

inverters to reduce power consumption. To allow the system to

shut off inverters, two types of controllable inverters are de-

signed as shown in Fig. 10. The first is an inverter design using

the output-switch scheme, as shown in Fig. 10(a). Herein, we

addtwo control transistors addressed by and to a con-

ventional inverter. When islogic-0 and is logic-1,the

inverter is enabled to perform its operation. Conversely, when

is logic-1 and is logic-0, the inverter is disabled and

its output node is floating. However these inverter rings gen-
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TABLE IIMEASURED OUTPUT FREQUENCIES AND POWER CONSUMPTION OF THE CONVENTIONAL VCO, AND THE PROPOSED VCOS USING

THE OUTPUT-SWITCH AND POWER-SWITCH SCHEMES

Fig. 10. Proposed controllable inverters. (a) An inverter using theoutput-switch scheme. (b) An inverter using the power-switch scheme.

erate the highest output frequency, which is smaller than that of

the original inverter ring because their charging and discharging

currents pass through more transistors, subsequently enlarging

theRCtime constant between inverters. In light of this consider-ation, we design another type of a controllable inverter that uses

the power-switch scheme, as shown in Fig. 10(b). The two con-

trol transistors are individually neighboring to and

nodes to reduce their impacts on the inverter during charging

and discharging operations. This design allows the highest os-

cillation frequency of the proposed inverter rings to closely re-

semble that of the original inverter ring.

Programming the number of paralleled inverter rings not only

significantly increases the output frequency range of the VCO,

but also enables the PLL to adjust the output frequency under

different demands. Doing so lowers the power consumption not

only for the system, but also for the functional unit generating

low clock frequencies. In particular, the range-programmable

VCO can overcome small frequency ranges of the PLL at a low

supply voltage as well as decrease the ratio of the frequency

range versus control voltage swing to enhance noise immunity

of the PLL.

E. Programmable DividerTo reduce power dissipation, the programmable divider is

realized by an asynchronous ripple counter using a flip-flop

chain, multiplexors, and demultiplexors. Adequately selecting

the division factor allows us to generate the required output fre-

quency in the range of the predetermined frequency band of the

range-programmable VCO.

IV. MEASUREMENT RESULTS

The characteristics of the VCO are analyzed herein by

designing a conventional VCO and two proposed VCOs using

four output-switch and power-switch inverter rings, individ-

ually. Excluding control transistors of and , the totalactive transistors sizes of four output-switch or power-switch

inverters are the same as that of each inverter used in the

conventional VCO. In addition, the proposed and conventional

VCOs have the same voltage-controlled nMOS transistors and

capacitors that are implemented by small transistor sizes and

capacitances, respectively, for a low hardware cost and thereby

yield a small tuning range of the RCtime constant. Table II lists

the measured output frequencies and power consumption of

these three VCO architectures where denotes the number of

paralleled inverter rings. According to this table, the proposed

range-programmable VCO architectures can expand the output

frequency ranges at a supply voltage of 1.8 V. In line with


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Fig. 11. Output frequencies and power dissipation of three VCOs under different control voltages or numbers of paralleled inverter rings. (a) Conventional VCO.(b) Range-programmable VCO using the output-switch scheme. (c) Range-programmable VCO using the power-switch scheme.

the theoretical derivation, power consumption of the VCO isclosely related to the transistors sizes, and is independent of

the output frequency. The output frequencies of the conven-

tional VCO range from 816 MHz to 1.07 GHz with a power

dissipation of 3.92 mW. Closely examining the two proposed

range-programmable VCOs reveals that the VCO using the

output-switch scheme can generate output frequencies ranging

from 84 to 799 MHz. Moreover, its power dissipation is propor-

tional to the number of the paralleled inverter rings, from 1.09

to 4.77 mW. On the other hand, the inverter rings of the VCO

designed by the power-switch scheme can generate output fre-

quencies ranging from 103 MHz to 1.02 GHz, and has a power

dissipation that is also proportional to the number of paralleled

inverter rings, ranging from 1.07 to 4.19 mW. Therefore, theproposed PLL based on the parallel-structured inverter rings

of the VCO using the power-switch scheme can effectively

achieve the wide-range and low-power performances. Fig. 11

shows the output frequencies and power dissipation of three

VCOs under different control voltages, or number of paralleled

inverter rings. The proposed range-programmable VCO can

effectively extend the output frequency range. The control

transistors are connected to the output node of the inverter

during analysis of the VCO using the output-switch scheme.

The charging and discharging of the output-switch inverter

require passing through the control transistors to yield longer

delays. Hence, the maximum frequency of the VCO using the


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Fig. 12. Die photo of the proposed PLL using the power-switch scheme.

Fig. 13. Jitter performance at an input reference frequency of 33 MHz.

output-switch scheme is lower than that of the conventional

VCO. In the power-switch scheme, the control transistors are

moved to the power supply and ground. The control transistors

are preset to turn on or off so that the and can be

likely connected to the transistors for the inverter operation.

This scheme increases the maximum output frequency as

well as a wide frequency range. Fig. 11 reveals that the VCO,

under different numbers of paralleled inverter rings, can have

overlapping output frequency ranges. Closely examining its

relationship with power dissipation under different numbers

allows us to select a more power-efficient combination togenerate output frequency when it falls on the overlapping

range.

The proposed PLL using the power-switch scheme is im-

plemented by the TSMC 0.35- m 1P4M CMOS technology

where the number of paralleled inverter rings of the range-pro-

grammable VCO is four. At a supply voltage of 1.8 V, the output

frequencies of the PLL range from 103 MHz to 1.02 GHz. Its

power consumption is around 1.32 to 4.59 mW. The die photo

of the proposed PLL with a size of 0.4 mm 0.4 mm is shown

in Fig. 12. Fig. 13 shows a jitter performance at an input ref-

erence frequency of 33 MHz. The peak-to-peak jitter is 110 ps

and the average jitter is 30 ps. Table III lists the specifications of

TABLE IIISPECIFICATIONS OF THE PROPOSED PLL USING THE POWER-SWITCH SCHEME

the proposed PLL. Table IV compares the proposed and conven-

tional approaches with the wide-range output frequencies [11],

[13], [14]. The factors of , , and are the normalized fre-

quency, gain, and power consumption, respectively, when con-

sidering the 0.35- m CMOS technology, a supply voltage of

1.8 V, and an oscillation frequency of 1.02 GHz. These normal-ized factors are derived by

T e c h n o l o g y

(15)

T e c h n o l o g y

(16)

T e c h n o l o g y

Hz(17)

where the threshold voltage of an nMOS transistor made by

the TSMC 0.35- m CMOS technology is around 0.62 V. Com-

pared to the conventional approaches, the proposed PLL using

the range-programmable VCO can have the largest frequency

range, a fairly small gain, and power-efficient operation. Partic-

ularly in generating a low output frequency, the proposed PLL

can effectively scale down its power consumption. Therefore,

the PLL proposed herein can be widely utilized in various dig-

ital systems for power-efficient operations.

V. CONCLUSION

This work has developed a wide-range phase-locked loop

using the range-programmable voltage-controlled oscillator.

The modified phase/frequency detector and charge pump are

designed to minimize the dead zone and charging sharing,

respectively. The controllable inverter rings of the range-pro-

grammable VCO using the output-switch and power-switch

schemes are also explored. Experimental results indicate that

the power-switch scheme yields a larger frequency range. The

relationship that power consumption of the VCO depends on

transistor sizes rather than operating frequencies is theoreti-

cally formulated and illustrated. By using the TSMC 0.35- m

CMOS technology, the designed PLL using the power-switch
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TABLE IVCOMPARISON OF THE PROPOSED AND CONVENTIONAL APPROACHES WITH THE WIDE-RANGE OUTPUT FREQUENCIES

scheme can generate clock frequencies ranging from 103 MHzto 1.02 GHz with a power dissipation ranging from 1.32 to

4.59 mW, at a supply voltage of 1.8 V. Upon each systems

computing requirement, the number of paralleled inverter rings

of the range-programmable VCO can be adjusted to supply

different clock frequencies. When a low clock frequency is

generated, power consumption of our PLL can be reduced due

to shutting off unused inverter rings. Therefore, the proposed

wide-range and power-efficient PLL is highly promising for

applications in multiple clock operations of digital systems for

various task operations.

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Oscal T.-C. Chen (M01) was born in Taiwan,R.O.C., in 1965. He received the B.S. degreein electrical engineering from National TaiwanUniversity in 1987, and the M.S. and Ph.D. degreesin electrical engineering from the University ofSouthern California, Los Angeles, in 1990 and 1994,respectively.

He was with the Computer Processor ArchitectureDepartment of Computer Communication and

Research Labs. (CCL), Industrial TechnologyResearch Institute (ITRI), as a System DesignEngineer, Project Leader, and Section Chief from 1994 to 1995. He contributedsignificantly to many industrial applications including the fuzzy chip, neuralnetworks, speech recognition system, and digital signal processor. He has beenan Associate Professor in the Department of Electrical Engineering, NationalChung Cheng University (NCCU), Taiwan, since September 1995. Currently,he is also a Director, Industrial Cooperation, The Office of Development andInternational Cooperation, NCCU. He has served as a Technical Consultantin the Institute for Information Industry, Center for Aviation and Space Tech-nology, and CCL, ITRI. He was a Co-Chair of Southern TelecommunicationCenter, NSC, Taiwan, from June 1996 to July 1999. His research interestsinclude analog/digital circuit design, video/audio processing, DSP processors,VLSI systems, RF IC, microsensors and communication systems.

Dr. Chen was the co-recipient of the Best Paper Award of the IEEETRANSACTIONS ON VLSI SYSTEMS in 1995. He was an Executive Secretary ofVLSI/CAD program, National Science Council (NSC), Taiwan, from 1994 to

1996. He was an Associate Editor ofIEEE Circuits and Devices Magazine fromJuly 1995 to March 1999, and a founding member of the multimedia systemsand applications technical committee of IEEE Circuits and Systems Society.He participates in the Technical Program Committee of the IEEE InternationalConference on Multimedia and Expo 20002001. He was the TechnicalProgram Committee and Session Chair of the IEEE Asia Pacific Conferenceon Circuits and Systems in 1998, the IEEE International Conference on NeuralNetworks in 1996, and the IEEE International Conference on Computer Designin the Architectures and Algorithm Track in 1994 and 1995. He is a LifeMember of the Chinese Fuzzy Systems Association.

Robin Ruey-Bin Sheen received the B.S. and M.S.degrees in electrical engineering from NationalChung Cheng University (CCU), Taiwan, R.O.C., in1996 and 1998, respectively. He is currently workingtoward the Ph.D. degree in electrical engineering atCCU.

His research interests include the design of CMOSmixed-signal integrated circuits for low-power andhigh-speed data computationand broadband commu-

nications.

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