Post-Silicon Debugging of Transactional Memory Tests

WTM’13, Prague, April 14, 20131

Post-Silicon Debugging of Transactional Memory Tests

Carla Ferreira, João Lourenço

{carla.ferreira, joao.lourenco}@fct.unl.pt

Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin

{ophirf, wisamk, nahir, vitali}@il.ibm.com

IBM Research Universidade Nova de Lisboa


Post Silicon

Post-silicon validation elements:

1. Stimulating the design under test

2. Detecting erroneous behavior

3. Localizing the root cause of the problem

4. Providing a fix.


Stimulation

1. Test generation

2. Execution

3. Consistency checking

4. Repeat… Forever! Silicon

Accelerator

Generation

Checking

Execution

OS services

Test Template

Topology

ArchitecturalModel

Exerciser Image (Threadmill)


DetectionConsistency checking

• Run the same test-case from the same initial architectural state.

• Expect the same final architectural state

ori r10,r0,170stb r10,0(r6)lbz r11,0(r6)...

Initial StateR0 = 0x1, R1 = 0x2 … Final State

R0 = 0xA, R1 = 0xB …

Micro-architectural state varies!Caches, page misses, pre-fetching, thread priorities


DetectionAnd what if two different final states are manifested?



R0 = 0xA, R1 = 0xB …



R0 = 0xC, R1 = 0xB …

MIS-COMPARE

Final StateR0 = 0xA, R1 = 0xB …

Final StateR0 = 0xC, R1 = 0xB …


Localization approach1. A test-case that produces a mis-compare is found

2. Fast-forward to that test-case on a software simulator (a.k.a. Reference model)

3. Execute test case on the reference model instruction by instruction and extract information


Localization

Reduce number of resources and instructions that might be the root cause of the mis-compare

Study the effect of transactions in the test-case on the final state.

Justification: Force erroneous behaviour on reference model and re-

create the mis-compare results

8

R1 R4R3R2

Localization1 4 1 2:I R R R

2 :I tbegin

3 1 3:I R R

4 4 1 2:I R R R

5 2 1:I R R

6 :I tend

7 3 1 2:I R R R

= suspicious instruction subset


Concluding remarks

Debug automation effectively reduces the debugging effort.

Graph analysis holds the potential automate the localization of suspicious resources and instructions

Future work:- Study the impact of escaped stores in transaction aborts- experiment with larger (real-world) cases


Questions

Post-Silicon Debugging of Transactional Memory Tests

Documents

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