PLL Building Blocks Part 2 - TI Training

19
PLL Building Blocks Part 2 TI Precision Labs – Clocks and Timing Presented by Dean Banerjee Prepared by Liam Keese 1

Transcript of PLL Building Blocks Part 2 - TI Training

Page 1: PLL Building Blocks Part 2 - TI Training

PLL Building Blocks Part 2 TI Precision Labs – Clocks and Timing

Presented by Dean Banerjee

Prepared by Liam Keese

1

Page 2: PLL Building Blocks Part 2 - TI Training

R Divider

1/D

Output DividerReference

Oscillator

1/N

1/R

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

KPD Z(s)fOUT

Phase lock loop (PLL) overview

2

fOSC fPD

fN fVCO

Page 3: PLL Building Blocks Part 2 - TI Training

Input sources

3

R Divider

1/D

Output DividerReference

Oscillator

1/N

1/R

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

KPD Z(s)

fOSC

• Crystal oscillator (XO)

• Temperature compensated crystal oscillator (TCXO),

• Oven controlled crystal oscillator (OCXO),

• Clock output from another device

Page 4: PLL Building Blocks Part 2 - TI Training

R

Q

Q

RQ

Q1

fN

fR

1UP

DOWN

tRESET

+Vcc

OUTPUT

Source

Current

Sink

Current

Phase frequency detector/charge pump

4

R DividerReference Oscillator

1/N

1/R

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

KPD Z(s)

Page 5: PLL Building Blocks Part 2 - TI Training

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• High Impedance (tri-state) if output frequency/phase is correct (within tolerances)

• Sources Current if output frequency/phase is too low

• Sinks Current if output frequency/phase is too high

Phase Frequency Detector/Charge Pump Phase detector/charge pump operation

Page 6: PLL Building Blocks Part 2 - TI Training

Loop filter

• The loop filter is a low pass filter

– Has a dramatic effect on performance

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R Divider

1/D

Output DividerReference

Oscillator

1/N

1/R

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

KPD Z(s)

Page 7: PLL Building Blocks Part 2 - TI Training

Brief overview of loop dynamics

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R Divider

1/D

Output DividerReference

Oscillator

1/N

1/R

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

KPD Z(s)

Kvco/s

Page 8: PLL Building Blocks Part 2 - TI Training

Choosing loop bandwidth

• Choose optimal jitter loop bandwidth to be BWJIT to minimize area under the

curve

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Page 9: PLL Building Blocks Part 2 - TI Training

Choosing loop bandwidth

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Design Goal Bandwidth

Minimize Jitter BW = BWJIT

Minimize Phase Noise at

offset < BWJIT

BW > BWJIT

Minimize Phase Noise at

offset > BWJIT

BW < BWJIT

Minimize Lock Time BW > BWJIT

Minimize Spurs BW < BWJIT

Page 10: PLL Building Blocks Part 2 - TI Training

To find more technical resources and search products, visit ti.com/clocks

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Page 11: PLL Building Blocks Part 2 - TI Training

Short Quiz

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1. True or False:

The reference input frequency is provided by VCO.

Page 12: PLL Building Blocks Part 2 - TI Training

Short Quiz

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1. True or False:

The reference input frequency is typically fixed frequency and provided by a stable reference

source such as crystal oscillator.

Page 13: PLL Building Blocks Part 2 - TI Training

Short Quiz

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2. Choose one:

The phase detector will

(a) Sink and source current to the loop filter

(b) Sample the phase error between the R and N counter

(c) Provide the output frequency

Page 14: PLL Building Blocks Part 2 - TI Training

Short Quiz

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2. Choose one:

The phase detector will

(a) Sink and source current to the loop filter

(b) Sample the phase error between the R and N counter

(c) Provide the output frequency

Page 15: PLL Building Blocks Part 2 - TI Training

Short Quiz

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3. True or False:

Choose loop bandwidth to be the point where VCO noise is equal to PLL noise to minimize jitter.

Page 16: PLL Building Blocks Part 2 - TI Training

Short Quiz

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3. True or False:

Choose loop bandwidth to be the point where VCO noise is equal to PLL noise to minimize jitter.

Page 17: PLL Building Blocks Part 2 - TI Training

Short Quiz

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4. Choose all that apply:

When choosing a loop bandwidth, which of these tradeoff are correct?

a) To reduce lock time, increase the loop bandwidth

b) To reduce spurious noise, increase the loop bandwidth

c) To reduce phase noise at larger frequency offsets, reduce the loop bandwidth

Page 18: PLL Building Blocks Part 2 - TI Training

Short Quiz

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4. Choose all that apply:

When choosing a loop bandwidth, which of these tradeoff are correct?

a) To reduce lock time, increase the loop bandwidth

b) To reduce spurious noise, increase the loop bandwidth

c) To reduce phase noise at larger frequency offsets, reduce the loop bandwidth

Page 19: PLL Building Blocks Part 2 - TI Training

TI Information – Selective Disclosure


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