PIXIE-4 ManualsPixie_Set_Current_ModChan. This will give API programmers more flexibility when using...

Digital Gamma Finder (DGF)

PIXIE-4 Manuals Version 1.22, December 2004

X-Ray Instrumentation Associates 8450 Central Ave

Newark, CA 94560 USA

Phone: (510) 494-9020; Fax: (510) 494-9040 http://www.xia.com

Release Notes for PIXIE-4 Viewer Copyright (c) 2004 X-Ray Instrumentation Associates All Rights Reserved =============================================== Product Release: December 3 2004 - Igor Viewer Version: 1.22 - Igor XOP Version: 1.22 - Igor XOP Build Number: 1 - DSP Code Version: 3.20 - DSP Code Build Number: 1 =============================================== Thank you for using our products. This file contains important information about this PIXIE-4 release. We strongly recommend that you read the entire document. We also welcome your comments and suggestions. ************* Installation Guide ************** If you received this software on a CD from XIA: 1. Put the CD into the CD-ROM, and run the program Setup.exe on the CD if it doesn’t start automatically. Follow the instructions shown on the screen. 2. If you are using the PIXIE-4 for the first time, please read the User’s Manual. 3. Start to the use the PIXIE-4 Viewer by double clicking the IGOR file PIXIE4.pxp. If you received this software as an upgrade via email: 1. Unzip the file PIXIE4.zip into a folder (e.g., C:\XIA\PIXIE4). 2. Run the program Setup.exe in the unzipped folder. Follow the instructions shown on the screen. 3. Print out the User’s Manual, Programmer’s Manual, What’s New and Help File located in the Doc subfolder. If you are using the PIXIE-4 for the first time, please also read the User’s Manual. 4. Start to the use the PIXIE-4 Viewer by double clicking the IGOR file PIXIE4.pxp. ************* Configuration Guide ************** 1. After installing the Pixie-4 software, shut down the computer and insert the Pixie-4 modules into the PXI/CompactPCI chassis, then reboot the computer. 2. Check Windows operating system’s Device Manager to see if the Pixie-4 modules have been successfully installed. Pixie-4 modules are normally reported as Custom (OEM) PCI 9054 Board under the Other Devices category. If the Device Manager reports problems such as missing driver for the PCI 9054 board, please reinstall the driver by pointing to the INF file (PciSdk.inf) located in the Drivers folder of the Pixie-4 software distribution. 3. Reboot the computer and recheck if the Device Manager reports Custom

(OEM) PCI 9054 Board has been installed successfully. ************* IMPORTANT NOTES ***************** 1. When choosing the destination folder to install the Pixie-4 software, please make sure the combined length of file and path names is less than 80 characters. For instance, a good choice for the installation folder would be <DRV_Letter>:\XIA\Pixie4\. 2. If the installation program Setup.exe could not install the Pixie-4 software properly, please contact XIA for technical assistance. 3. This Pixie-4 software release supports the installation of one or multiple Pixie-4 modules in a 4, 8 or 18 slot PXI/CompactPCI chassis and it has been successfully tested using National Instruments' line of chassis and controllers. If a different brand of chassis or controller is used, please contact XIA if there is any installation problem. 4. The supported operating systems include Windows 2000/98/Me/XP. **************** DISCLAIMER ******************* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

What’s New in PIXIE-4 Viewer Revision 1.22 (Released on 12/03/2004)

What's New in the Software

1. Speeded up the system booting.

2. Made storing of list mode .dat file optional on the Data Record Option Panel. Since the .dat is saved as a text file so its size could be much bigger than the .bin file.

3. The software now supports 18-slot PXI chassis. A user can select 4/8 slot chassis or 18-slot chassis on the Pixie-4 Start Up Panel. NOTE: for 18-slot chassis, the first module (module #0) must be in the first bus segment, i.e. slots 2 - 6.

4. Resolved a few compatibility issues related to different IGOR PRO versions, mainly IGOR PRO ver. 4 and ver. 5.


Hardware Software revision 3.2.0 also supports the new Pixie-4 hardware revision C. Revision C modules are compatible with Revision B modules, but have the following new features:

1. The module can be PXI clock master if residing in slot 2.

2. The module can disconnect from backplane trigger lines, which allows several trigger groups in one chassis.

3. The module can store list data of several runs in the external memory, which can be read out in a fast burst transfer, reducing read-out dead time.

4. The module has additional connections for optional trigger distribution via front panel or backplane (currently not implemented).

5. The module has a front panel LED to indicate host I/O. Revision B and Revision C modules use different configuration files, which are automatically selected by the software. Note that if both revisions are used together in the same chassis, item 3 is not possible.

PIXIE-4 Viewer - IGOR Interface 1. Added a new “Backplane Option” to the Module Register Edit Panel. If set, connect

module trigger lines to backplane. Triggers will be shared with other modules. If not set, triggers are distributed only between channels of this module, depending on channel settings.

2. Added a new “Read 32 list data buffers per spill” option to the Data Record Option Panel. This feature is only available in Revision C Pixie-4 modules. Previously (Revision B modules), the host needs to read out the DSP’s internal 8192-word buffer before it can resume the next run. Now, the host can choose to store 32 consecutive 8192-word buffers in DSP’s external memory before it reads out the whole external memory. This will also improve the data transfer speed since the host can directly access the DSP external memory using fast burst transfer.

PIXIE-4 API (C Driver) Updated driver to accommodate the new hardware features in Revision C modules.

Firmware Updated communication FPGA configurations for Revision C modules.

Manuals 1. User’s Manual

i. Added descriptions for Revision C clock distribution mode. ii. Added screenshots of Pixie-4 Viewer.

iii. Added Pixie-4 functional block diagram.

2. Programmer’s Manual i. Updated the manual to accommodate the new hardware features in Revision C

modules. ii. Updated description of MODCSRA.


PIXIE-4 Viewer - IGOR Interface 1. Improved “Offline Analysis” functionality. Without using a Pixie-4 module, a user

can still excise the features of the Pixie-4 Viewer, or display previously acquired MCA spectra or list mode data.

2. Added a new functionality for the automatic update of MCA spectra every 5 seconds. It can be enabled by clicking on the option “Update MCA every 5 seconds or spills” on the “Data Record Option Panel” (accessible through “Run” tab -> “Record” button).

3. Added a new “Update” button on the MCA Spectrum panel. A user can click on it to update the MCA spectrum while a MCA or list mode run is in progress.

4. Expanded the functionality of the “Sum” button on the MCA Spectrum panel. Now a user has three options for summing a MCA spectrum: (1) Sum-Background between limits; (2) Sum between limits; (3) Sum complete MCA.

5. Expanded the functionality of the file I/O on the MCA Spectrum panel. Now a user has three options for importing or exporting a MCA spectrum: (1) Save MCA to an Igor text file; (2) Read MCA from an Igor text file; (3) Extract MCA from a MCA binary file.

6. Added a “More/Less” button to the Pixie4 Run Control Panel (next to the “Help” button on the bottom of the Control Panel). It can be used to hide some controls. This may be helpful to those first-time Pixie users who only need to use those major controls in the beginning.

PIXIE-4 API (C Driver) This new version of Pixie-4 API is a major overhaul compared to the previous releases in the following aspects:

1. Streamlined the error message relay from the bottom layer of the API to the host computer. The host computer program should check the return value of each of the API functions, and any negative return value indicates an error in the API. Error message information and error handling methods can be found in the Programmer’s Manual.

2. Improved the user parameter I/O function Pixie_User_Par_IO. Now a user parameter is classified as either a “SYSTEM” parameter, or a “MODULE” parameter, or a “CHANNEL” parameter. Please see the Programmer’s Manual for the detailed description of these types of parameters.

3. Module Number and/or Channel Number are now part of the input parameters for functions Pixie_User_Par_IO, Pixie_Acquire_Data and

Pixie_Set_Current_ModChan. This will give API programmers more flexibility when using these functions.

Firmware No change.

Manuals 1. User’s Manual

i. Added the jumper settings for different clock distribution modes; ii. Added descriptions for those new controls added to the Igor interface.

2. Programmer’s Manual

i. Rewrote Section 2 where each API function is described; ii. Updated the descriptions of DSP variables in Section 4.

User's Manual Digital Gamma Finder (DGF)

PIXIE-4

Version 1.20, August 2004




Disclaimer Information furnished by XIA is believed to be accurate and reliable. However, XIA assumes no responsibility for its use, or for any infringement of patents, or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under the patent rights of XIA. XIA reserves the right to change the DGF product, its documentation, and the supporting software without prior notice.

PIXIE-4 User’s Manual V1.20 XIA 2004. All rights reserved.

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Table of Contents Table of Contents...................................................................................................................... ii 1 Overview................................................................................................................1

1.1 Features ................................................................................................................. 1 1.2 Specifications........................................................................................................ 2

2 Setting up ...............................................................................................................4 2.1 Scope of document................................................................................................ 4 2.2 Installation............................................................................................................. 4 2.3 Getting Started ...................................................................................................... 4

3 Navigating the Pixie Viewer..................................................................................8 3.1 Overview............................................................................................................... 8 3.2 Settings.................................................................................................................. 8 3.3 Calibrate................................................................................................................ 9 3.4 Run...................................................................................................................... 10 3.5 Analyze ............................................................................................................... 10 3.6 Optimizing Parameters........................................................................................ 11

3.6.1 Noise ................................................................................................................... 11 3.6.2 Energy Filter Parameters..................................................................................... 11 3.6.3 Threshold and Trigger Filter Parameters ............................................................ 12 3.6.4 Decay time .......................................................................................................... 12

4 Data Runs and Data Structures ............................................................................14 4.1 Run types ............................................................................................................ 14

4.1.1 MCA Runs .......................................................................................................... 14 4.1.2 List Mode Runs................................................................................................... 14 4.1.3 Fast List Mode Runs ........................................................................................... 15

4.2 Output data structures ......................................................................................... 16 4.2.1 MCA histogram data........................................................................................... 16 4.2.2 List mode data..................................................................................................... 16

5 Hardware Description ..........................................................................................19 5.1 Analog signal conditioning ................................................................................. 19 5.2 Real-time processing units.................................................................................. 20 5.3 Digital signal processor (DSP)............................................................................ 21 5.4 PCI interface ....................................................................................................... 21

6 Theory of Operation.............................................................................................23 6.1 Digital Filters for γ-ray detectors ........................................................................ 23 6.2 Trapezoidal Filtering in the Pixie-4 .................................................................... 25 6.3 Baselines and preamplifier decay times.............................................................. 26 6.4 Thresholds and Pile-up Inspection...................................................................... 28 6.5 Filter range .......................................................................................................... 30

7 Operating multiple Pixie-4 modules synchronously............................................31 7.1 Clock distribution................................................................................................ 31

7.1.1 Individual Clock mode........................................................................................ 32 7.1.2 Daisy-chained Clock Mode................................................................................. 32 7.1.3 Bussed Clock Mode ............................................................................................ 32


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7.1.4 PXI Clock Mode ................................................................................................. 33 7.2 Trigger distribution ............................................................................................. 33 7.3 Run Synchronization........................................................................................... 34 7.4 External gate — GFLT (Veto)............................................................................ 34

8 Troubleshooting ...................................................................................................36 8.1 Startup Problems................................................................................................. 36

9 Appendix A..........................................................................................................37 9.1 Jumpers ............................................................................................................... 37 9.2 PXI backplane pin functions............................................................................... 38 9.3 Control and Status Register Bits ......................................................................... 39


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1 Overview The Digital Gamma Finder (DGF) family of digital pulse processors features unique capabilities for measuring both the amplitude and shape of pulses in nuclear spectroscopy applications. The DGF architecture was originally developed for use with arrays of multi-segmented HPGe gamma-ray detectors, but has since been applied to an ever broadening range of applications. The DGF Pixie-4 is a 4-channel all-digital waveform acquisition and spectrometer card based on the CompactPCI/PXI standard for fast data readout to the host. It combines spectroscopy with waveform digitizing and on-line pulse shape analysis. The Pixie-4 accepts signals from virtually any radiation detector. Incoming signals are digitized by 14-bit 75 MSPS ADCs. Waveforms of up to 13 µs in length for each event can be stored in a FIFO. The waveforms are available for onboard pulse shape analysis, which can be customized by adding user functions to the core processing software. Waveforms, timestamps, and the results of the pulse shape analysis can be read out by the host system for further off-line processing. Pulse heights are calculated to 16-bit precision and can be binned into spectra with up to 32K channels. The Pixie-4 supports coincidence spectroscopy and can recognize complex hit patterns. Data readout rates through the CompactPCI/PXI backplane to the host computer can be over 100Mbytes/s. The PXI backplane is also used to distribute clocks and trigger signals between several Pixie-4 modules for group operation. With a large variety of CompactPCI/PXI processor, controller or I/O modules being commercially available, complete data acquisition and processing systems can be built in a small form factor.

1.1 Features

• Designed for high precision γ-ray spectroscopy with HPGe detectors. • Directly compatible with scintillator/PMT combinations: NaI, CsI, BGO, and many

others. • Simultaneous amplitude measurement and pulse shape analysis for each channel. • Input signal decay time: as fast as 150ns and up to 10ms, exponentially decaying. • Wide range of filter rise times: from 27ns to 109µs, equivalent to 12ns to 50µs

shaping times. • Programmable gain and input offset. • Excellent pileup inspection: double pulse resolution of 50 ns. Programmable pileup

inspection criteria include trigger filter parameters, threshold, and rejection criteria. • Digital oscilloscope and FFT for health-of-system analysis. • Triggered synchronous waveform acquisition across channels, modules and crates. • Dead times as low as 1 µs per event are achievable (limited by DSP algorithm

complexity). Events at even shorter time intervals can be extracted via off-line ADC waveform analysis.


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• Digital constant fraction algorithm measures event arrival times down to a few ns accuracy.

• Programmable token ring and nearest neighbor logic through PXI backplane. • Supports 32-bit 33 MHz PCI data transfers (>100 Mbytes/second).

1.2 Specifications

Inputs (Analog) Signal Input 4 inputs. Selectable input impedance: 50Ω, and 10kΩ, ±5V pulsed,

±2V DC. Selectable input attenuation 1:7.5 and 1:1.

Inputs (Digital) Clock Input/Output

Distributed 37.5 MHz clock on PXI backplane.

Triggers Two wired-or trigger buses on PXI backplane. One for synchronous waveform acquisition, one for event triggers.

Next-neighbor logic One pair of next-neighbor signals to each neighbor for distributed next-neighbor logic, on PXI backplane. Designated Token Ring lines for multiplicity information.

Synch Wired-or SYNC signal distributed through PXI backplane to synchronize timers and run start/stop to 50ns.

Veto VETO signal distributed through PXI backplane to suppress event triggering.

Front Panel General Purpose I/O connected to programmable logic (Rev. C only). Function to be determined.

Outputs (Digital) Front Panel General Purpose output from Digital Signal Processor. Function to

be determined.

Interface PCI 32-bit, 33MHz Read/Write, memory readout rate to host

over 100 Mbytes/s.

Digital Controls Gain Analog switched gain from 1.93 to 22.5 in max. 10% steps.

Digital gain adjustment of up to ±10% in 15ppm steps. Offset DC offset adjustment from –2.5V to +2.5V, in 65535 steps. Shaping Digital trapezoidal filter. Rise time and flat top set independently:

27ns – 109µs in small steps. Trigger Digital trapezoidal trigger filter with adjustable threshold. Rise time

and flat top set independently from 26 to 413ns.


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Data Outputs Spectrum 1024-32768 channels, 32 bit deep (4.2 billion counts/bin).

Additional memory for sum spectrum for clover detectors. Statistics Real time, live time, input and throughput counts. Event data Pulse height (energy), timestamps, pulse shape analysis results,

waveform data and ancillary data like hit patterns.


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2 Setting up

2.1 Scope of document The scope of this document is Pixie-4 modules with serial numbers 105 through 129 (Revision B) and serial numbers 130 through 154 (Revision C).

2.2 Installation The Pixie-4 modules can be operated in any standard 3U CompactPCI or PXI chassis. Chassis following only the CompactPCI standard can be used to operate modules individually. To operate several modules together, a backplane following the PXI standard has to be present. Put the host computer (or remote PCI controller) in the system slot of your chassis. Connect your host computer to monitor, mouse and keyboard. Place the Pixie-4 modules into any free slots with the chassis still powered down, then power up the chassis (Pixie-4 modules are not hot swappable). If using a remote controller, be sure to boot the host computer after powering up the chassis. The Pixie Viewer, XIA’s graphical user interface to set up and run the Pixie-4 modules, is based on WaveMetrics’ IGOR Pro. To run the Pixie Viewer, you have to have IGOR Version 4.0 or higher installed on your computer. By default, the IGOR Pro should be installed at C:\Program Files\WaveMetrics\IGOR Pro Folder. The CD-ROM with the Pixie-4 software distribution contains

1) an installation program Setup.exe, 2) the Pixie-4 software in the folder XIA\Pixie4 and its subfolders.

The Pixie-4 software can be installed by running its installation program. Follow the instructions shown on the screen to install the software to the default folder selected by the installation program, or to a custom folder. This folder will contain the IGOR control program (Pixie4.pxp), online help files and 5 subfolders including Configuration, DSP, Firmware, MCA, and PulseShape. Make sure you keep this folder organization intact, as the IGOR program and future updates rely on this. Feel free, however, to add folders and subfolders at your convenience.

2.3 Getting Started To start the Pixie Viewer, double-click on the file Pixie4.pxp in the installation folder. After IGOR loaded the Pixie Viewer, the Start Up panel should be prominently displayed in the middle of the desktop.


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Figure 2.1: The Pixie-4 Start Up Panel.

In the panel, first select the number of Pixie-4 modules in the system. Then specify the slot number in which each module resides. Click on the “Start Up System” button to initialize the modules. This will download DSP code and FPGA configuration to the modules, as well as the module parameters. If you see messages similar to “Module 0 in slot 5 started up successfully!” in the IGOR history window, the Pixie-4 modules have been initialized successfully. Otherwise, refer to the troubleshooting section for possible solutions. If you want to try the software without a chassis or modules attached, click on the “Offline Analysis” button. After the system is initialized successfully, you will see the main Pixie Control Panel from which all work is conducted. The tabs in the Control Panel are arranged in logical order from left to right. For most of the actions the Pixie Viewer interacts with one Pixie module at a time. The number of that module is displayed at the top right corner of the Control Panel (inside the "Module" control). Next to the “Module” control is the “Channel” control which indicates the current channel the Pixie Viewer is interacting with. Proceed with the steps below to configure your system. Note: The “More/Less” button next to the “Help” button on the bottom of the Pixie Control Panel can be used to hide some controls. This may be helpful to those first-time Pixie users who only need to use those major controls in the beginning.


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Figure 2.2: The Pixie-4 Run Control Panel.

1. In the Calibrate tab, click on the Oscilloscope button. This opens a graph that shows the untriggered signal input. Click "Refresh" to update the display. The pulses should fall in the display range. If no pulses are visible or if they are cut off out of the display range, click "Adjust Offsets" to automatically set the DC offset. There is a control called “Baseline [%]” on the Oscilloscope which can be used to set the DC-offset level for each channel. If the pulse amplitude is too large to fall in the display range, decrease the "Gain" in the Calibrate tab of the Pixie Control Panel. If the pulses are negative, toggle the “Trigger positive” checkbox in the Channel CSRA Edit Panel which can be accessed by clicking on the Edit button next to “Channel” on the Settings tab.

2. In the Calibrate tab, input an estimated preamplifier exponential RC decay time for

Tau, and then click on "Auto Find" to determine the actual Tau value for the current channel of the current module. Repeat this for other channels if necessary. You can also enter a known good Tau value directly in the control.

3. Save the modified parameter settings to file. To do so, click on the “Save” button on

the Settings tab to open a save file dialog. Create a new file name to avoid overwriting the default settings file.

4. Click on the Run tab, set "Run Type" to 0x301 MCA Mode, “Polling time” to 1

second, and “Run time/time out” to 30 seconds or so, then click on the "Start Run" button. A spinning wheel will appear occasionally in the lower left corner of the screen as long as the system is waiting for the run to finish. After the run is complete, select the Analyze tab and click on the “MCA Spectrum” button. The MCA spectrum shows the MCA histograms for all four channels. You can deselect other channels while working on only one channel. You can do a Gauss fit on a peak by entering values in the "Min" and "Max" fields as the limits for a Gauss fit. You can also use the mouse to drag the Cursor A and B in the MCA spectrum to the limits of the fit.


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Click "Fit" to select one or all channels and to perform the fit. Enter the true energy value in the "Peak" field to calibrate the energy scale.

At this stage, you may not be able to get a spectrum with good energy resolutions. You may need to adjust some settings such as energy filter rise time and flat top etc. as described in section 3.6.


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3 Navigating the Pixie Viewer

3.1 Overview The Pixie Viewer consists of a number of graphs and control panels, linked together by the main “Pixie Run Control” panel. The “Pixie Run Control” panel is divided into 4 tabs, corresponding to the 4 topics summarized below. The Settings tab contains controls used to initialize the module, and the file and directory settings. The Calibrate tab contains controls to adjust parameters such as gain, DC-offset, preamplifier decay time, histogram control. The Run tab is used to start and stop runs, and in the Analyze tab are controls to analyze, save and read spectra or event traces. At the bottom of the panel is a “More” button, which will make all advanced panel controls visible as well. For initial setup and normal operation, these controls are not important. Below we describe the concepts and principles of using the Pixie Viewer. Detailed information on the individual controls can be found in the Online Help for each panel.

3.2 Settings The Pixie Viewer comes up in exactly the same state as it was when last saved to a file using File->Save Experiment. However, the Pixie module itself loses all programming when it is switched off. When the Pixie is switched on again, all programmable components need code and configuration files to be downloaded to the module. Clicking on the Start System button in the main “Pixie Run Control” panel performs this download.

Figure 3.1: The Settings tab of the Pixie-4 Run Control Panel.

The Pixie-4 being a digital system, all parameter settings are stored in a settings file. This file is separate from the main IGOR experiment file, to allow saving and restoring different settings for different detectors and applications. Parameter files are saved and loaded with the


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corresponding buttons in the Settings tab. After loading a settings file, the settings are automatically downloaded to the module. At module initialization, the settings are automatically read and applied to the Pixie module from the current settings file. Internally, the module parameters are handled as binary numbers and bitmasks. The Settings tab gives access to user parameters in meaningful physical units. Values entered by the user are converted by the Pixie Viewer to the closest value in internal units. Refer to the Online Help for detailed descriptions of the parameters.

3.3 Calibrate The Calibrate tab is used to calibrate or diagnose the system. You can adjust the Gain and DC-Offset on the channel by channel basis. You can use the automatic Tau-Finder routine to find the "Decay Time" of the preamplifier. You can also control the histogram by setting the cut-off energy and binning factor.

Figure 3.2: The Calibrate tab of the Pixie-4 Run Control Panel.

The Calibrate tab also has an Oscilloscope button linking to a diagnostic graph. The Oscilloscope shows a graph of ADC samples which are untriggered pulses from the signal input. The time intervals between the samples can be adjusted; for intervals greater than 0.147µs the samples will be averaged over the interval. The main purpose of the Oscilloscope is to make sure that the signal is in range in terms of gain and DC-offset. The Oscilloscope is also useful to estimate the noise in the system. Clicking on the FFT Display button opens the “ADC Trace FFT”, where the noise spectrum can be investigated as a function of frequency. This works best if the Oscilloscope trace contains no pulses, i.e. with the detector attached but no radioactive sources present.


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3.4 Run The Run tab is used to start and stop runs. There are two major run types: List mode runs and MCA runs. MCA runs only collect spectra, List mode runs acquire data on an event-by event basis. List mode runs come in several variants. Before you start a run, you need to select the run type, polling time (the time interval for polling the run status), run time for MCA runs and time out limit and the number of spills (repeated runs) for list mode runs.

Figure 3.3: The Run tab of the Pixie-4 Run Control Panel.

In a multi-module system, you can set all modules to start and stop simultaneously and to reset the timers in all modules with the start of the next data acquisition run by selecting the two options in the Synchronization group. You can choose a base name and a run number in order to form an output file name. The run data will be written to a file whose name is composed of both. The run number is automatically incremented at the end of each run if you select “Auto update run number” on the Record panel, but you can set it manually as well. Data are stored in files in either the MCA folder if the run is a MCA run or the PulseShape folder if the run is a List mode run. These files have the same name as the output file name but different extension. For list mode runs, buffer data are stored in a file with name extension ".bin". For both list mode runs and MCA runs, MCA spectrum data are stored in a file with name extension “.mca” if you select “Auto store spectrum data” on the Record panel. Module settings are stored in a file with name extension “.set” after each run if you select “Auto store settings” on the Record panel.

3.5 Analyze The Analyze tab is used to investigate the spectrum or to view list mode traces. It also shows the run statistics such as run time, event rate and live time and input count rate for each channel. You can perform Gauss fits on peaks to find the resolution, and calibrate the energy


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spectrum by entering a known energy value for a fitted peak. You can also view individual event trace and its energy from a standard list mode run.

Figure 3.4: The Analyze tab of the Pixie-4 Run Control Panel.

3.6 Optimizing Parameters Optimization of the Pixie-4’s run parameters for best resolution depends on the individual systems and usually requires some degree of experimentation. The Pixie Viewer includes several diagnostic tools and settings options to assist the user, as described below.

3.6.1 Noise For a quick analysis of the electronic noise in the system, you can view a Fourier transform of the incoming signal by selecting Oscilloscope FFT Display in the Calibrate tab. The graph shows the FFT of the untriggered input sigal of the Oscilloscope. By adjusting the “dT” control in the Oscilloscope and clicking the Refresh button, you can investigate different frequency ranges. For best results, remove any source from the detector and only regard traces without actual events. If you find sharp lines in the 10 kHz to 1 MHz region you may need to find the cause for this and remove it. If you click on the “Apply Filter” button, you can see the effect of the energy filter simulated on the noise spectrum.

3.6.2 Energy Filter Parameters The main parameter to optimize energy resolution is the rise time of the energy filter. Generally, longer rise times result in better resolution, but reduce the throughput. Optimization should begin with scanning the rise time through the available range. Try 2µs, 4µs, 8µs, 11.2µs, take a run of 60s or so and note changes in energy resolution. Then fine tune the rise time.


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The flat top usually needs only small adjustments. For a typical coaxial Ge-detector we suggest to use a flat top of 1.2µs. For a small detector (20% efficiency) a flat top of 0.8µs is a good choice. For larger detectors flat tops of 1.2µs and 1.6µs will be more appropriate. In general the flat top needs to be wide enough to accommodate the longest typical signal rise time from the detector. It then needs to be wider by one filter clock cycle than that minimum, but at least 3 clock cycles. Note that the filter clock cycle ranges from 0.026 to 0.853µs, depending on the filter time range, so that it is not possible to have a very short flat top together with a very long filter rise time. The Pixie Viewer provides a tool which automatically scans all possible combinations of energy filter rise time and flat top and finds the combination that gives the best energy resolution. This tool can be accessed by clicking the Optimize button on the Settings tab. Please refer to the Online Help documentation for more details.

3.6.3 Threshold and Trigger Filter Parameters In general, the trigger threshold should be set as low as possible for best resolution. If too low, the input count rate will go up dramatically and “noise peaks” will appear at the minimum edge of the spectrum. If the threshold is too high, especially at high count rates, low energy events below the threshold can pass the pile-up inspector and pile up with larger events. This increases the measured energy and thus leads to exponential tails on the ideally Gaussian peaks in the spectrum. Ideally, the threshold should be set such that the noise peaks just disappear. The settings of the trigger filter have only minor effect on the resolution. However, changing the trigger conditions might have some effect on certain undesirable peak shapes. A longer trigger rise time allows the threshold to be lowered more, since the noise is averaged over longer periods. This can help to remove tails on the peaks. A long trigger flat top will help to trigger on slow rising pulses and thus result in a sharper cut off at the threshold in the spectrum.

3.6.4 Decay time The preamplifier decay time τ is used to correct the energy of a pulse sitting on the falling slope of a previous pulse. The calculations assume a simple exponential decay with one decay constant. A precise value of τ is especially important at high count rates where pulses overlap more frequently. If τ is off the optimum, peaks in the spectrum will broaden, and if τ is very wrong, the spectrum will be significantly blurred. The first and usually sufficiently precise estimate of τ can be obtained from the Auto Find routine in the Calibrate tab. Measure the decay time several times and settle on the average value. Fine tuning of τ can be achieved by exploring small variations around the fit value (±2-3%). This is best done at high count rates, as the effect on the resolution is more pronounced. The


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value of τ found through this way is also valid for low count rates. Manually enter τ in the Calibrate tab, take a short run, and note the value of τ that gives the best resolution. Pixie users can also use the Manual Fit routine to manually find the decay time through exponentially fitting the untriggered input signals. Another tool is the Optimize routine. Similar to the routine for finding the optimal energy filter times, this routine can be used to automatically scan a range of decay times and find the optimal one. Please refer to the Online Help documentation for more details.


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4 Data Runs and Data Structures

4.1 Run types There are two major run types: MCA runs and List mode runs. MCA runs only collect spectra, List mode runs acquire data on an event-by event basis. List mode runs come in several variants. The output data are available in three different memory blocks. The multichannel analyser (MCA) block resides in memory external to the DSP. There is a local I/O data buffer for list mode data located in the DSP, consisting of 8192 16-bit words, and an extended I/O data buffer for list mode runs in the external memory, holding up to 32 local buffers.

4.1.1 MCA Runs If all you want to do is to collect spectra, you should start an MCA run. For each event, this type of run collects the data necessary to calculate pulse heights (energies) only. The energy values are used to increment the MCA spectrum. The run continues until the host computer stops data acquisition, either by reaching the run time set in the Pixie Viewer, or by a manual stop from the user (the module does not stop by itself). Run statistics, such as live time, run time, and count rates are kept in the Pixie module.

4.1.2 List Mode Runs If, on the other hand, you want to operate the Pixie in multi-parametric or list mode and collect data on an event-by-event basis, including energies, time stamps, pulse shape analysis values, and wave forms, you should start a list mode run. In list mode, you can still request histogramming of energies, e.g. for monitoring purposes. In the current software, one pulse shape analysis value is a constant fraction trigger time calculated by the DSP, the other is reserved for user-written event processing routines. The output data of list mode runs can be reduced by using one of the compressed formats described below. The key difference is that as less data is recorded for each event, there is room for more events in the I/O data buffer of the Pixie-4 module. List mode runs halt data acquisition either when the local I/O data buffer is full, or when a preset number of events are reached. The maximum number of events is calculated by the Pixie Viewer when selecting a run type, and downloaded to the module before starting a run. In Rev. C modules, the local buffer is then transferred to the external memory, and the run resumes. When the external memory is filled with 32 local buffers, the run stops, and the memory can be read out by the host software in a fast block read. As an alternative for low count rate applications or for systems including Rev. B modules, runs can be set up to end after just one local buffer is filled and no data is transferred to external memory.


15

Runs can be “resumed” by the host after the memory is read out. In a resumed run, run statistics are not cleared at the beginning of the run, i.e. it is possible to combine several buffer readouts (“spills”) into one extended run.

4.1.3 Fast List Mode Runs In Fast List Mode, data are collected on an event-by-event basis, but waveforms are not read. The output can again be stored in standard or compressed format. This is mainly a legacy run type, and only marginally faster (slightly shorter dead time from event processing) than a normal list mode run recording waveforms of zero length. To make it faster, a number of functions are omitted during data acquisition. For example, the live time and other run statistics are not updated during the run. Also, at high count rate, when an intermediate buffer for event processing fills faster with raw data than being emptied by the processing routine, output data can be corrupted as checks for this condition are omitted. It is therefore important to always keep the input rate below the average processing rate. Table 4.1: Summary of run types and data formats.

Output data DSP Variables List Mode (standard)

Energies, time stamps, 6 PSA values, and wave forms in List mode block. Spectra in MCA block

RUNTASK = 256 MAXEVENTS = <calculate> (CHANHEADLEN = 9)

List Mode Compression 1

Energies, time stamps, and 6 PSA values in List mode block. Spectra in MCA block






Energies and time stamps in List mode block. Spectra in MCA block


Fast List Mode (standard)



Fast List Mode Compression 1




16





Energies and time stamps in List mode block. Spectra in MCA block


MCA Mode Spectra in MCA block RUNTASK = 769 MAXEVENTS=0

4.2 Output data structures

4.2.1 MCA histogram data The MCA block is fixed to 32K words (32-bit deep) per channel, residing in the external memory. The memory can be read out via the PCI data bus at rates over 100Mbytes/s. If spectra of less than 32K length are requested, only part of the 32K will be filled with data. This data can be read even when a run is in progress, to get a spectrum update.

4.2.2 List mode data The list mode data in external memory consists of 32 local I/O data buffers. The local I/O data buffer can be written by the DSP in a number of formats. User code should access the three variables BUFHEADLEN, EVENTHEADLEN, and CHANHEADLEN in the configuration file of a particular run to navigate through the data set. It should only be read when the run has ended. The 32 buffers in external memory follow immediately one after the other. The data organization of one I/O buffer is as follows. The buffer content always starts with a buffer header of length BUFHEADLEN. Currently, BUFHEADLEN is six, and the six words are: Table 4.2: Buffer header data format.

Word # Variable Description 0 BUF_NDATA Number of words in this buffer 1 BUF_MODNUM Module number 2 BUF_FORMAT Format descriptor = RunTask + 0x1000 3 BUF_TIMEHI Run start time, high word 4 BUF_TIMEMI Run start time, middle word 5 BUF_TIMELO Run start time, low word

Following the buffer header, the events are stored in sequential order. Each event starts out with an event header of length EVENTHEADLEN. Currently, EVENTHEADLEN=3, and the three words are:


17

Table 4.3: Event header data format.

Word # Variable Description 0 EVT_PATTERN Hit pattern 1 EVT_TIMEHI Event time, high word2 EVT_TIMELO Event time, low word

The hit pattern is a bit mask, which tells which channels were read out. The LSB (bit 0), if set, indicates that channel 0 has been read. Bit number n, if set, indicates that channel n has been read. The bits set, 0…3, tells for which channels data have been recorded following the event header. After the event header there follow the channel information as indicated by the hit pattern, and in order of increasing channel numbers. The data for each channel are organized into a channel header of length CHANHEADLEN, which may be followed by waveform data. CHANHEADLEN depends on the run type and on the method of data buffering, i.e. if raw data is directed to the intermediate Level-1 buffer or directly to the linear buffer. Offline analysis programs should therefore check the value of RUNTASK, which are reported in the run settings file. All currently supported data formats are defined below.

1. For List Mode or Fast List Mode, either standard or compression 1, (RUNTASK = 256, 257, 512 or 513), CHANHEADLEN=9, and the nine words are

Table 4.4: Channel header, possibly followed by waveform data.

Word # Variable Description 0 CHAN_NDATA Number of words for this channel 1 CHAN_TRIGTIME Fast trigger time 2 CHAN_ENERGY Energy 3 CHAN_XIAPSA XIA PSA value 4 CHAN_USERPSA User PSA value 5 Unused N/A 6 Unused N/A 7 Unused N/A 8 CHAN_REALTIMEHI High word of the real time

Any waveform data for this channel would then follow this header. An offline analysis program can recognize this by computing N_WAVE_DATA=CHAN_DATA-9. If N__WAVE_DATA is greater than zero, it indicates the number of waveform data words to follow. In the current software version, the XIA PSA value contains the result of the constant fraction trigger time computation (CFD). The format is as follows: the upper 8-bit of the word point to the ADC sample before the CFD, counted from the beginning of the trace. The lower 8 bits give the fraction of an ADC sample time between the sample and the CFD time. For example, if the value is 0x0509, the CFD time is 5 + 9/256 ADC sample steps away from the beginning of the recorded trace.


18

2. For compression 2 List Mode or Fast List Mode (RUNTASK = 258 or 514),

CHANHEADLEN=4, and the four words are:

Table 4.5: Channel header for compression 2 format.

Word # Variable Description 1 CHAN_TRIGTIME Fast trigger time 2 CHAN_ENERGY Energy 3 CHAN_XIAPSA XIA PSA value 4 CHAN_USERPSA User PSA value

3. For compression 3 List Mode or Fast List Mode (RUNTASK = 259 or 515),

CHANHEADLEN=2, and the two words are: Table 4.6: Channel header for compression 3 format.

Word # Variable Description 1 CHAN_TRIGTIME Fast trigger time 2 CHAN_ENERGY Energy

Note that for runs with several modules and multiple spills, the buffer ordering in the data file has changed in Revision C modules. Previously (Revision B modules), the data file would begin with the first buffer readout of module 0, followed by first buffers of module 1, module 2, … module N, then the second buffers of modules 0 to N, and so forth. Now, since list mode runs are repeated 32 times before readout, the data file will begin with the first 32 buffer readouts of module 0, followed by the first 32 buffers of module 1, module 2, … module N, then a second 32 buffers of module 0 to N and so forth.


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5 Hardware Description The Pixie-4 is a 4-channel unit designed for gamma-ray spectroscopy and waveform capturing. It incorporates four functional building blocks, which we describe below. This section concentrates on the functionality aspect. Technical specification can be found in section 1.2. Figure 1 shows the functional block diagram of the Pixie-4.

Figure 5.1: Functional block diagram of the Pixie-4 front-end data acquisition and signal processing card.

5.1 Analog signal conditioning Each analog input has its own signal conditioning unit. The task of this circuitry is to adapt the incoming signals to the input voltage range of the ADC, which spans 2V. Input signals are adjusted for offsets, and there is a computer-controlled gain stage of switched relays. This helps to bring the signals into the ADC's voltage range and set the dynamic range of the channel. A fine tuning of the gain is achieved by multiplying the calculated energy values with digital gain factors in the digital signal processor (DSP).


20

The ADC is not a peak sensing ADC, but acts as a waveform digitizer. In order to avoid aliasing, we remove the high frequency components from the incoming signal prior to feeding it into the ADC. The anti-aliasing filter, an active Sallen-Key filter, cuts off sharply at the Nyquist frequency, namely half the ADC sampling frequency. Though the Pixie-4 can work with many different signal forms, best performance is to be expected when sending the output from a charge integrating preamplifier directly to the Pixie-4 without any further shaping.

5.2 Real-time processing units The real time processing units (RTPUs), one per two channels, consist of a field programmable gate array (FPGA) which also incorporates a FIFO memory for each channel. The data stream from the ADCs is sent to these units at the full ADC sampling rate. Using a pipelined architecture, the signals are also processed at this high rate, without the help of the on-board DSP. Note that the use of one RTPU for two channels allows sampling the incoming signal at twice the regular ADC clock frequency. If both channels are fed the same input signal, the RTPU can give the second ADC a clock with a 180 degree phase shift, thus sampling the signal twice in one clock cycle. Special software is required to combine the two input streams into one; contact XIA for details. The real-time processing units apply digital filtering to perform essentially the same action as a shaping amplifier. The important difference is in the type of filter used. In a digital application it is easy to implement finite impulse response filters, and we use a trapezoidal filter. The flat top will typically cover the rise time of the incoming signal and makes the pulse height measurement less sensitive to variations of the signal shape. Secondly, the RTPUs contain a pileup inspector. This logic ensures that if a second pulse is detected too soon after the first, so that it would corrupt the first pulse height measurement, both pulses are rejected as piled up. The pileup inspector is, however, not very effective in detecting pulse pileup on the rising edge of the first pulse, i.e. in general pulses must be separated by their rise time to be effectively recognized as different pulses. Therefore, for high count rate applications, the pulse rise times should be as short as possible, to minimize the occurrence of pileup peaks in the resulting spectra. If a pulse was detected and passed the pileup inspector, a trigger may be issued. That trigger would notify the DSP that there are raw data available now. If a trigger was issued the data remain latched until the RTPU has been serviced by the DSP. The third component of the RTPU is a FIFO memory, which is controlled by the pile up inspector logic. The FIFO memory is continuously being filled with waveform data from the ADC. On a trigger it is stopped, and the read pointer is positioned such that it points to the


21

beginning of the pulse that caused the trigger. When the DSP collects event data, it can read any fraction of the stored waveform, up to the full length of the FIFO.

5.3 Digital signal processor (DSP) The DSP controls the operation of the Pixie-4, reads raw data from the RTPUs, reconstructs true pulse heights, applies time stamps, prepares data for output to the host computer, and increments spectra in the on-board memory. The host computer communicates with the DSP, via the PCI interface, using a direct memory access (DMA) channel. Reading and writing data to DSP memory does not interrupt its operation, and can occur even while a measurement is underway. The host sets variables in the DSP memory and then calls DSP functions to program the hardware. Through this mechanism all gain and offset DACs are set and the RTPUs are programmed in this way. The RTPUs process their data without support from the DSP, once they have been set up. When any one or more of them generate a trigger, an interrupt request is sent to the DSP. It responds with reading the required raw data from the RTPUs and storing those in an intermediate buffer. It then returns from the interrupt routine without processing the data to minimize the DSP induced dead time. The event processing routine works from the data in the buffer to generate the requested output data. There are different implementations of the intermediate buffer for the different run types. In standard list mode runs, intermediate and I/O buffer are the same, to avoid moving long waveforms inside the DSP. In other run types, the intermediate buffer is circular, old data is overwritten once it has been processed. If the circular buffer fills up before the data can be processed, no further raw data is read from the RTPUs. In this scheme, the greatest processing power is located in the RTPUs. Implemented in FPGAs each of them processes the incoming waveforms from its associated ADC in real time and produces, for each valid a event, a small set of distilled data from which pulse heights and arrival times can be reconstructed. The computational load for the DSP is much reduced, as it has to react only on an event-by-event basis and has to work with only a small set of numbers for each event.

5.4 PCI interface The PCI interface through which the host communicates with the Pixie-4 is implemented in a PCI slave IC together with an FPGA. The configuration of this PCI IC is stored in a PROM, which is placed in the only DIP-8 IC-socket on the Pixie-4 board. The interface conforms to the commercial PCI standard. It moves 32-bit data words at a time. The interface dos not issue interrupt requests to the host computer. Instead, for example to determine when data is ready for readout, the host has to poll a Control and Status Register (CSR) in the communication FPGA.


22

The communication FPGA links the PCI slave with the DSP and the on-board memory. The host can read out the memory without interrupting the operation of the DSP. This allows updates of the MCA spectrum while a run is in progress.


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6 Theory of Operation

6.1 Digital Filters for γ-ray detectors Energy dispersive detectors, which include such solid state detectors as Si(Li), HPGe, HgI2, CdTe and CZT detectors, are generally operated with charge sensitive preamplifiers as shown in Figure 6.1 (a). Here the detector D is biased by voltage source V and connected to the input of preamplifier A which has feedback capacitor Cf and feedback resistor Rf. The output of the preamplifier following the absorption of an γ-ray of energy Ex in detector D is shown in Figure 6.1 (b) as a step of amplitude Vx (on a longer time scale, the step will decay exponentially back to the baseline, see section 6.3). When the γ-ray is absorbed in the detector material it releases an electric charge Qx = Ex/ε, where ε is a material constant. Qx is integrated onto Cf, to produce the voltage Vx = Qx/Cf = Ex/(εCf). Measuring the energy Ex of the γ-ray therefore requires a measurement of the voltage step Vx in the presence of the amplifier noise σ, as indicated in Figure 6.1 (b).

D C

V

-4

-2

0

2

4

0.00 0.02 0.04 0.06

Prea

mp

Out

put (

mV

)

Time (ms)

σ

V x

f

a) b)

A

R f

Figure 6.1: (a) Charge sensitive preamplifier with RC feedback; (b) Output on absorption of an γ-ray.

Reducing noise in an electrical measurement is accomplished by filtering. Traditional analog filters use combinations of a differentiation stage and multiple integration stages to convert the preamp output steps, such as shown in Figure 6.1 (b), into either triangular or semi-Gaussian pulses whose amplitudes (with respect to their baselines) are then proportional to Vx and thus to the γ-ray’s energy. Digital filtering proceeds from a slightly different perspective. Here the signal has been digitized and is no longer continuous. Instead it is a string of discrete values as shown in


24

Figure 6.2. Figure 6.2 is actually just a subset of Figure 6.1 (b), in which the signal was digitized by a Tektronix 544 TDS digital oscilloscope at 10 MSA (megasamples/sec). Given this data set, and some kind of arithmetic processor, the obvious approach to determining Vx is to take some sort of average over the points before the step and subtract it from the value of the average over the points after the step. That is, as shown in Figure 6.2, averages are computed over the two regions marked “Length” (the “Gap” region is omitted because the signal is changing rapidly here), and their difference taken as a measure of Vx. Thus the value Vx may be found from the equation:

∑ ∑+−=)( )(

,beforei afteri

iiiikx VWVWV (6.1)

where the values of the weighting constants iW determine the type of average being computed. The sums of the values of the two sets of weights must be individually normalized.

-4

-2

0

2

4

20 22 24 26 28 30

Pre

amp

Out

put (

mV

)

Time ( µ s)

Length

Length

Gap

Figure 6.2: Digitized version of the data of Figure 6.1 (b) in the step region.

The primary differences between different digital signal processors lie in two areas: what set of weights iW is used and how the regions are selected for the computation of Eqn. 6.1. Thus, for example, when larger weighting values are used for the region close to the step while smaller values are used for the data away from the step, Eqn. 6.1 produces “cusp-like” filters. When the weighting values are constant, one obtains triangular (if the gap is zero) or trapezoidal filters. The concept behind cusp-like filters is that, since the points nearest the step carry the most information about its height, they should be most strongly weighted in the averaging process. How one chooses the filter lengths results in time variant (the lengths vary


25

from pulse to pulse) or time invariant (the lengths are the same for all pulses) filters. Traditional analog filters are time invariant. The concept behind time variant filters is that, since the γ-rays arrive randomly and the lengths between them vary accordingly, one can make maximum use of the available information by setting the length to the interpulse spacing. In principal, the very best filtering is accomplished by using cusp-like weights and time variant filter length selection. There are serious costs associated with this approach however, both in terms of computational power required to evaluate the sums in real time and in the complexity of the electronics required to generate (usually from stored coefficients) normalized iW sets on a pulse by pulse basis. The Pixie-4 takes a different approach because it was optimized for very high speed operation. It implements a fixed length filter with all iW values equal to unity and in fact computes this sum afresh for each new signal value k. Thus the equation implemented is:

∑∑+−=

−−

+−−=

+−=k

Lkii

GLk

GLkiikx VVLV

112, (6.2)

where the filter length is L and the gap is G . The factor L multiplying kxV , arises because the sum of the weights here is not normalized. Accommodating this factor is trivial. While this relationship is very simple, it is still very effective. In the first place, this is the digital equivalent of triangular (or trapezoidal if G ≠ 0) filtering which is the analog industry’s standard for high rate processing. In the second place, one can show theoretically that if the noise in the signal is white (i.e. Gaussian distributed) above and below the step, which is typically the case for the short shaping times used for high signal rate processing, then the average in Eqn. 6.2 actually gives the best estimate of Vx in the least squares sense. This, of course, is why triangular filtering has been preferred at high rates. Triangular filtering with time variant filter lengths can, in principle, achieve both somewhat superior resolution and higher throughputs but comes at the cost of a significantly more complex circuit and a rate dependent resolution, which is unacceptable for many types of precise analysis. In practice, XIA’s design has been found to duplicate the energy resolution of the best analog shapers while approximately doubling their throughput, providing experimental confirmation of the validity of the approach.

6.2 Trapezoidal Filtering in the Pixie-4 From this point onward, we will only consider trapezoidal filtering as it is implemented in the Pixie-4 according to Eqn. 6.2. The result of applying such a filter with Length L=1µs and Gap G=0.4µs to a γ-ray event is shown in Figure 6.3. The filter output is clearly trapezoidal in shape and has a rise time equal to L, a flattop equal to G, and a symmetrical fall time equal to L. The basewidth, which is a first-order measure of the filter’s noise reduction properties, is thus 2L+G.


26

This raises several important points in comparing the noise performance of the Pixie-4 to analog filtering amplifiers. First, semi-Gaussian filters are usually specified by a shaping time. Their rise time is typically twice this and their pulses are not symmetric so that the basewidth is about 5.6 times the shaping time or 2.8 times their rise time. Thus a semi-Gaussian filter typically has a slightly better energy resolution than a triangular filter of the same rise time because it has a longer filtering time. This is typically accommodated in amplifiers offering both triangular and semi-Gaussian filtering by stretching the triangular rise time a bit, so that the true triangular rise time is typically 1.2 times the selected semi-Gaussian rise time. This also leads to an apparent advantage for the analog system when its energy resolution is compared to a digital system with the same nominal rise time. One important characteristic of a digitally shaped trapezoidal pulse is its extremely sharp termination on completion of the basewidth 2L+G. This may be compared to analog filtered pulses whose tails may persist up to 40% of the rise time, a phenomenon due to the finite bandwidth of the analog filter. As we shall see below, this sharp termination gives the digital filter a definite rate advantage in pileup free throughput.

33x103

32

31

30

AD

C u

nits

12.5µs12.011.511.010.510.09.5Time

GL2L+G

ADC output Filter Output

Figure 6.3: Trapezoidal filtering of a preamplifier step with L=1µs and G=0.4µs.

6.3 Baselines and preamplifier decay times Figure 6.4 shows an event over a longer time interval and how the filter treats the preamplifier noise in regions when no γ-ray pulses are present. As may be seen the effect of the filter is both to reduce the amplitude of the fluctuations and reduce their high frequency content. This signal is termed the baseline because it establishes the reference level from which the γ-ray peak amplitude Vx is to be measured. The fluctuations in the baseline have a


27

standard deviation σe which is referred to as the electronic noise of the system, a number which depends on the rise time of the filter used. Riding on top of this noise, the γ-ray peaks contribute an additional noise term, the Fano noise, which arises from statistical fluctuations in the amount of charge Qx produced when the γ-ray is absorbed in the detector. This Fano noise σf adds in quadrature with the electronic noise, so that the total noise σt in measuring Vx is found from

σt = sqrt( σf2 + σe

2) (3) The Fano noise is only a property of the detector material. The electronic noise, on the other hand, may have contributions from both the preamplifier and the amplifier. When the preamplifier and amplifier are both well designed and well matched, however, the amplifier’s noise contribution should be essentially negligible. Achieving this in the mixed analog-digital environment of a digital pulse processor is a non-trivial task, however.

33x103

32

31

30

29

28

AD

C u

nits

95µs90858075Time

σe

σt

Vx

ADC Output Filter Output

Figure 6.4: A γ-ray event displayed over a longer time period to show baseline noise and the effect of preamplifier decay time.

With a RC-type preamplifier, the slope of the preamplifier is rarely zero. Every step decays exponentially back to the DC level of the preamplifier. During such a decay, the baselines are obviously not zero. This can be seen in Figure 6.4, where the filter output during the exponential decay after the pulse is below the initial level. Note also that the flat top region is sloped downwards. Using the decay constant τ, the baselines can be mapped back to the DC level. This allows precise determination of γ-ray energies, even if the pulse sits on the falling slope of a previous pulse. The value of τ, being a characteristic of the preamplifier, has to be determined by the user and host software and downloaded to the module.


28

6.4 Thresholds and Pile-up Inspection As noted above, we wish to capture a value of Vx for each γ-ray detected and use these values to construct a spectrum. This process is also significantly different between digital and analog systems. In the analog system the peak value must be “captured” into an analog storage device, usually a capacitor, and “held” until it is digitized. Then the digital value is used to update a memory location to build the desired spectrum. During this analog to digital conversion process the system is dead to other events, which can severely reduce system throughput. Even single channel analyzer systems introduce significant deadtime at this stage since they must wait some period (typically a few microseconds) to determine whether or not the window condition is satisfied. Digital systems are much more efficient in this regard, since the values output by the filter are already digital values. All that is required is to take the filter sums, reconstruct the energy Vx, and add it to the spectrum. In the Pixie-4, the filter sums are continuously updated by the RTPU (see section 5.2), and only have to be read out by the DSP when an event occurs. Reconstructing the energy and incrementing the spectrum is done by the DSP, so that the RTPU is ready to take new data immediately after the readout. This usually takes much less than one filter rise time, so that no system deadtime is produced by a “capture and store” operation. This is a significant source of the enhanced throughput found in digital systems.

32x103

31

30

29

28

27

26

AD

C u

nits

48µs47464544Time

Threshold

Arrival Time Sampling Time

ADC Output Fast Filter Output Slow Filter Output

Figure 6.5: Peak detection and sampling in the Pixie-4. The peak detection and sampling in the Pixie-4 is handled as indicated in Figure 6.5. Two trapezoidal filters are implemented, a fast filter and a slow filter. The fast filter is used to detect the arrival of γ-rays, the slow filter is used for the measurement of Vx, with reduced


29

noise at longer filter rise times. The fast filter has a filter length Lf = 0.1µs and a gap Gf =0.1µs. The slow filter has Ls = 1.2µs and Gs = 0.35µs. The arrival of the γ-ray step (in the preamplifier output) is detected by digitally comparing the fast filter output to THRESHOLD, a digital constant set by the user. Crossing the threshold starts a counter to count PEAKSAMP clock cycles to arrive at the appropriate time to sample the value of the slow filter. Because the digital filtering processes are deterministic, PEAKSAMP depends only on the values of the fast and slow filter constants and the rise time of the preamplifier pulses. The slow filter value captured following PEAKSAMP is then the slow digital filter’s estimate of Vx.

36x103

34

32

30

28

26

24

22

20

AD

C u

nits

68µs666462605856Time

PeakSep

1

2

3

Fast Filter Output

Slow Filter Output

ADC Output

Figure 6.6: A sequence of 3 γ-ray pulses separated by various intervals to show the origin of pileup and demonstrate how it is detected by the Pixie-4.

The value Vx captured will only be a valid measure of the associated γ-ray’s energy provided that the filtered pulse is sufficiently well separated in time from its preceding and succeeding neighbor pulses so that their peak amplitudes are not distorted by the action of the trapezoidal filter. That is, if the pulse is not piled up. The relevant issues may be understood by reference to Figure 6.6, which shows 3 γ-rays arriving separated by various intervals. The fast filter has a filter length Lf = 0.1µs and a gap Gf =0.1µs. The slow filter has Ls = 1.2µs and Gs = 0.35µs. Because the trapezoidal filter is a linear filter, its output for a series of pulses is the linear sum of its outputs for the individual members in the series. Pileup occurs when the rising edge of one pulse lies under the peak (specifically the sampling point) of its neighbor. Thus, in Figure 6.6, peaks 1 and 2 are sufficiently well separated so that the leading edge of peak 2 falls after the peak of pulse 1. Because the trapezoidal filter function is symmetrical, this also means that pulse 1’s trailing edge also does not fall under the peak of pulse 2. For this to be true, the two pulses must be separated by at least an interval of L + G. Peaks 2 and 3, which


30

are separated by less than 1.0 µs, are thus seen to pileup in the present example with a 1.2 µs rise time. This leads to an important point: whether pulses suffer slow pileup depends critically on the rise time of the filter being used. The amount of pileup which occurs at a given average signal rate will increase with longer rise times. Because the fast filter rise time is only 0.1 µs, these γ-ray pulses do not pileup in the fast filter channel. The Pixie-4 can therefore test for slow channel pileup by measuring the fast filter for the interval PEAKSEP after a pulse arrival time. If no second pulse occurs in this interval, then there is no trailing edge pileup. PEAKSEP is usually set to a value close to L + G + 1. Pulse 1 passes this test, as shown in Figure 6.6. Pulse 2, however, fails the PEAKSEP test because pulse 3 follows less than 1.0 µs. Notice, by the symmetry of the trapezoidal filter, if pulse 2 is rejected because of pulse 3, then pulse 3 is similarly rejected because of pulse 2.

6.5 Filter range To accommodate the wide range of filter rise times from 0.053 µs to 106 µs, the filters are implemented in the RTPUs or FPGA configurations with different clock decimations (filter ranges). The ADC sampling rate is always 13.3ns, but in higher clock decimations, several ADC samples are averaged before entering the filtering logic. In filter range 1, 21 samples are averaged, 22 samples in filter range 2, and so on. Since the sum of rise time and flat top is limited to 127 decimated clock cycles, filter time granularity and filter time are limited to the values are listed in Table 6.1. Table 6.1: RTPU clock decimations and filter time granularity

Filter range Filter granularity max. Trise+Tflat min. Trise min. Tflat 1 0.0267µs 3.387µs 0.0533µs 0.08µs 2 0.0533µs 6.773µs 0.1067µs 0.16µs 3 0.1067µs 13.547µs 0.2133µs 0.32µs 4 0.2133µs 27.093µs 0.4267µs 0.64µs 5 0.4267µs 54.187µs 0.8533µs 1.28µs 6 0.8533µs 108.373µs 1.7067µs 2.56µs

All filter ranges are implemented in the same FPGA configuration. Only the “FILTERRANGE” parameter of the DSP has to be set to select a particular filter range.


31

7 Operating multiple Pixie-4 modules synchronously When many Pixie-4 modules are operating as a system, it may be required to synchronize clocks and timers between them and to distribute triggers across modules. It will also be necessary to ensure that runs are started and stopped synchronously in all modules. All these signals are distributed through the PXI backplane.

7.1 Clock distribution In a multi-module system, there will be one clock master and a number of clock slaves or repeaters. The clock function of a module can be selected by setting jumpers JP1, JP2 and JP3 near the back of the board. Pin 2 of JP2 is the input to the board’s clock distribution circuitry. It can be connected with a shunt to several other pins, thus choosing a particular clock distribution mode. These jumpers differ slightly for modules of Revision B and Revision C. The clock functions themselves described below are identical and compatible for both revisions. Pixie-4 Revision B

JP1 JP2

LOC

JP1 JP2 JP1 JP2 JP1 JP2

JP3 JP3

a) Individual or clock master mode

b) Clock repeater mode

c) Bussed clock master mode

d) Bussed clock slave mode

e) PXI clock slave mode

JP1 JP2

JP3 JP3 JP3

LOC

OUT BUS BUS

PXI

Figure 7.1. Jumper Settings for different clock distribution modes of Revision B modules. In a group of modules, there will be one daisy-chained clock master (a) in the leftmost position and several repeaters (b) OR one bussed clock master (c) and several bussed clock slaves (d). Modes (a/b) and (c/d) can not be mixed. Mode (e) can only be used with a backplane providing 37.5 MHz instead of the usual 10MHz. Jumper JP3 is located near the chip U2; it has no label.


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Pixie-4 Revision C

JP3

a) Individual or clock master mode

b) Clock repeater mode

c) Bussed clock master mode

d) Bussed clock slave mode

e) PXI clock slave mode

JP3 JP3 JP3 JP3 JP

1 JP

2

JP1

JP2

JP1

JP2

JP1

JP2

JP1

JP2

f) PXI clock master mode

JP3

JP1

JP2

LOC

OU

T

BU

S

BU

S

P

XI

IN L

OC

Left

IN

IN

IN L

OC

P

XI

BP

Figure 7.2. Jumper Settings for different clock distribution modes of Revision C modules. In a group of modules, there will be one daisy-chained clock master (a) in the leftmost position and several repeaters (b) OR one bussed clock master (c) and several bussed clock slaves (d) OR one PXI clock master (f) in slot 2 and several PXI clock slaves (e). Modes (a/b), (c/d), or (e/f) can not be mixed. Mode (e) can also be used with a custom module in slot 2 or a backplane providing 37.5 MHz instead of the usual 10MHz.

7.1.1 Individual Clock mode If only one Pixie-4 module is used in the system, or if clocks between modules do not have to be synchronized, the module should be set into individual clock mode, as shown in Figures 7.1 (a) and 7.2 (a). Connect pin 2 of JP2 (the clock input) with a shunt to pin 3 of JP2, which is labeled “LOC”. This will use the on-board clock crystal as the clock source.

7.1.2 Daisy-chained Clock Mode The preferred way to distribute clocks between modules is to daisy-chain the clocks from module to module, where each module repeats and amplifies the signal. This requires one master module, located in the leftmost slot of the group of Pixie-4 modules, with the same jumper settings as an individual module, see Figures 7.1 (a) and 7.2 (a). Configure the other modules in the chassis as clock repeaters by setting the jumpers as shown in Figures 7.1 (b) and 7.2 (b); i.e. remove all shunts from JP 1 and JP2 and set a shunt on JP3, located on top of the clock crystal U2. Note that the clock output is always enabled, i.e. every board, independent of its clock mode, sends out a clock to its right neighbor as long as it has a clock itself. Thus make sure that no other module sits to the right of a Pixie module that uses the PXI_LBR0 line on the PXI backplane for other purposes.

7.1.3 Bussed Clock Mode If there have to be gaps between a group of Pixie-4 modules, the daisy-chained clock distribution will not work since the chain is broken. In this case, the modules can be


33

configured for bussed clock mode. To do so, configure one module (in any slot) as the bussed clock master as shown in Figures 7.1 (c) and 7.2 (c), i.e. set one shunt to connect pins 2 and 3 on JP2 and a second shunt to connect Pin1 of JP1 and JP2 together(“OUT” to “BUS”). The clock master will drive the clock signal to a line that is bussed to all others slots in the chassis. The drive strength is limited to 3-4 modules. All other modules should be configured as clock slaves, i.e. set a shunt to connect pin 1 and 2 of JP2 (“BUS” to clock input) as shown in Figures 7.1 (d) and 7.2 (d). Note that the bussed clock line does usually not connect over a PCI bridge in chassis with more than 8 slots, whereas daisy-chains usually do. Always make sure that there is no shunt on JP3, in order to disconnect from the incoming daisy-chained clock, else there will be a conflict between the two clock signals.

7.1.4 PXI Clock Mode A further option for clock distribution is to use the PXI clock distributed on the backplane, by connecting pin 2 on JP1 and JP2 together (“PXI” to clock input), as shown in Figures 7.1 (e) and 7.2 (e). By default, this line is driven by the PXI backplane at a rate of 10 MHz - too slow to run the Pixie 4 modules. Only if a custom backplane provides 37.5 MHz, or if a module in slot 2 overrides the default signal from the backplane, can this input be used as an alternative setting for clock slaves. Such a module can be a Revision C Pixie module configured as PXI clock master, shown in Figure 7.2 (f), a XIA PDM power and trigger module, or any other suitable custom module. Always make sure that there is no shunt on JP3, in order to disconnect from the incoming daisy-chained clock, else there will be a conflict between the two clock signals.

7.2 Trigger distribution Two kinds of triggers can be distributed over the PXI backplane: Fast triggers and event triggers. Fast triggers are generated when the fast filter goes above threshold as described in section 6.4. Event triggers are generated if no pileup is detected in the PEAKSEP interval after the fast trigger; they essentially act as trigger validation. Both triggers are distributed over the PXI backplane as a wired-OR bussed signal. Normally pulled high, the signal is driven low by the module that issues a trigger. All other modules detect the line being low and use the fast trigger to stop the waveform acquisition in the FIFO, or use the event trigger to validate data for read. The reaction to distributed (group) triggers has to be enabled in the software, as described in the Online Help. Each channel can be enabled to respond to group triggers, and the module as a whole can either connect to the backplane and share triggers with other modules, or distribute triggers only within the module.


34

Note that for the trigger timing to be correct, all channels in a trigger group should be set to the same energy filter rise time and flat top.

7.3 Run Synchronization It is possible to make all Pixie-4 modules in a system start and stop runs at the same time by using a wired-OR SYNC line on the PXI backplane. In all modules the variable SYNCHWAIT has to be set to 1. If the run synchronization is not used SYNCHWAIT must be set to 0. The variable is set by checking the corresponding checkbox in the Run tab of the Pixie Viewer. The run synchronization works as follows. When the host computer requests a run start, the Pixie-4’s DSP will first execute a run initialization sequence (clearing memory etc). At the beginning of the run initialization the DSP causes the SYNC line to be driven low. At the end of the initialization, the DSP enters a waiting loop, and allows the SYNC line to be pulled high by pullup resistors. As long as at least one of all modules is still in the initialization, the SYNC line will be low. When all modules are done with the initialization and waiting loop, the SYNC line will go high. The low->high transition will signal the DSP to break out of the loop and begin taking data. If the timers in all modules are to be synchronized at this point, set the variable INSYNCH to 0 by checking the corresponding checkbox in the Run tab of the Pixie Viewer. This instructs the DSP to reset all timers to zero when coming out of the waiting loop. From then on they will remain in synch if the system is operated from one master clock. Whenever a module encounters an end-of-run condition and stops the run it will also drive the SYNC line low. This will be detected in all other modules, and in turn stop the data acquisition. Note that if the run synchronization is not operating properly and there was a run start request with SYNCHWAIT=1, the DSP will be caught in an infinite loop. This can be recognized by reading the variables INSYNCH and SYNCHWAIT. If after the run start request the DSP continues to show INSYNCH=0 and SYNCHWAIT=1, it is stuck in the loop waiting for an OK to begin the run. Besides rebooting, there is a software way to force the DSP to exit from that loop and to lead it back to regular operation. See the Programmer’s Manual for details.

7.4 External gate — GFLT (Veto) It is common in larger applications to have dedicated electronics to create event triggers or vetoes. While the Pixie-4 does not accept an external fast trigger, it does accept a global first level trigger (GFLT). This signal acts as a validation for an event already recognized by the Pixie-4. Based on multiplicities and other information the dedicated trigger logic needs to


35

make the decision whether to accept or reject a given event. If that decision can be made within a filter rise time of all Pixie-4 channels involved, then the GFLT input can be used. The GFLT signal applied to the Pixie-4 must be logic 0 at the time when the event data are latched in the RTPUs. This happens not before a filter rise time has passed since the event arrival and not later than a rise time plus the flat top. Therefore the trigger logic should generate a GFLT pulse that is logic 0 during the filter flat top. The GFLT signal is distributed through the PXI backplane. Using XIA’s PDM module or a custom board, external signals can be connected to the backplane. Each involved channel can be programmed individually to require the presence of a GFLT in order to latch event data. This is achieved by setting the corresponding checkbox in the Pixie Viewer’s Channel Control Register panel.


36

8 Troubleshooting

8.1 Startup Problems The following describes solutions to common startup problems.

1. Computer does not boot when Pixie module is installed in chassis This is usually caused by an incorrect clock setting on the Pixie module. The module needs to have a valid clock to respond to the computer’s scanning of the PCI bus.

2. Computer reports new hardware found, needs driver files Whenever a Pixie module is installed in a slot of the chassis for the first time, it is detected as new hardware, even if Pixie modules have been installed in other slots previously. Point Windows to the driver files provides with the software distribution.

3. When starting the Pixie Viewer, IGOR reports compile error For IGOR to start up properly, a number of driver files have to be in the correct locations. In particular, the file pixie.xop has to be located in the “Igor Extensions” folder – usually C:\Program Files\Wavemetrics\Igor Pro\Igor Extensions in a default installation.

4. When starting up modules in the Pixie Viewer, downloads are not “successful” This can have a number of reasons. Verify that - The files and paths point to valid locations; - The slot numbers entered in the Startup panel match the location of the modules.

5. After starting up modules, the ADC traces show only rectangular waves. This problem can be caused by downloading the wrong Communication FPGA file (e.g. A Rev. B file to a Rev. C module). Verify the file names are correct.


37

9 Appendix A This section contains hardware-related information.

9.1 Jumpers Table 9.1: Analog conditioning selection jumpers on Pixie-4 modules. x=1..4 for channel 0..3.

JPx00 Set for input impedance of 50Ω. If not set, input impedance is 10KΩ. JPx01 Remove only if you require attenuation. Attenuation will be 1:7.5 if JPx00 is

set. JPx05 (Revision B only) Set to “VGA” to enable contributions of the variable gain

amplifier to the overall system gain for fine tuning of the gain. This might increase the signal noise and is currently not supported by software.

Table 9.2: On-board jumper settings for the clock distribution on Pixie-4 modules.

Clock mode JP1 and JP2 JP3 PCB Reference Single Module Connect pins 2 and 3 of JP2

not set LOC to IN

Daisy-Chained Clock Master

Connect pins 2 and 3 of JP2 not set LOC to IN

Daisy-Chained Clock Repeater

Not set set Left

Bussed Clock Master

Connect pins 2 and 3 of JP2 Connect pin1, JP1 to pin 1, JP2

not set LOC to IN OUT to BUS

Bussed Clock Slave

Connect pins 1 and 2 of JP2

not set BUS to IN

Clock Slave with PXI clock

Connect pin2, JP1 to pin 2, JP2 not set PXI to IN

Clock Master for PXI clock (Revision C only)

Connect pin2, JP1 to pin 2, JP2 Connect pin3, JP1 to pin 3, JP2

not set PXI to IN LOC to BP


38

9.2 PXI backplane pin functions Table 9.3: Pins of the J2 backplane connector defined in the PXI standard used by the Pixie-4. Pins not listed are not connected except for pull-ups to 5V recommended by the PXI standard.

J2 pin number

PXI pin name

Connection Type Pixie pin function

1A LBL9 Left neighbor Nearest Neighbor 0 (left) 16A TRIG1 Bussed Event Trigger 17A TRIG2 Bussed Veto 18A TRIG3 Bussed Sync 21A LBR0 Right neighbor Clock output 16B TRIG0 Bussed Fast Trigger 18B TRIG4 Bussed Reserved 1C LBL10 Left neighbor Nearest Neighbor 1 (left) 3C LBR8 Right neighbor Token Ring Out 18C TRIG5 Bussed Token Ring Return 20C LBL0 Left neighbor Clock input 3D LBR9 Right neighbor Nearest Neighbor 0 (right) 17D STAR Star trigger to slot 2 Reserved 2E LBL8 Left neighbor Token Ring In 3E LBR10 Right neighbor Nearest Neighbor 1 (right) 16E TRIG7 Bussed Bussed Clock 17E CLK10 Clock PXI Clock


39

9.3 Control and Status Register Bits

Table 9.4: Control and Status Register of the Pixie-4 System FPGA

CSR, revision-B modules: 0x0001 Bit 0 RunEna Set to 1 to start data acquisition or 0 to stop.

Automatically cleared when DSP de-asserts Active to end run.

0x0002 Bit 1 Unused Reserved for future use. 0x0004 Bit 2 PCIactive Set to reserve external memory I/O for host

0x0008 Bit 3 Unused Reserved for future use. 0x0010 Bit 4 DSPReset Write only.

Set to reset DSP processor to initiate program download 0x0020 Bit 5 SynchCtrl Read only. If low, module is busy with run initialization,

has filled its I/O buffer with data, or is finished with the run.

0x0040 Bit 6 Unused Reserved for future use. 0x0080 Bit 7 Unused Reserved for future use. 0x0100 Bit 8 SynchFlag Read only. Reserved for future use. 0x0200 Bit 9 Live* Read only. If zero, DSP is taking data. 0x0400 Bit 10 Unused Reserved for future use. 0x0800 Bit 11 Unused Reserved for future use. 0x1000 Bit 12 Unused Reserved for future use. 0x2000 Bit 13 Active Read only. If set, there is a run in progress. 0x4000 Bit 14 LAMState Read only. If set, LAM is set internally. 0x8000 Bit 15 Unused Reserved for future use.

Programmer's Manual Digital Gamma Finder (DGF)

PIXIE-4

Version 1.20, August 2004





PIXIE-4 Programmer’s Manual V1.20 XIA 2004. All rights reserved.

ii

Table of Contents

1 Overview ........................................................................................................................ 1 2 PIXIE-4 API................................................................................................................... 1

Pixie_Hand_Down_Names ................................................................................................. 3 Pixie_Boot_System ............................................................................................................. 5 Pixie_User_Par_IO.............................................................................................................. 6 Pixie_Acquire_Data............................................................................................................. 9 Pixie_Set_Current_ModChan............................................................................................ 13 Pixie_Buffer_IO ................................................................................................................ 14 Options for Compiling PIXIE-4 API................................................................................. 17

3 Control PIXIE-4 Modules via CompactPCI................................................................. 18 3.1 Initializing............................................................................................................... 18

3.1.1 Initialize Global Variables ........................................................................... 18 3.1.2 Boot PIXIE Modules.................................................................................... 19

3.2 Setting DSP variables ............................................................................................. 21 3.3 Access spectrum memory or list mode data ........................................................... 23

3.3.1 Access spectrum memory............................................................................. 23 3.3.2 Access list mode data ................................................................................... 24

4 User Accessible Variables............................................................................................ 28 4.1 Module parameters.................................................................................................. 28 4.2 Channel variables.................................................................................................... 32

5 Control Tasks ............................................................................................................... 44 6 Appendix A — User supplied DSP code ..................................................................... 47

6.1 Introduction............................................................................................................. 47 6.2 The development environment ............................................................................... 47 6.3 Interfacing user code to XIA’s DSP code............................................................... 47 6.4 The interface ........................................................................................................... 48 6.5 Debugging tools ...................................................................................................... 51


1

1 Overview This manual is divided into three major sections. The first section is a description of the PIXIE-4 application program interface (API). Advanced users can build their own user interface using these API functions. The second section is a reference guide to program the PIXIE-4 modules using the PIXIE-4 API. This will be interesting to those users who want to integrate the PIXIE-4 modules into their own data acquisition system. The third section describes those user accessible variables that control the functions of the PIXIE-4 modules. Those advanced and curious users can use this section to better understand the operation of the PIXIE-4. Additionally, this manual also includes instructions on how to write User DSP code.

2 PIXIE-4 API The PIXIE-4 API consists of a set of C functions for building various coincidence data acquisition applications. It can be used to configure Pixie-4 modules, make MCA or list mode runs and retrieve data from the Pixie modules. The API can be compiled as a WaveMetrics Igor XOP file which is currently used by the Pixie-4 Viewer, a dynamic link library (DLL) or static library to be used in customized user interfaces or applications. In order to better illustrate the usage of these functions, an overview of the operation of Pixie-4 is given below and the usage of these functions is mentioned wherever appropriate. At first the PIXIE-4 API needs to be initialized. This is a process in which the names of system configuration files and variables are downloaded to the API. The function Pixie_Hand_Down_Names is used to achieve this. The second step is to boot the Pixie modules. It involves initializing each PXI slot where a Pixie module is installed, downloading all FPGA configurations and booting the digital signal processor (DSP). It concludes with downloading all DSP parameters (the instrument settings) and commanding the DSP to program the FPGAs and the on-board digital to analog converters (DACs). All this has been encapsulated in a single function Pixie_Boot_System. Now, the instrument is ready for data acquisition. The function used for this purpose is Pixie_Acquire_Data. By setting different run types, it can be used to start, stop or poll a data acquisition run (list mode run, MCA run, or special task runs like acquiring ADC traces). It can also be used to retrieve list mode or histogram data from the Pixie modules. After checking the quality of a MCA spectrum, a Pixie user may decide to change one or more settings like energy filter rise time or flat top. The function used to change Pixie settings is Pixie_User_Par_IO. This function converts a user parameter like energy filter rise time in µs into a number understood by the Pixie hardware or vice versa. Another function, Pixie_Buffer_IO, is used to read data from DSP’s internal memory to the host or write data from the host into the internal memory. This is useful for diagnosing Pixie


2

modules by looking at their internal memory values. The other usage of this function is to read, save, copy or extract Pixie’s configurations though its settings files. In a multi-module Pixie-4 system, it is essential for the host to know which module or channel it is communicating to. The function Pixie_Set_Current_ModChan is used to set the current module and channel. The detailed description of each function is given below.


3

Pixie_Hand_Down_Names

Syntax S32 Pixie_Hand_Down_Names ( U8 *Names[], // An array containing the names to be downloaded U8 *Name); // A string indicating the type of names (file or

// variable names) to be downloaded Description Use this function to download the file or variable names from the host user interface to the Pixie-4 API. The API needs these file names so that it can read the Pixie hardware configurations from the files stored in the host computer and download these configurations to the Pixie. The variable names are used by the API to obtain the indices of the DSP variables when the API converts user variable values into DSP variable values or vice versa. Parameter description Names is a two dimensional string array containing either the file names or the variable names. The API will know which type of names is being downloaded by checking the other parameter Name:

1. ALL_FILES: This indicates we are downloading boot files names. In this case, Names is a string array which has N_BOOT_FILES elements. Currently N_BOOT_FILES is defined as 7. The elements of Names are the names of communication FPGA files (Revision B and Revision C, respectively), signal processing FPGA file, DSP executable code binary file, DSP I/O parameter values file, DSP code I/O variable names file, and DSP code memory variable names file. All file names should contain the complete path name.

2. SYSTEM: This indicates we are downloading System_Parameter_Names.

System_Parameter_Names are those global variables that are applicable to all modules in a Pixie system, e.g. number of Pixie modules in the chassis, etc. System_Parameter_Names currently can hold 64 names. If less than 64 names are needed (which is the current case), the remaining names should be defined as empty strings. A detailed description of System_Parameter_Names is given in Table 3.5.

3. MODULE: This indicates we are downloading Module_Parameter_Names.

Module_Parameter_Names are those global variables that are applicable to each individual module, e.g. module number, module CSR, coincidence pattern, and run type, etc. Module_Parameter_Names can currently hold 64 names. If less than 64 names are needed (which is the current case), the remaining names should be defined as empty strings. A detailed description of Module_Parameter_Names is given in Table 3.5.


4

4. CHANNEL: This indicates we are downloading Channel_Parameter_Names. Channel_Parameter_Names are those global variables that are applicable to individual channels of the Pixie modules, e.g. channel CSR, filter rise time, filter flat top, voltage gain, and DC offset, etc. Channel_Parameter_Names currently can hold 64 names. If less than 64 names are needed (which is the current case), the remaining names should be defined as empty strings. A detailed description of Channel_Parameter_Names is given in Table 3.5.

Return values

Value Description Error Handling 0 Success None -1 Invalid name Check the second parameter Name Usage example S32 retval; // download system parameter names; define System_Parameter_Names first retval = Pixie_Hand_Down_Names(System_Parameter_Names, "SYSTEM"); if(retval < 0) // error handling // download module parameter names; define Module_Parameter_Names first retval = Pixie_Hand_Down_Names(Module_Parameter_Names, "MODULE"); if(retval < 0) // error handling // download channel parameter names; define Channel_Parameter_Names // first retval = Pixie_Hand_Down_Names(Channel_Parameter_Names, "CHANNEL"); if(retval < 0) // error handling // download boot file names; define All_Files first retval = Pixie_Hand_Down_Names(All_Files, "ALL_FILES"); if(retval < 0) // error handling


5

Pixie_Boot_System

Syntax S32 Pixie_Boot_System ( U16 Boot_Pattern); // The Pixie-4 boot pattern

Description Use this function to boot all Pixie modules in the system. Before booting the modules, it scans all PXI crate slots and finds the address for each slot where a Pixie module is installed. Parameter description Boot_Pattern is a bit mask used to control the boot pattern of Pixie modules:

Bit 0: Boot communication FPGA Bit 1: Boot signal processing FPGA Bit 2: Boot DSP Bit 3: Load DSP parameters Bit 4: Apply DSP parameters (call Set_DACs and Program_FIPPI)

Under most of the circumstances, all the above tasks should be executed to initialize the Pixie modules, i.e. the Boot_Pattern should be 0x1F. Return values

Value Description Error Handling 0 Success None -1 Unable to scan crate slots Check PXI slot map -2 Unable to read communication FPGA configuration (Rev. B) Check comFPGA file -3 Unable to read communication FPGA configuration (Rev. C) Check comFPGA file -4 Unable to read signal processing FPGA configuration Check SPFPGA file -5 Unable to read DSP executable code Check DSP code file -6 Unable to read DSP parameter values Check DSP parameter file-7 Unable to initialize DSP parameter names Check DSP .var file -8 Failed to boot all modules present in the system Check Pixie modules Usage example S32 intval; retval = Pixie_Boot_System(0x1F); if(ret < 0) // error handling


6

Pixie_User_Par_IO

Syntax S32 Pixie_User_Par_IO ( double *User_Par_Values, // A double precision array containing the

// user parameters to be transferred U8 *User_Par_Name, // A string variable indicating which user // parameter is being transferred U8 *User_Par_Type, // A string variable indicating which type // of user parameters is being transferred U16 Direction, // I/O direction (read or write) U8 ModNum, // Number of the module to work on U8 ChaNum); // Channel number of the Pixie module

Description Use this function to transfer user parameters between the user interface, the API and DSP’s I/O memory. Some of these parameters (User_Par_Type = “SYSTEM”) are applicable to all Pixie modules in the system, like the total number of Pixie modules in the system. Other parameters (User_Par_Type = “MODULE”) are applicable to a whole Pixie module (independent of its four channels), e.g. coincidence pattern, Module CSRA, etc. The final set of parameters (User_Par_Type = “CHANNEL”) are applicable to each individual channel in a Pixie module, e.g. energy filter settings or voltage gain, etc. For those parameters which need to be transferred to or from DSP’s internal memory (other parameters such as number of modules are only used by the API), this function will call another function UA_PAR_IO which first converts these parameters into numbers that are recognized by both the DSP and the API then performs the transfer. Parameter description User_Par_Values is a double precision array containing the parameters to be transferred. Depending on another input parameter User_Par_Type, different User_Par_Values array should be used. Totally three User_Par_Values arrays should be defined and all of them are one-dimensional arrays. The corresponding relationship between User_Par_Values and User_Par_Type is shown in Table 2.1. Table 2.1: The Combination of User_Par_Name and User_Par_Values.

User_Par_Values User_Par_Type Name Size Data Type SYSTEM System_Parameter_Values 64 Double precision MODULE Module_Parameter_Values 64×7 Double precision CHANNEL Channel_Parameter_Values 64×7×4 Double precision


7

The way to fill the Channel_Parameter_Values array is to fill the channel first then the module. For instance, first 64 values are stored in the array for channel 0, and then repeat this for other three channels. After that, 64×4 values have been filled for module 0. Then repeat this for the remaining modules. For the Module_Parameter_Values array, first store 64 values for module 0, and then repeat this for the other modules. User_Par_Name is the name of the variable which is to be transferred. It is one element of either System_Parameter_Names, or Module_Parameter_Names, or Channel_Parameter_Names. direction indicates the transfer direction of parameters:

0 - download (write) parameters from the user interface to the API; 1 - upload (read) parameters from the API to the user interface.

ModNum is the number of the Pixie module being communicated to. ChanNum is the channel number of the Pixie module being communicated to. Return values

Value Description Error Handling 0 Success None -1 Null pointer for User_Par_Values Check User_Par_Values-2 Invalid user parameter name Check User_Par_Name -3 Invalid user parameter type Check User_Par_Type -4 Invalid I/O direction Check direction -5 Invalid Pixie module number Check ModNum -6 Invalid Pixie channel number Check ChanNum Usage example U16 direction, modnum, channum; S32 retval; direction = 0; // download modnum = 0; // Module #0 channum = 1; // Channel #1 // set module parameter COINCIDENCE_PATTERN to 0xFFFF Module_Parameter_Values[Coincidence_Pattern_Index]=0xFFFF; // download COINCIDENCE_PATTERN to the DSP retval = Pixie_User_Par_IO(Module_Parameter_Values,

"COINCIDENCE_PATTERN", “MODULE”, direction, modnum, channum); if(retval < 0) // error handling // set channel parameter ENERGY_RISETIME to 6.0 µs


8

Channel_Parameter_Values[ENERGY_RISETIME_Index]=6.0; // download ENERGY_RISETIME to DSP retval = Pixie_User_Par_IO(Channel_Parameter_Values, “ENERGY_RISETIME”,

“CHANNEL”, direction, modnum, channum); if(retval < 0) // error handling


9

Pixie_Acquire_Data

Syntax S32 Pixie_Acquire_Data ( U16 Run_Type, // Data acquisition run type U32 *User_data, // An unsigned 32-bit integer array containing the // data to be transferred U8 *file_name, // Name of the file used to store list mode or MCA // histogram data U8 ModNum); // The number of the Pixie module

Description Use this function to acquire ADC traces, MCA histogram, or list mode data. The string variable file_name needs to be specified when stopping a MCA run or list mode run in order to save the data into a file, or when calling those special list mode runs to retrieve list mode data from a saved list mode data file. In all other cases, file_name can be specified as an empty string. The unsigned 32-bit integer array User_data is only used for acquiring ADC traces (control task 0x4), reading out list mode data or MCA spectrum. In all other cases, User_data can be any unsigned integer array with arbitrary size. Make sure that User_data has the correct size and data type before reading out ADC traces, list mode data, or MCA spectrum. Parameter description Run_Type is a 16-bit word whose lower 12-bit specifies the type of either data run or control task run and upper 4-bit specifies actions (start\stop\poll) as described below.

Lower 12-bit: 0x100,0x101,0x102,0x103 list mode runs

0x200,0x201,0x202,0x203 fast list mode runs 0x301 MCA run 0x1 -> 0x15 control task runs Upper 4-bit: 0x0000 start a control task run 0x1000 start a new data run 0x2000 resume a data run 0x3000 stop a data run 0x4000 poll run status 0x5000 read histogram data and save it to a file 0x6000 read list mode buffer data and save it to a file 0x7000 offline list mode data parse routines 0x7001 parse list mode data file 0x7002 locate traces


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0x7003 read traces 0x7004 read energies 0x7005 read PSA values 0x8000 manually read MCA histogram from a MCA file 0x9000 external memory (EM) I/O 0x9001 read histogram memory section of EM 0x9002 write to histogram memory section of EM 0x9003 read list mode memory section of EM 0x9004 write to list mode memory section of EM file_name is a string variable which specifies the name of the output file. It needs to have the complete file path. Return values Return values depend on the run type:

Run type = 0x0000

Value Description Error Handling 0 Success None -0x1 Invalid Pixie module number Check ModNum -0x2 Failure to adjust offsets Reboot the module-0x3 Failure to acquire ADC traces Reboot the module-0x4 Failure to start the control task run Reboot the module

Run type = 0x1000

Value Description Error Handling 0x10 Success None -0x11 Invalid Pixie module number Check ModNum -0x12 Failure to start the data run Reboot the module

Run type = 0x2000

Value Description Error Handling 0x20 Success None -0x21 Invalid Pixie module number Check ModNum -0x22 Failure to resume the data run Reboot the module

Run type = 0x3000

Value Description Error Handling 0x30 Success None -0x31 Invalid Pixie module number Check ModNum -0x32 Failure to end the run Reboot the module


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Run type = 0x4000

Value Description Error Handling0 No run is in progress N/A 1 Run is in progress N/A CSR value When run type = 0x40FF N/A -0x41 Invalid Pixie module number Check ModNum

Run type = 0x5000

Value Description Error Handling 0x50 Success None -0x51 Failure to save histogram data to a file Check the file name

Run type = 0x6000

Value Description Error Handling 0x60 Success None -0x61 Failure to save list mode data to a file Check the file name

Run type = 0x7000

Value Description Error Handling 0x70 Success None -0x71 Failure to parse the list mode data file Check list mode data file -0x72 Failure to locate list mode traces Check list mode data file -0x73 Failure to read list mode traces Check list mode data file -0x74 Failure to read event energies Check list mode data file -0x75 Failure to read PSA values Check list mode data file -0x76 Invalid list mode parse analysis request Check run type

Run type = 0x8000

Value Description Error Handling 0x80 Success None -0x81 Failure to read out MCA spectrum from the file Check the MCA data file

Run type = 0x9000

Value Description Error Handling 0x90 Success None -0x91 Failure to read out MCA section of external memory Reboot the module -0x92 Failure to write to MCA section of external memory Reboot the module -0x93 Failure to read out LM section of external memory Reboot the module -0x94 Failure to write to LM section of external memory Reboot the module -0x95 Invalid external memory I/O request Check the run type


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Usage example S32 retval; U16 RunType; U32 dummy[2]; U8 ModNum; RunType = 0x1100; // start a new list mode run ModNum = 0; retval = Pixie_Acquire_Data(RunType, dummy, “ ”, ModNum); if(retval != 0x10) // Error handling // wait until the run has ended RunType = 0x4100; while( ! Pixie_Acquire_Data(RunType, dummy, “ ”, ModNum) ) ; // Read out the list mode data from all Pixie modules and save to a file RunType = 0x6100; retval = Pixie_Acquire_Data(RunType, dummy, “C:\XIA\Pixie4\PulseShape\Listdata0001.bin”, ModNum); if(retval != 0x60) // Error handling // Read out the histogram data from all Pixie modules and save to a file RunType = 0x5100; retval = Pixie_Acquire_Data(RunType, dummy,

“C:\XIA\Pixie4\MCA\Histdata0001.bin”, ModNum); if(retval != 0x50) // Error handling


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Pixie_Set_Current_ModChan

Syntax S32 Pixie_Set_Current_ModChan ( U8 Module, // Module number to be set U8 Channel); // Channel number to be set

Description Use this function to set the current module number and channel number. Parameter description Module specifies the current module to be set. Module should be in the range of 0 to MAX_NUMBER_OF_MODULES (currently MAX_NUMBER_OF_MODULES is set to 7). Channel specifies the current channel to be set. Channel should be in the range of 0 to NUMBER_OF_CHANNELS - 1 (currently NUMBER_OF_CHANNELS is set to 4). Return values

Value Description Error Handling0 Success None -1 Invalid module number Check Module -2 Invalid channel number Check Channel Usage example // Set current module to 1 and current channel to 3 Pixie_Set_Current_ModChan(1, 3);


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Pixie_Buffer_IO

Syntax S32 Pixie_Buffer_IO (

U16 *Values, // An unsigned 16-bit integer array containing the // data to be transferred U8 type, // Data transfer type U8 direction, // Data transfer direction U8 *file_name, // File name

U8 ModNum); // Module number Description Use this function to:

1) Download or upload DSP parameters between the user interface and the Pixie modules; 2) Save DSP parameters into a settings file or load DSP parameters from a settings file

and applies to all modules present in the system; 3) Copy parameters from one module to others or extracts parameters from a settings file

and applies to the selected modules. Parameter description Values is an unsigned 16-bit integer array used for data transfer between the user interface and Pixie modules. type specifies the I/O type. direction indicates the data flow direction. The string variable file_name contains the name of settings files. Different combinations of the three parameters - Values, type, direction – designate different I/O operations as listed in Table 2.2. Table 2.2: Different I/O operations using function Pixie_Buffer_IO.

Type Direction Values I/O Operation 0 Write DSP I/O variable values to modules

0 1

DSP I/O variable values Read DSP I/O variable values from modules

0* Values to be written Write to certain locations of the data memory 1

1 All DSP variable values Read all DSP variable values from modules 0 Save current settings in all modules to a file

2 1

N/A** Read settings from a file and apply to all modules in the system

0 Extract settings from a file and apply to selected modules

3 1

Values[0] – source module number; Values[1] – source channel number; Values[2] – copy/extract pattern bit mask; Values[3], Values[4], … - destination channel pattern

Copy settings from a source module to destination modules

4 N/A*** Values[0] – address; Values[1] – length

Specify the location and number of words to be written into the data memory


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*Special care should be taken for this I/O operation since mistakenly writing to some locations of the data memory will cause the system to crash. The Type 4 I/O operation should be called first to specify the location and the number of words to be written before calling this one. If necessary, please contact XIA for assistance. **Any unsigned 16-bit integer array could be used here. ***Direction can be either 0 or 1 and it has no effect on the operation. Return values

Value Description Error Handling 0 Success None -1 Failure to set DACs after writing DSP parameters Reboot the module -2 Failure to program Fippi after writing DSP parameters Reboot the module -3 Failure to set DACs after loading DSP parameters Reboot the module -4 Failure to program Fippi after loading DSP parameters Reboot the module -5 Can't open settings file for loading Check the file name-6 Can't open settings file for reading Check the file name-7 Can't open settings file to extract settings Check the file name-8 Failure to set DACs after copying or extracting settings Reboot the module -9 Failure to program Fippi after copying or extracting settings Reboot the module -10 Invalid module number Check ModNum -11 Invalid I/O direction Check direction -12 Invalid I/O type Check type Usage example S32 retval; U8 type, direction, modnum; modnum = 0; // Module number // Download DSP parameters to the current Pixie module; DSP_Values is a // pointer pointing to the DSP parameters; no need to specify file name // here. direction = 0; // Write type = 0; // DSP I/O values retval = Pixie_Buffer_IO(DSP_Values, type, direction, “”, modnum); if(retval < 0) // Error handling // Read DSP memory values from the current PIXIE module; Memory_Values // is a pointer pointing to the memory block; no need to specify file // name Here. direction = 1; // Read type = 1; // DSP memory values retval = Pixie_Buffer_IO(Memory_Values, type, direction, “”, modnum); if(retval < 0)


16

// Error handling


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Options for Compiling PIXIE-4 API Pixie-4 API can be compiled as either a WaveMetrics Igor XOP file which is currently used by the Pixie-4 Viewer, a dynamic link library (DLL) or static library. The two latter options can be used by advanced users to integrate Pixie modules into their own data acquisition systems. The following table summarizes the required files for these options. Table 2.3: Options for compiling the PIXIE-4 C Driver.

Required Files Compilation Option C source files C header files Library files

a dynamic link library (DLL)

or static library

Boot.c, eeprom.c, pixie_c.c, utilities.c

boot.h, defs.h, globals.h, sharedfiles.h, utilities.h, PciApi.h, PciRegs.h, Plx.h, PlxApi.h, PlxDefinitionsCheck.h, PlxError.h, PlxTypes.h, Reg9054.h

PlxApi.lib, PlxApi.dll

Igor XOP

Boot.c, eeprom.c, pixie_c.c, utilities.c, pixie4_iface.c, pixie4_igor.c, PixieWinCustom.rc

boot.h, defs.h, globals.h, pixie4_iface.h, sharedfiles.h, utilities.h, PciApi.h, PciRegs.h, Plx.h, PlxApi.h, PlxDefinitionsCheck.h, PlxError.h, PlxTypes.h, Reg9054.h

PlxApi.lib, PlxApi.dll

The Igor XOP option also needs the following files in the Igor XOP Library provided by WaveMetrics.

IgorXOP.h, VCExtraIncludes.h, Xop.h, XOPResources.h, XOPStandardHeaders.h, XOPSupport.h, XOPSupportWin.h, XOPWinMacSupport.h, XOPSupport x86.lib, and IGOR.lib.


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3 Control PIXIE-4 Modules via CompactPCI

3.1 Initializing We describe here how to initialize PIXIE-4 modules in a PXI chassis using the functions described in Section 2. As an example, we assume two PIXIE-4 modules – resided in slot #3 and #4, respectively. Users are also encouraged to read the sample C code shipped with the API.

3.1.1 Initialize Global Variables As discussed in Section 2, we assume that three global variable arrays have been defined: System_Parameter_Values, Module_Parameter_Values and Channel_Parameter_Values. For these three global variable arrays, we also need to define three global name arrays: System_Prameter_Names, Module_Parameter_Names and Channel_Parameter_Names, respectively. Table 3.1 lists the names contained in each of these name arrays. The order of placing these names into the name array is not important since the API uses search functions to locate each name at run time. Table 3.1: Contents of Global Name Arrays.

Array Names System_Parameter_Names NUMBER_MODULES, OFFLINE_ANALYSIS,

C_LIBRARY_RELEASE, C_LIBRARY_BUILD, SLOT_WAVE

Module_Parameter_Names MODULE_NUMBER, MODULE_CSRA, MODULE_CSRB, MODULE_FORMAT, MAX_EVENTS, COINCIDENCE_PATTERN, ACTUAL_COINCIDENCE_WAIT, MIN_COINCIDENCE_WAIT, SYNCH_WAIT, IN_SYNCH, RUN_TYPE, FILTER_RANGE, BUFFER_HEAD_LENGTH, EVENT_HEAD_LENGTH, CHANNEL_HEAD_LENGTH, OUTPUT_BUFFER_LENGTH, NUMBER_EVENTS, RUN_TIME, BOARD_VERSION, SERIAL_NUMBER

Channel_Parameter_Names CHANNEL_CSRA, CHANNEL_CSRB, ENERGY_RISETIME, ENERGY_FLATTOP, TRIGGER_RISETIME, TRIGGER_FLATTOP, TRIGGER_THRESHOLD, VGAIN, VOFFSET, TRACE_LENGTH, TRACE_DELAY, PSA_START, PSA_END, EMIN, BINFACTOR, TAU, BLCUT, XDT, BASELINE_PERCENT, CFD_THRESHOLD, INTEGRATOR, LIVE_TIME, INPUT_COUNT_RATE, FAST_PEAKS

Additionally, a string array All_Files containing the file names for the initialization is also needed. Table 3.2 lists the file names needed to initialize the PIXIE-4 modules.


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Table 3.2: File Names in All_Files.

All_Files File Name Note All_Files[0] C:\XIA\PIXIE4\Firmware\syspixie_revB.bin Communication FPGA configurations

(Rev. B) All_Files[1] C:\XIA\PIXIE4\Firmware\syspixie_revC.bin Communication FPGA configurations

(Rev. C) All_Files[2] C:\XIA\PIXIE4\Firmware\pixie.bin Signal processing FPGA configurations All_Files[3] C:\XIA\PIXIE4\DSP\PXIcode.bin DSP executable binary code All_Files[4] C:\XIA\PIXIE4\Configuration\default.set Settings file All_Files[5] C:\XIA\PIXIE4\DSP\PXIcode.var File of DSP I/O variable names All_Files[6] C:\XIA\PIXIE4\DSP\PXIcode.lst File of DSP memory variable names

The global variable array, System_Parameter_Values, also needs to be initialized before the API functions are called to start the initialization. Table 3.3 lists those global variables. Table 3.3: Initialization of Module_Global_Values.

Module_Global_Names Module_Global_Values Note NUMBER_MODULES 2 The total number of PIXIE-4 modules SLOT_WAVE[0] 3 Module 0 sits in slot 3 SLOT_WAVE[1] 4 Module 1 sits in slot 4

3.1.2 Boot PIXIE Modules The boot procedure for PIXIE-4 modules includes the following steps. First, all the global parameter names and boot file names should be downloaded by calling Pixie_Hand_Down_Names. Then function Pixie_User_Par_IO should be called to initialize the global value array System_Parameter_Values. Finally, function Pixie_Boot_System should be called to boot the modules. The following code is an example showing how to boot the PIXIE-4 modules using the API functions.

An Example Code Illustrating How to Boot PIXIE-4 Modules

S32 retval; U8 direction, modnum, channum; // initialize system parameter values System_Parameter_Values[NUMBER_MODULES_Index] = 2; System_Parameter_Values[OFFLINE_ANALYSIS_Index] = 0; System_Parameter_Values[SLOT_WAVE_Index] = 3; System_Parameter_Values[SLOT_WAVE_Index+1] = 4; retval = Pixie_Hand_Down_Names(System_Parameter_Names, "SYSTEM"); if( retval < 0 )

// Error handling retval = Pixie_Hand_Down_Names(Module_Parameter_Names, "MODULE"); if( retval < 0 )


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// Error handling

retval = Pixie_Hand_Down_Names(Channel_Parameter_Names, "CHANNEL"); if( retval < 0 )

// Error handling retval = Pixie_Hand_Down_Names(All_Files, "ALL_FILES"); if( retval < 0 )

// Error handling direction = 0; // download modnum = 0; // Module #0 channum = 0; // Channel #0 retval = Pixie_User_Par_IO(System_Parameter_Values, "NUMBER_MODULES",

"SYSTEM", direction, modnum, channum); if( retval < 0 )

// Error handling retval = Pixie_User_Par_IO(System_Parameter_Values, "OFFLINE_ANALYSIS", "SYSTEM", direction, modnum, channum); if( retval < 0 )

// Error handling retval = Pixie_User_Par_IO(System_Parameter_Values, "SLOT_WAVE", "SYSTEM", direction, modnum, channum); if( retval < 0 )

// Error handling // boot PIXIE-4 modules retval = Pixie_Boot_System(0x1F); if( retval < 0 )

// Error handling // set current module and channel number Pixie_Set_Current_ModChan(0, 0);


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3.2 Setting DSP variables The host computer communicates with the DSP by setting and reading a set of variables called DSP I/O variables. These variables, totally 416 unsigned 16-bit integers, sit in the first 416 words of the data memory. The first 256 words, which store input variables, are both readable and writeable, while the remaining 160 words, which store pointers to various data buffers and run summary data, are only readable. The exact location of any particular variable in the DSP code will vary from one code version to another. To facilitate writing robust user code, we provide a reference table of variable names and addresses with each DSP code version. Included with your software distribution is a file called PXIcode.var. It contains a two-column list of variable names and their respective addresses. Thus you can write your code such that it addresses the DSP variables by name, rather than by fixed location. It should come as no surprise that many of the DSP variables have meaningful values and ranges depending on the values of other variables. A complete description of all interdependencies can be found in Section 4. All of these interdependencies have been taken care of by the PIXIE-4 API. So instead of directly setting DSP variables, users only need to set the values of those global variables defined in Table 3.1. The API will then convert these values into corresponding DSP variable values and download them into the DSP data memory. On the other hand, if users want to read out the data memory, the API will first convert these DSP values into the global variable values. The code shown below is an example of setting DSP variables through the API.

An Example Code Illustrating How to Set DSP Variables through the API

S32 retval; U8 direction, modnum, channum; direction = 0; // download modnum = 0; // Module #0 channum = 0; // Channel #0 // set COINCIDENCE_PATTERN to 0xFFFF Module_Parameter_Values[COINCIDENCE_PATTERN_Index] = 0xFFFF; // download COINCIDENCE_PATTERN to the DSP retval = Pixie_User_Par_IO(Module_Parameter_Values,

“COINCIDENCE_PATTERN", "MODULE", direction, modnum, channum); if( retval < 0 )

// Error handling // set ENERGY_RISETIME to 6.0 µs Channel_Parameter_Values[ENERGY_RISETIME_Index] = 6.0; // download ENERGY_RISETIME to the DSP retval = Pixie_User_Par_IO(Channel_Parameter_Values,


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“ENERGY_RISETIME", "CHANNEL", direction, modnum, channum); if( retval < 0 )

// Error handling

Table 3.5 gives a complete description of all the global variables being used by the PIXIE-4 API. Table 3.5: Descriptions of Global Variables in PIXIE-4.

System_Parameter_Names I/O Type Unit Corresponding DSP Variables NUMBER_MODULES Read/Write N/A N/A OFFLINE_ANALYSIS Read/Write N/A N/A C_LIBRARY_RELEASE Read only N/A N/A C_LIBRARY_BUILD Read only N/A N/A SLOT_WAVE Read/Write N/A N/A Module_Parameter_Names I/O Type Unit Corresponding DSP Variables MODULE_NUMBER Read only N/A MODNUM MODULE_CSRA Read/Write N/A MODCSRA MODULE_CSRB Read/Write N/A MODCSRB MODULE_FORMAT Read/Write N/A MODFORMAT MAX_EVENTS Read/Write N/A MAXEVENTS COINCIDENCE_PATTERN Read/Write N/A COINCPATTERN ACTUAL_COINCIDENCE_WAIT Read/Write N/A COINCWAIT MIN_COINCIDENCE_WAIT Read only N/A COINCWAIT SYNCH_WAIT Read/Write N/A SYNCHWAIT IN_SYNCH Read/Write N/A INSYNCH RUN_TYPE Write only N/A RUNTASK FILTER_RANGE Read/Write N/A FILTERRANGE BUFFER_HEAD_LENGTH Read only N/A BUFHEADLEN EVENT_HEAD_LENGTH Read only N/A EVENTHEADLEN CHANNEL_HEAD_LENGTH Read only N/A CHANHEADLEN OUTPUT_BUFFER_LENGTH Read only N/A LOUTBUFFER NUMBER_EVENTS Read only N/A NUMEVENTSA, NUMEVENTSB RUN_TIME Read only s RUNTIMEA, RUNTIMEB,

RUNTIMEC BOARD_VERSION Read only N/A N/A SERIAL_NUMBER Read only N/A N/A Channel_Parameter_Names I/O Type Unit Corresponding DSP Variables CHANNEL_CSRA Read/Write N/A CHANCSRA CHANNEL_CSRB Read/Write N/A CHANCSRB ENERGY_RISETIME Read/Write µs SLOWLENGTH ENERGY_FLATTOP Read/Write µs SLOWGAP TRIGGER_RISETIME Read/Write µs FASTLENGTH TRIGGER_FLATTOP Read/Write µs FASTGAP TRIGGER_THRESHOLD Read/Write N/A FASTTHRESH VGAIN Read/Write V/V GAINDAC


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VOFFSET Read/Write V TRACKDAC TRACE_LENGTH Read/Write µs TRACELENGTH TRACE_DELAY Read/Write µs TRIGGERDELAY PSA_START Read/Write µs PSAOFFSET PSA_END Read/Write µs PSALENGTH EMIN Read/Write N/A ENERGYLOW BINFACTOR Read/Write N/A LOG2EBIN TAU Read/Write µs PREAMPTAUA, PREAMPTAUB BLCUT Read/Write N/A BLCUT XDT Read/Write N/A XWAIT BASELINE_PERCENT Read/Write N/A BASELINEPERCENT CFD_THRESHOLD Read/Write N/A CFDTHR INTEGRATOR Read/Write N/A FTPWIDTH LIVE_TIME Read only s LIVETIMEA, LIVETIMEB,

LIVETIMEC INPUT_COUNT_RATE Read only cps FASTPEAKSA, FASTPEAKSB,

FASTPEAKSC, LIVETIMEA, LIVETIMEB, LIVETIMEC

FAST_PEAKS Read only N/A FASTPEAKSA, FASTPEAKSB, FASTPEAKSC

3.3 Access spectrum memory or list mode data

3.3.1 Access spectrum memory The MCA spectrum memory is fixed to 32K words (32 bits per word) per channel, residing in the external memory. Therefore, the starting address of the MCA spectrum in the external memory for Channel #0, 1, 2 and 3 will be 0x00000000, 0x000080000, 0x00010000, 0x00018000, respectively. The reading-out of the spectrum memory to the host is through the PCI burst read at rates over 100 Mbytes/s. The spectrum memory is accessible even when a data acquisition run is in progress. The following code is an example of how to start a MCA run and read out the MCA spectrum after the run is finished.

An Example Code Illustrating How to Access MCA Spectrum Memory

S32 retval; U8 direction, modnum, channum; U32 User_Data[131072]; // an array for holding the MCA spectrum data of

// 4 channels direction = 0; // download modnum = 0; // Module #0 channum = 0; // Channel #0 // start a MCA run retval = Pixie_Acquire_Data(0x1301, User_Data, “ ”, modnum); if( retval < 0 )

// Error handling


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// wait for 30 seconds Sleep(30000); // stop the MCA run retval = Pixie_Acquire_Data(0x3301, User_Data, “ ”, modnum); if( retval < 0 )

// Error handling // save MCA spectrum to a file retval = Pixie_Acquire_Data(0x5301, User_Data, “C:\\XIA\\Pixie4\\MCA\Data0001.bin”, modnum); if( retval < 0 )

// Error handling // read out the MCA spectrum and put it to array User_data retval = Pixie_Acquire_Data(0x9001, User_data, “ ”, modnum); if( retval < 0 )

// Error handling

3.3.2 Access list mode data The list mode data in the linear output data buffer can be written in a number of formats. User code should access the three variables BUFHEADLEN, EVENTHEADLEN, and CHANHEADLEN in the configuration file of a particular run to navigate through the data set. There are two data buffers to choose from: the DSP’s local I/O buffer (8K 16-bit words), and section of the external memory (128K 32-bit words). The target data buffer is selected by setting bit 1 in the variable MODCSRA. If the external buffer is chosen to hold the output data, the local buffer is transferred to the external memory when it has been filled. Then the run resumes automatically, without interference from the host, until 32 local buffers have been transferred. The data can then be read from external memory in a fast block read starting from location 0x00020000. If the local buffer is chosen, the run stops when the local buffer is filled. The data has to be read out from local memory. With any data buffer, you can do any number of runs in a row. The first run would be started as a NEW run. This clears all histograms and run statistics in the memory. Once the data has been read out, you can RESUME running. Each RESUME run will acquire another either 32


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or 1 8K buffers of data, depending on which buffer has been chosen. In a RESUME run the histogram memory is kept intact and you can accumulate spectra over many runs. The example code shown below illustrates this.

An Example Code Illustrating How to Access List Mode Data

S32 retval; U8 direction, modnum, channum; U32 User_Data[131072]; // an array for holding the MCA spectrum data of

// 4 channels U16 k, Nruns; char *DataFile = "C:\\XIA\\PIXIE4\\PulseShape\\Data.bin"; direction = 0; // download modnum = 0; // Module #0 channum = 0; // Channel #0 Nruns = 10; // 10 repeated list mode runs k = 0; // initialize counter // start a general list mode run retval = Pixie_Acquire_Data(0x1100, User_Data, “ ”, modnum); if( retval < 0 )

// Error handling do

// wait until run has ended while( ! Pixie_Acquire_Data(0x4100, User_Data, “ ”, modnum) ) ; // read out the list mode data and save it to a file retval = Pixie_Acquire_Data(0x6100, User_Data, DataFile, modnum); if( retval < 0 )

// Error handling k ++; if(k > Nruns)

break; // issue RESUME RUN command retval = Pixie_Acquire_Data(0x2100, User_Data, “ ”, modnum); if( retval < 0 )

// Error handling

while(1); // read out the MCA spectrum and put it to array User_Data retval = Pixie_Acquire_Data(0x9001, User_Data, “ ”, modnum);


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if( retval < 0 )

// Error handling

To process the list mode data after it is saved to a file, the PIXIE-4 API provides several utility routines to parse the list mode data and read out the waveform, energy of each individual trace or PSA values. The code below shows how to read waveforms from a list mode file.

An Example Code Illustrating How to Parse List Mode Data

S32 retval; U8 direction, modnum, channum, i; U32 List_Data[2* MAX_NUMBER_OF_MODULES]; // list mode trace information char *DataFile = "C:\\XIA\\PIXIE4\\PulseShape\\Data.bin"; U32 totaltraces; // total number of traces in the list mode data file U32 *traceposlen; // point to positions of the traces in the file U16 *Trace0; // point to the first trace in the file direction = 0; // download modnum = 0; // Module #0 channum = 0; // Channel #0 // start a general list mode run retval = Pixie_Acquire_Data(0x1100, List_Data, “ ”, modnum); if( retval < 0 )

// Error handling // wait until run has ended while( ! Pixie_Acquire_Data(0x4100, List_Data, “ ”, modnum) ) ; // read out the list mode data and save it to a file retval = Pixie_Acquire_Data(0x6100, List_Data, DataFile, modnum); if( retval < 0 )

// Error handling // parse list mode file retval = Pixie_Acquire_Data(0x7001, List_Data, DataFile, modnum); if( retval < 0 )

// Error handling totaltraces = 0; for(i=0; i<MAX_NUMBER_OF_MODULES; i++) // sum the total number of traces for all modules totaltraces += List_Data[i+ MAX_NUMBER_OF_MODULES];


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// allocate memory to hold the starting address, trace length, and // energy of each trace (therefore, 3 32-bit words are needed for each // trace.) traceposlen = (U32)malloc(totaltraces*3*NUMBER_OF_CHANNELS); if(traceposlen == NULL)

// Error handling // locate traces in the data file retval = Pixie_Acquire_Data(0x7002, traceposlen, DataFile, modnum); if( retval < 0 )

// Error handling // allocate memory to hold the first trace; 2 extra 16-bit words for // notifying the API the trace position and length information Trace0 = (U16)malloc(traceposlen[1]+2); if(Trace0 == NULL)

// Error handling Trace0[0] = traceposlen[0]; // position of the first trace Trace0[1] = traceposlen[1]; // length of the first trace // read out the first trace and put it into trace0 retval = Pixie_Acquire_Data(0x7003, trace0, DataFile, modnum); if( retval < 0 )

// Error handling


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4 User Accessible Variables User parameters are stored in the data memory space of the on-board DSP. The organization is that of a linear memory with 16-bit words. Subsequent memory locations are indicated by increasing addresses. The data memory space, as seen by the host computer, starts at 0x4000. There are two sets of user-accessible parameters. 256 words in data memory are used to store input parameters. These can and must be set properly by the user application. A second set of 160 words is used for results furnished by the PIXIE-4 module. These should not be overwritten. As of this writing the start address for the input parameter block is InParAddr=0x4000 and for the output parameter block it is OutParAddr=0x4100, i.e. the two blocks are contiguous in memory space. We provide an ASCII file named PXIcode.var which contains in a 2-column format the offset and name of every user accessible variable. We suggest that user code use this information to create a name address lookup table, rather than relying on the parameters retaining their address offsets with respect to the start address. The input parameter block is partitioned into 5 subunits. The first contains 64 data that pertain to the PIXIE-4 as a whole. It is followed by four blocks of 48 words, which describe the settings of the four channels. Below we describe the module and channel parameters in turn. Where appropriate, we show how a variable can be viewed using the PIXIE-Viewer.

4.1 Module parameters MODNUM: Logical number of the module. This number will be written into the header of

the list mode buffer to aid offline event reconstruction.

MODCSRA: The Module Control an Status Register A

Bit 0: Reserved. Bit 1: If set, DSP acquires 32 data buffers in each list mode run and stores the data

in external memory. If not set, only one buffer is acquired and the data is kept in local memory.

Bit 2: If set, connect module trigger lines to backplane. Triggers will be shared with

other modules. If not set, triggers are distributed only between channels of this module, depending on channel settings.

Bits 3-15: Reserved.


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MODCSRB: Reserved. MODFORMAT: List mode data format descriptor. Currently it is not in use. CHANNUM: The chosen channel number of a Pixie module. Mainly used by the host to set

the designated channel. RUNTASK: This variable tells the Pixie-4 what kind of run to start in response to a run

start request. Nine run tasks are currently supported.

RunTask Mode Trace Capture

CHANHEADLEN

0 Slow control run N/A N/A 256 (0x100) Standard list mode Yes 9 257 (0x101) Compressed list mode Yes 9 258 (0x102) Compressed list mode Yes 4 259 (0x103) Compressed list mode Yes 2 512 (0x200) Standard fast list mode No 9 513 (0x201) Compressed fast list mode No 9 514 (0x202) Compressed fast list mode No 4 515 (0x203) Compressed fast list mode No 2 769 (0x301) MCA mode No N/A

RunTask 0 is used to request slow control tasks. These include programming the trigger/filter FPGAs, setting the DACs in the system, transfers to/from the external memory, and calibration tasks. RunTask 256 (0x100) requests a standard list mode run. In this run type all bells and whistles are available. The scope of event processing includes computing energies to 16-bit accuracy, and performing pulse shape analyses for improved energy resolution and better time of arrival measurements. Nine words of results, including time of arrival, energy, XIA pulse shape analysis, user pulse shape analysis, etc. are written into the I/O buffer for each channel. Level-1 buffer is not used in this RunTask. RunTask 257 (0x101) requests a compressed list mode run. Both Level-1 buffer and I/O buffer are used in this RunTask, but no traces are written into the I/O buffer. Nine words of results, including time of arrival, energy, XIA pulse shape analysis, user pulse shape analysis, etc. are written into the I/O buffer for each channel. RunTask 258 (0x102) requests a compressed list mode run. The only difference between RunTask 258 and 257 is that in RunTask 258, only four words of results (time of arrival, energy, XIA pulse shape analysis, user pulse shape analysis) are written into the I/O buffer for each channel.


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RunTask 259 (0x103) requests a compressed list mode run. The only difference between RunTask 259 and 257 is that in RunTask 259, only two words of results (time of arrival and energy) are written into the I/O buffer for each channel. RunTask 512 (0x200) employs the same internal data format as RunTask 256, but omits buffer-full checks and trace capture. The run is stopped when the required number of events (MaxEvents) has been acquired. This run type uses the shortest possible interrupt routine for raw data gathering. Hence, it allows for the shortest time between two logged events. For best results the channel variables PAFLength and TriggerDelay should be set to 1 for all channels involved. Level-1 buffer is not used in this run type. Nine words of results, including time of arrival, energy, XIA pulse shape analysis, user pulse shape analysis, etc. are written into the I/O buffer for each channel. RunTask 513 (0x201) requests a compressed fast list mode run without trace capture. Both Level-1 buffer and I/O buffer are used in this RunTask. Nine words of results, including time of arrival, energy, XIA pulse shape analysis, user pulse shape analysis, etc. are written into the I/O buffer for each channel. RunTask 514 (0x202) requests a compressed fast list mode run. The only difference between RunTask 514 and 513 is that in RunTask 514, only four words of results (time of arrival, energy, XIA pulse shape analysis, user pulse shape analysis) are written into the I/O buffer for each channel. RunTask 515 (0x203) requests a compressed fast list mode run. The only difference between RunTask 515 and 513 is that in RunTask 515, only two words of results (time of arrival and energy) are written into the I/O buffer for each channel. RunTask 769 (0x301) requests a MCA run. The raw data stream is always sent to the level-1 buffer, independent of MODCSRA. The data-gathering interrupt routine fills that buffer with raw data, while the event processing routine removes events after processing. If the interrupt routine finds the level-1 buffer to be full, it will ignore events until there is room again in the buffer. The run will not abort due to buffer-full condition. This run type does not write data to the I/O buffer. The module variable MAXEVENTS should be set to zero, to avoid early run termination due to a MAXEVENTS-exceeded condition. The RunTask can be chosen as the run type in the Run tab of the PIXIE-4 Viewer.

CONTROLTASK: Use this variable to select a control task. Consult the control tasks section of this manual for detailed information. The control task will be launched when you issue a run start command with RUNTASK=0.


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MAXEVENTS: The module ends its run when this number of events has been acquired. In

PIXIE-4 Viewer, MAXEVENTS is automatically calculated when a run mode is chosen from the run type pulldown menu. The calculation is based on the trace lengths set by the user. Set MaxEvents=0 if you want to switch off this feature, e.g., when logging spectra (done automatically in an MCA mode run).

COINCPATTERN: When a PIXIE-4 is operated on its own, the user can request that

certain coincidence/anticoincidence patterns are found for the event to be accepted. With four channels there are 16 different hit patterns, and each can be individually selected or marked for rejection by setting the appropriate bit in the COINCPATTERN mask.

Consider the 4-bit hit pattern 1010. The two 1's indicate that channel 3 (MSB)

and channel 1 have reported a hit. Channels 2 and 0 did not. The 4-bit word reads as 10(decimal). If this hit pattern qualifies as an acceptable event, set bit 10 in the COINCPATTERN to 1. The 16 bit in COINCPATTERN cover all combinations. Setting COINCPATTERN to 0xFFFF causes the Pixie-4 to accept any hit pattern as valid.

In the PIXIE-4 Viewer this variable can be set in the Coincidence Pattern Edit

Panel reachable through the Settings tab by clicking on Edit next to the Coinc. Pattern entry.

COINCWAIT: Duration of the coincidence time window in clock ticks (each clock tick spans 13.3 ns). The actual coincidence window is 26.6 ns wider than the value determined by COINCWAIT. For this feature to work, bit no. 1 of the ChannelCSRA of the involved channels should be cleared. This ensures that the DSP can at the end of the coincidence window suppress further hits reporting by late channels.

In the PIXIE-4 Viewer this bit is set or cleared in line 1 of the Channel CSRA

Edit Panel. The line has the title "Measure individual live time". Make sure it is unchecked, so the DSP globally controls FPGA triggering and live time measurements.

When acquiring long waveforms it may be necessary to delay DSP data

reading to ensure that the FIFOs will contain valid data. Secondly, when using a filter range of 6 in the FPGA, the minimum value for COINCWAIT is larger than 1 in all circumstances. Use the following formula to determine COINCWAIT:

COINCWAIT = Max(PeakSep*2^FilterRange)ch0-ch4 – Min(PeakSep*2^FilterRange)ch0-ch4


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Choose COINCWAIT big enough such that the requirements of all channels in the module are met.

SYNCHWAIT: Controls run start behavior. When set to 0 the module simply starts or resumes a run in response to the corresponding request. When set to 1, one or multi-modules will run synchronously through the backplane. This kind of set up in connection with SyncWait=1 will ensure that the last module ready to actually begin data taking will start the run in all modules. And the first module to end the run will stop the run in all modules. This way it never happens that a multi-Pixie system is only partially active.

INSYNCH: InSynch is an input/output variable. It is used in multi-Pixie systems in which

the modules are driven by a common clock. When InSynch is 1, the module assumes it is in synch with the other modules and no particular action is taken at run start. If this variable is 0, then all system timers are cleared at the beginning of the next data acquisition run (RunTask>0). The timers are reset when the entire system actually starts the run. After run start, InSynch is automatically set to 1.

HOSTIO: A 4 word data block that is used to specify command options. RESUME: Set this variable to 1 to resume a data run; otherwise, set it to 0. Set to 2 before stopping a list mode run prematurely. FILTERRANGE: The energy filter range downloaded from the host to the DSP. It sets the

number of ADC samples (2^FILTERRANGE) to be averaged before entering the filtering logic. The currently supported filer range in the signal processing FPGA includes 1, 2, 3, 4, 5 and 6.

U00: Many unused, but reserved, data blocks have names of the structure Unn.

Those unused data blocks which reside in the block of input parameters for each channel are called UNUSEDA and UNUSEDB.

XdatLength: Length of a data block to be downloaded from the host. Use XdatLength=0 as

the default value for normal operation.

USERIN: A block of 16 input variables used by user-written DSP code.

4.2 Channel variables All channel-0 variables end with "0", channel-1 variables end with "1", etc. In the following explanations the numerical suffix has been removed. Thus, e.g., CHANCSRA0 becomes CHANCSRA, etc.


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CHANCSRA: The control and status register bits switch on/off various aspects of the PIXIE-4 operation, see the Channel CSRA Edit Panel reachable through the Settings tab of the PIXIE-4 Viewer. In general, setting the bit activates the option in question.

Bit 0: Respond to group triggers only. Set this bit if you want to control the waveform acquisition for non-triggering channels by a triggering master channel. For this option to work properly choose one channel as the master and have its Trigger_Enable bit set. All dependent channels should have their Trigger_Enable bit cleared. Set bit 0 in all slave channels. You should also set it the master channel to ensure equal time of arrivals for the fast trigger signal, which is used to halt the FIFOs. Note: To distribute group triggers between modules, bit 2 in the variable MODCSRA has to be set as well.

Bit 1: Measure individual live time. Keep this bit cleared when operating with master and slave channels, or when making coincidence measurements using single modules. Set this bit when measuring independent spectra, i.e., when list mode data are not required.

Bit 2: Good channel. Only channels marked as good will contribute to spectra and list mode data.

Bit 3: Read always Channels marked as such will contribute to list mode data, even if they did not report a hit. This is most useful when acquiring induced signal waveforms on spectator electrodes, i.e., electrodes that did not collect any net charge, but only saw a transient induced signal.

Bit 4: Enable trigger. Set this bit for channels that are supposed to contribute to an event trigger.

Bit 5: Trigger positive. Set this bit to trigger on a positive slope; clear it for triggering on a negative slope. The trigger/filter FPGA can only handle positive signals. The PIXIE handles negative signals by inverting them immediately after entering the FPGA.

Bit 6: GFLT. Set this bit if you want to validate or veto events using the PXI backplane. When the bit is cleared, the GFLT input is ignored. When set, the event is accepted only if validated. To be validated, the GFLT input must be a logic 0 no later than an energy filter rise time after the signal arrival, and must remain at logic 0 level until a rise time + flat top after signal arrival.


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Bit 7: Histogram energies. Set this bit to histogram energies from this channel in the on-board MCA memory.

Bit 8: Reserved. Set to 0.

Bit 9: Reserved.

Bit 10: Compute constant fraction timing. This pulse shape analysis computes the time of arrival for the signal from the recorded waveform. The result is stated in units of 1/256th of a sampling period (13.3 ns). Time zero is the start of the waveform.

Bit 11..15: Reserved. CHANCSRB: Control and status register B. Bit 0: If set, call user written DSP code.

Bit 1: If set, all words in the channel header except Ndata, trigtime and energy will be overwritten with the contents of URETVAL. Depending on the run type, this allows for 6, 2 or 0 user return values in the channel header.

Bit2..15: are reserved. Set to 0.

The following two data words are used to set the on-board DACs for this channel. Once a new variable has been written to DSP memory the DACs have to be reprogrammed by starting a run with RunTask=0 and ControlTask=0. GAINDAC: Reserved and not supported. TRACKDAC: This DAC determines the DC-offset voltage. The offset can be calculated

using the following formula: Offset [V] = 2.5 * ((32768 - TRACKDAC) / 32768)

SGA: The index of the relay combinations of the switchable gain amplifier. DIGGAIN: The digital gain factor for compensating the difference between the user-

desired voltage gain and the SGA gain. UNUSEDA0 or UNUSEDA1: Reserved. The following block of data contains trigger/filter FPGA data. Once a new variable has been written to DSP memory it has to be activated by starting a run with RunTask 0 (Set DACs)


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and ControlTask 5 (Program FiPPI). SLOWLENGTH: The rise time of the energy filter depends on SlowLength:

RiseTime = SlowLength * 2^FilterRange * 13.3 ns

SLOWGAP: The flat top of the energy filter depends on SlowGap: FlatTop = SlowGap * 2^FilterRange * 13.3 ns. There is a constraint concerning the sum value of the two parameters: SlowLength + SlowGap < 127

FASTLENGTH: The rise time of the trigger filter depends on FastLength: RiseTime = FastLength * 13.3 ns. Note the constraint: FastLength < 32

FASTGAP: The flat top of the trigger filter depends on FastGap: FlatTop = FastGap * 13.3 ns. There is a constraint concerning the sum value of the two parameters: FastLength + FastGap < 32

PEAKSAMPLE: This variable determines at what time the value from the energy filter

will be sampled. Note that the following formulae depend on the filter range: Filter Range = 0: PeakSample = max(0, SlowLength + Slow Gap – 7) Filter Range = 1: PeakSample = max(2, SlowLength + Slow Gap – 4) Filter Range = 2: PeakSample = SlowLength + Slow Gap – 2 Filter Range >= 3: PeakSample = SlowLength + Slow Gap – 1 If the sampling point is chosen poorly, the resulting spectrum will show energy resolutions of 10% and wider rather than the expected fraction of a percent. For some parameter combinations PeakSample needs to be varied by one or two units in either direction, due to the pipelined architecture of the trigger/filter FPGA.

PEAKSEP: This value governs the minimum time separation between two pulses. Two

pulses that arrive within a time span shorter than determined by PeakSep will be rejected as piled up. The recommended value is: PeakSep = PeakSample+5


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If PeakSep>33, PeakSep=PeakSample+1

Note the constraint: 0 < PeakSep - PeakSample < 7

FASTADCTHR: Reserved. FASTTHRESH: This is the trigger threshold used by the trigger/filter FPGA. The value

relates to a trigger threshold through the formula: FASTTHRESH = TriggerThreshold * FASTLENGTH The TriggerThreshold can be set on the Settings tab of the PIXIE-4 Viewer.

MINWIDTH: Unused. MAXWIDTH: This value aids the pile up inspector. MaxWidth is the maximum duration,

in sample clock ticks (13.3 ns), which the output from the fast filter may spend over threshold. Pulses longer than that will be rejected as piled up. The recommended setting is MaxWidth = FastLength + FastGap + SignalRiseTime/13.3 ns. Note the constraint MaxWidth < 256 Setting Maxwidth=0 switches this part of the pile up inspector off. Indeed it is recommended to begin with MaxWidth=0. Once the other parameters have been optimized, one can use the MaxWidth cut to improve the pile up rejection at high count rates. Maxwidth should be tuned by observing the main energy peak in the spectrum for fixed time intervals. Once the MaxWidth cut is too tight there will be a loss of efficiency in the main peak. Setting MaxWidth to such a value that the efficiency loss in the main peak is acceptable will give the best overall performance in terms of efficiency and pile up rejection.

PAFLENGTH: A FIFO control variable that needs to be written into the trigger/ filter FPGA. Using the programmable almost-full register we can time the waveform capturing thus that by the time the DSP is triggered at the end of the pile up inspection period the data of interest have percolated through to the begin of the FIFO and are available for read out without delay. The acquired waveform will start rising from the baseline at a time delay after the beginning of the trace. This delay is a quantity that the user will want to set. In the PIXIE-4 Viewer it is called TraceDelay (measured in microseconds) and is available through the Settings tab. The recommended setting for PafLength is:


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PafLength = TriggerDelay + TraceDelay/13.3ns Note the constraint: PafLength < 4092. Note that PAFLength should be adjusted only in multiples of 4, as the hardware ignores the lower two bits of this value.

TRIGGERDELAY: This is a partner variable to PafLength. For all filter ranges,

TriggerDelay = (PeakSep -1)*2^(FilterRange)

Note that TriggerDelay should be adjusted only in multiples of 4, as the hardware ignores the lower two bits of this value. For MCA runs without taking traces, (trace length=0), TriggerDelay should be 1.

RESETDELAY: This variable controls the restarting of the FIFO after it was halted to read

the waveform. When triggers are distributed across channels and modules, a halted FIFO is automatically restarted if the trigger/filter FPGA does not receive the distributed event trigger within RESETDELAY 13.3ns clock ticks after the internal event trigger. The default value written by the PIXIE module should not be changed by the user.

FTPWIDTH: Unused. This completes the list of values that control the trigger/filter FPGAs. The following input parameters are used by the DSP program. They become active as soon as the first data taking run has been started. Only then will the output parameters reflect the changes made to the set of input parameters. TRACELENGTH: This tells the DSP how many words of trace data to read. The action

taken depends on FIFOlength , which is 1024. If TraceLength < FIFOlength, the DSP will read from the FIFO. In that case individual samples are 13.3 ns apart. If FIFOlength <= TraceLength, the PIXIE-4 code will force the TraceLength to be equal to FIFOlength.

XWAIT: Extra wait states. This parameter controls how many extra clock cycles the DSP waits when reading waveform data in real time rather than out of a FIFO memory. This occurs when acquiring data in list mode and asking for trace lengths longer than FIFOlength. The time between recorded samples is

∆T = (3+XWAIT)*13.3ns.

XWAIT is used differently when acquiring untriggered traces in a control run with ControlTask=4. In this case, the time between recorded samples is


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∆T = 4*13.3ns if XWAIT <= 4;

XWAIT*13.3ns if 4 < XWAIT <= 12; (3 + XWAIT )*13.3ns if XWAIT > 13 (XWAIT has to be multiple of 5) The following variables affect internal MCA histogramming of the PIXIE-4 module. ENERGYLOW: Start energy histogram at ENERGYLOW. Only applies to list mode runs. LOG2EBIN: This variable controls the binning of the histogram. Energy values are

calculated to 16 bits precision. The LSB corresponds to 1/4th of a 14-bit ADC. The PIXIEs, however, do not have enough histogram memory available to record 64k spectra, nor would this always be desirable. The user is therefore free to choose a lower cutoff for the spectrum (EnergyLow) and control the binning. Observe the following formula to find to which MCA bin a value of Energy will contribute: MCAbin = (Energy-EnergyLow) * 2^Log2Ebin As can be seen, Log2Ebin should be a negative number to achieve the correct behaviour. At run start the DSP program ensures that Log2Ebin is indeed negative by replacing the stored value by -abs(Log2Ebin). The histogramming routine of the DSP takes care of spectrum overflows and underflows.

CFDTHR: This sets the threshold of the software constant fraction discriminator. The threshold fraction (f) is encoded as Round(f*65536), with 0<f<1.

PSAOFFSET: PSALENGTH: When recording traces and requiring any pulse shape analysis by the DSP,

these two parameters govern the range over which the analysis will be applied. The analysis begins at a point PSAOFFSET sampling clock ticks into the trace, and is applied over a piece of the trace with a total length of PSALENGTH clock ticks.

INTEGRATOR: This variable controls the energy reconstruction in the DSP.

INTEGRATOR == 0: normal trapezoidal filtering INTEGRATOR == 1: use gap sum only; good for scintillator signals INTEGRATOR == 2: ignore gap sum; pulse height=leading sum –

trailing sum; good for step-like pulses. BLCUT: This variable sets the cutoff value for baselines in baseline measurements. If

BLCUT is not set to zero, the DSP checks continuously each baseline value to see if it is outside of the limit set by BLCUT. If the baseline value is within


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the limit, it will be used to calculate the average baseline value. Otherwise, it will be discarded. Set BLCUT to zero to not check baselines, therefore reduce processing time. ControlTask 6 can be used to measure baselines. Host computer can then histogram these baseline values and determine the appropriate value for BLCUT for each channel according to the standard deviation SIGMA for the averaged baseline value. BLCUT could be set to be three times SIGMA.

BASELINEPERCENT: This variable sets the DC-offset level in terms of the percentage

of the ADC range. XAVG: Only used in Controltask 4 for reading untriggered traces. XAVG stores the

weight in the geometric-weight averaging scheme to remove higher frequency signal and noise components. The value is calculated as follows: For a given dt (in µs), calculate the integer intdt = dt/0.0133 If intdt>13, XAVG = floor( 65536/((intdt-3)/5) ) If intdt<=13, XAVG = 65535.

UNUSEDB0 or UNUSEDB1: Reserved.

CFDREG: Reserved for FPGA-based constant fraction discriminator. LOG2BWEIGHT: The PIXIE measures baselines continuously and effectively extracts

DC-offsets from these measurements. The DC-offset value is needed to apply a correction to the computed energies. To reduce the noise contribution from this correction baseline samples are averaged in a geometric weight scheme. The averaging depends on Log2Bweight: DC_avg = DC + (DC_avg-DC) * 2^LOG2BWEIGHT DC is the latest measurement and DC_avg is the average that is continuously being updated. At the beginning, and at the resuming, of a run, DC_avg is seeded with the first available DC measurement. As before, the DSP ensures that LOG2BWEIGHT will be negative. The noise contribution from the DC-offset correction falls with increased averaging. The standard deviation of DC_avg falls in proportion to sqrt(2^LOG2BWEIGHT). When using a BLCUT value from a noise measurement (cf control task 6) the PIXIE will internally adjust the effective Log2Bweight for best energy resolution, up to the maximum value given by LOG2BWEIGHT. Hence, the Log2Bweight setting should be chosen at low count rates (dead time < 10%). Best energy resolutions are typically obtained at values of -3 to -4, and this


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parameter does not need to be adjusted afterwards.

PREAMPTAUA: High word of the preamplifier exponential decay time. PREAMPTAUB: Low word of the above.

The two variables are used to store the preamplifier decay time. The time τ is measured in µs. The two words are computed as follows. PREAMPTAUA = floor(τ) PREAMPTAUB = 65536 * (τ - PreampTauA) To recover τ use: τ = PREAMPTAUA + PREAMPTAUB / 65536

This ends the block of channel input data. Note that there are four equivalent blocks of input channel data, one for each PIXIE-4 input channel. We now show the output variables, again beginning with module variables and continuing afterwards with the channel variables. The output data block begins at the address 0x4100. Note, however, that this address could change. The output data block comprises of 160 words; 1 block of 32 is reserved for module data; 4 blocks of 32 words each hold channel data. REALTIMEA: REALTIMEB: REALTIMEC: The 48-bit real time clock. A,B,C are the high, middle and low word,

respectively. The clock is zeroed on power up, and in response to a synch interrupt when InSynch was set to 0 prior to the run start. This requires the Busy--Synch loop to be closed; see the discussion above. RealTime =(RealTimeA * 65536^2 + RealTimeB * 65536 + RealTimeC) * 13.3ns

RUNTIMEA: RUNTIMEB: RUNTIMEC: The 48-bit run time clock. A,B,C words are as for the RealTime clock. This

time counter is active only while a data acquisition run is in progress. Comparing the run time with the real time allows judging the overhead due to data readout. Compute the run time using the following formula: RunTime =(RunTimeA * 65536^2 + RunTimeB * 65536 + RunTimeC) * 13.3ns

GSLTTIMEA: GSLTTIMEB:


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GSLTTIMEC: Unused.

NUMEVENTSA: NUMEVENTSB: Number of valid events serviced by the DSP.

Again the high word carries the suffix A and the low word the suffix B.

DSPERROR: This variable reports error conditions: = 0 (NOERROR), no error = 1 (RUNTYPEERROR), unsupported RunType = 2 (RAMPDACERROR), Baseline measurement failed SYNCHDONE: This variable can be set to 1 to force the DSP out of an infinite loop caused

by a malfunctioning Busy-Synch loop, when a run start request was issued with SYNCHWAIT=1.

BUFHEADLEN: At the beginning of each run the DSP writes a buffer header to the list mode data buffer. BufHeadLen is the length of that header. Currently, BUFHEADLEN is 6, but this value should not be hardcoded, it should be read from the DSP to ensure upgrade compatibility.

EVENTHEADLEN: For each event in the list mode buffer, or the level-1 buffer, there is an

event header containing time and hit pattern information. EventHeadLen is the length of that header. Currently, EVENTHEADLEN is 3, but this value should not be hardcoded, it should be read from the DSP to ensure upgrade compatibility.

CHANHEADLEN: For each channel that has been read, there is a channel header

containing energy and auxiliary information. ChanHeadLen is the length of this header. CHANHEADLEN varies between 2 and 9 words depending on the run type (see RUNTASK).

The event and channel header lengths plus the requested trace lengths determine the maximum logically possible event size. The maximum event size is the sum of EventHeadLen and the ChannelHeadLengths plus the TraceLengths for all channels marked as good, i.e. which have bit 2 in the ChanCSRA set. Example: With all four channels marked as good and required trace lengths of 1000 (i.e. 13.3µs) the maximum event size will be MaxEventSize = EventHeadLen + 4*(ChanHeadLen + 1000) = 4039 In the last line typical values for EventHeadLen (3) and ChanHeadLen (9) were substituted. BufHeadLen equals 6. Thus there is room for at least 2 events in the list mode data buffer, which is 8192 words long. But there is not enough room in the level-1 buffer, which contains only 2048 words.


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Below follow the addresses and lengths of a number of data buffers used by the DSP program. The addresses are generated by the assembler/linker when creating the executable. On power up the DSP code makes these values accessible to the user. Note that the addresses will typically change with every new compilation. Therefore your code should never assume to find any given buffer at a fixed address. Note that addresses in the DSP data memory fall into the range from 0x4000 to 0x7FFF. The word length in data memory is 16 bit. If an address falls in the range from 0 to 0x3FFF, it points to a location in program memory. Here the word lengths are 24 bits. USEROUT: 16 words of user output data, which may be used by user written DSP code. AOUTBUFFER: Address of the list mode data buffer. LOUTBUFFER: Number of words in the list mode buffer. AECORR: unused, reserved LECORR: unused, reserved.

Formerly address and length of an array containing coefficients for energy calculations. Now these coefficients are calculated in the DSP code from the decay time.

ATCORR: unused, reserved LTCORR: unused, reserved

Formerly address and length of an array containing coefficients for normalization and time of arrival corrections. Now these coefficients are calculated in the DSP code from the decay time.

HARDWAREID: ID of the hardware version HARDVARIANT: Variant of the hardware FIFOLENGTH: Length of the onboard FIFOs, measured in storage locations. FIPPIID: ID of the FiPPI FPGA configuration FIPPIVARIANT: Variant of the FiPPI FPGA configuration INTRFCID: ID of the system FPGA configuration INTRFCVARIANT: Variant of the system FPGA configuration DSPRELEASE: DSP software release number DSPBUILD: DSP software build number

The following channel variables contain run statistics. Again the variable names carry the channel number as a suffix. For example the LIVETIME words for channel 2 are LIVETIMEA2, LIVETIMEB2, LIVETIMEC2. Channel numbers run from 0 to 3.


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LIVETIMEA: LIVETIMEB: LIVETIMEC: Total live time as measured by the trigger/filter FPGA of that channel. It

excludes times during which the FPGA was prevented from sending triggers due to ongoing DSP data reads, or when the run was stopped. Convert the three LiveTime words into a live time using the formula: LiveTime = (LiveTimeA * 65536^2 + LiveTimeB * 65536 + LiveTimeC) * 16*13.3ns

FASTPEAKSA: The number of events detected by the fast filter is: FASTPEAKSB: NumEvents = FASTPEAKSA*65536 + FASTPEAKSB ADCPERDACA: Gain variable. ADCPERDACB: Both words currently unused, but reserved


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5 Control Tasks The DSP can execute a number of control tasks, which are necessary to control hardware blocks that are not directly accessible from the host computer. The most prominent tasks are those to set the DACs, program the trigger/filter FPGAs and read the histogram memory. The following is a list of control tasks that will be of interest to the programmer. To start a control task, set RUNTASK=0 and choose a CONTROLTASK value from the list below. Then start a run by setting bit 0 in the control and status register (CSR). Control tasks respond within a few hundred nanoseconds by setting the RUNACTIVE bit (#13) in the CSR. The host can poll the CSR and watch for the RUNACTIVE bit to be deasserted. All control tasks indicate task completion by clearing this bit. Execution times vary considerably from task to task, ranging from under a microsecond to 10 seconds. Hence, polling the CSR is the most effective way to check for completion of a control task. Control Task 0: SetDACs

Write the GAINDAC and TRACKDAC values of all channels into the respective DACs. Reprogramming the DACs is required to make effective changes in the values of the variables GAINDAC0…3, TRACKDAC0…3.

Control Task 1: Connect inputs

Close the input relay to connect the PIXIE electronics to the input connector.

Control Task 2: Disconnect inputs

Open the input relay to disconnect the PIXIE electronics from the input connector.

Control Task 3: Ramp offset DAC

This is used for calibrating the offset DAC. For each channel the offset DAC is incremented in 2048 equal-size steps. At each DAC setting the DC-offset is determined and written into the list mode buffer. At the end of the task the list mode buffer holds the following data. Its 8192 words are divided up equally amongst the four channels. Data for channel 0 occupy the lowest 2048 words, followed by data for channel 1, etc. The first entry for each channel's data block is for a DAC value of 0, the last entry is for a DAC value of 65504. In between entries the DAC value is incremented in steps of 32. An examination of the results will reveal a linearly rising or falling response of the ADC to the DAC increments. The slope depends on


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the trigger polarity setting, i.e., bit 5 of the channel control and status register A (ChanCSRA). For very low and very big DAC values the ADC will be driven out of range and an unpredictable, but constant response is seen. From the sloped parts a user program can find the DAC value that is necessary for a desired ADC offset. It is recommended, that for unipolar signals an ADC offset of 1638 units is chosen. For bipolar signals, like the induced waveforms from a segmented detector, the ADC offset would be 8192 units, i.e., midway between 0 and 16384. A user program would use the result from the calibration task to find, set and program the correct offset DAC values. Since the offset measurement has to take the preamplifier offset into account, this measurement must be made with the preamplifier connected to the PIXIE-4 input. The control task makes 16 measurements at each DAC step and uses the last computed DC-offset value to enter into the data buffer. Due to electronic noise, it may occasionally happen that none of the sixteen attempts at a base line measurement is successful, in which case a zero is returned. The user software must be able to cope with an occasional deviation from the expected straight line. On exit, the task restores the offset DAC values to the values they had on entry.

ControlTask 4: Untriggered Traces

This task provides ADC values measured on all four channels and gives the user an idea of what the noise and the DC-levels in the system are. This function samples 8192 ADC words for the channel specified in CHANNUM. The XWAIT variable determines the time between successive ADC samples (samples are XWAIT * 13.3ns apart). In the PIXIE-4 Viewer XWAIT can be adjusted through the dT variable in the Oscilloscope panel. The results are written to the 8192 words long I/O buffer. Use this function to check if the offset adjustment was successful. From the PIXIE-4 Viewer this function is available through the Oscilloscope Panel. Hit the Refresh button to start four consecutive runs with ControlTask 4 in the selected module, one for each channel.

ControlTask 5: ProgramFiPPI This task writes all relevant data to the FiPPI control registers.

ControlTask 6: Measure Baselines

This routine is used to collect baseline values. Currently, DSP collects


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six words, B0L, B0H, B1L, B1H, time stamp, and ADC value, for each baseline. 1365 baselines are collected until the 8192-word I/O buffer is almost completely filled. The host computer can then read the I/O buffer and calculate the baseline according to the formula: B1= (B1L+B1H*65536)/2(FILTERRANGE+8) B0= (B0L+B0H*65536)/ 2(FILTERRANGE+8) TAU=PreampTauA+PreampTauB/65536 Baseline=B1-B0*exp(-0.0133*(SlowLength+SlowGap)*2FILTERRANGE/TAU) Baseline values can then be statistically analyzed to determine the standard deviation associated with the averaged baseline value and to set the BLCUT. BLCUT should be about 3 times the standard deviation. Baseline values can also be plotted against time stamp or ADC value to explore the detector performance. BLCUT should be set to zero while running ControlTask 6.

ControlTask 9..23: reserved


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6 Appendix A — User supplied DSP code

6.1 Introduction It is possible for users to enhance the capabilities of the PIXIE-4 by adding their own DSP code. XIA provides an interface on the DSP level and has built support for this into the PIXIE-4 Viewer. The following sections describe the interfaces and support features.

6.2 The development environment For the DSP code development, XIA uses and recommends version 5 or 6 of the assembler and linker distributed by Analog Devices. Both versions are in use at XIA and work fine. It may be inconvenient, but is unavoidable to program the ADSP-2185 on board processor in assembler rather than in a higher level programming language like C. We found that code generated by the C-compiler is bloated and consequently runs very slow. As the main piece of the code could not be written in C at all, we did not burden our design by trying to be compatible with the C-compiler. Hence, using the C-compiler is currently not an option. With the general software distribution we provide working executables and support files. To support user DSP programming we provide files containing pre-assembled forms of XIA’s DSP code, together with a source code file that has templates for the user functions. The user templates have to be converted by the assembler and the whole project is brought together by the linker. XIA provides a link and a make file to assist the process. In the PIXIE-4 Viewer we provide powerful diagnostic tools to aid code developing and a data interface to exchange data between the host and the user code. The PIXIE-4 Viewer can, at any time, examine the complete memory content of the DSP and call any variable from any code section by name. A particularly useful added feature is the capability to download data in native format into the DSP and pretend that they were just acquired. The event processing routine, which calls the user code, is then activated and processes the data. This in-situ code testing allows the most control in the debugging process and is more powerful than having to rely on real signal sources.

6.3 Interfacing user code to XIA’s DSP code When the DSP is booted it launches a general initialization routine to reach a known, and useful, state. As part of this process a routine called UserBegin is executed. It is used to communicate addresses and lengths of buffers, local to the user code, to the host. The host finds this information in the USEROUT[16] buffer described in the main section of this document. The calling of UserBegin is not maskable. All other functions that are part of the user interface will be called only if bit 0 of MODCSRB is set at the time.


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When a run starts, the DSP executes a run start initialization during which it will call UserRunInit. It may be used to prepare data for the event procesing routines. When events are processed by the DSP code it may call user code in two different instances. Events are processed one channel at the time. For each channel with data, UserChannel is called at the end of the processing, but before the energy is histogrammed. UserChannel has access to the energy, the acquired wave form (the trace) and is permitted one return value. This is the routine in which custom pulse shape analysis will be performed. After the entire event, consisting of data from one to four channels, has been processed the function UserEvent may be called. It may be used in applications in which data have to be correlated across channels. At the end of a run the closing routine may call UserRunFinish, typically for updating statistics and similar run end tasks. The above mentioned routines are described below, including the interface variables and the permissible use of resources.

6.4 The interface The interface consists of five routines and a number of global variables. Data exchange with the host computer is achieved via two data arrays that are part of the I/O parameter blocks visible to the host. The total amount of memory available to the user comprises 2048 instructions and 1000 data words. Host interface as supported by the PIXIE-Viewer: UserIn[16] 16 words of input data UserOut[16] 16 words of output data Interface DSP routines: UserBegin: This routine is called after rebooting the DSP. Its purpose is to establish values for variables that need to be known before the first run may start. Address pointers to data buffers established by the user are an example. The host will need to know where to write essential data to before starting a run. Since the DSP program comes up in a default state after rebooting UserBegin will always be called. This is different for the routines listed below, which will only be called if for at least one channel bit 0 of ChannelCSRB has been set.


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UserRunInit: This function is called at each run start, for new runs as well as for resumed runs. The purpose is to precompute often needed variables and pointers here and make them available to the routines that are being called on an event-by-event basis. The variables in question would be those that depend on settings that may change in between runs. UserChannel: This function is called for every event and every PIXIE-4 channel for which data are reported and for which bit 0 of the channel CSR_B (ChannelCSRB variable) has been set. It is called after all regular event processing for this channel has finished, but before the energy has been histogrammed. UserEvent: This function is called after all event processing for this particular event has finished. It may be used as an event finish routine, or for purposes where the event as a whole is to be examined. UserRunFinish: This routine is called after the run has ended, but before the host computer is notified of that fact. Its purpose is to update run summary information. Global variables: UserIn[16] 16 words of input data, also visible to host UserOut[16] 16 words of output data, also visible to host When entering UserChannel the following globals have been set by the DSP:

Atstart Address of 1st word of the ADC trace Tlen Length of the ADC trace Energy Pulse height of the event ChanNum Current channel number RUNTASK RUNTASK of the current run E0L lagging Energy filter, low word E0H lagging Energy filter, high word E1L leading Energy filter, low word E1H leading Energy filter, high word

Your return value is UretVal. It is an array of 6 words. If bit 1 of ChanCSRB is 0, only the first word is incorporated into the output data stream by the main code. See Tables 2 to 6 in the user manual for the output data structure. If the bit is 1, up to six values are incorporated, overwriting the XIA PSA value, the USER PSA value, and the reserved word in the channel header. If the run type compresses the standard nine channel header words, the number of user return values is reduced accordingly (i.e only 2 words are available in RunTask 0x102 or 0x202, and no words in RunTask 0x103 or 0x203).


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When entering UserChannel or UserEvent the address register I5 will point to the start of the current event. Register usage: The user routines may use all computational registers without having to restore them. However, the secondary register set cannot be used, because the XIA interrupt routines use these. The usage of the address registers I0..I7 and the associate registers M0..M7, and L0..L7 is subject to restrictions. These are listed below for the various routines. The associate registers L,M are preset and guaranteed as follows:

L0..L7 = 0 M0 = 0; M1 = 1; M2 = -1; M4 = 0; M5 = 1; M6 = -1; M3 and M7 have no guaranteed values.

UserBegin, UserRunInit, and UserRunFinish: No further restrictions, but user code must leave the associated registers listed above in exactly this state when exiting. UserChannel: I5,I6,I7 L5,L6, M0,M1,M2,M4,M5,M6

These registers may not even temporarily be overwritten, because there are interrupt functions, which depend on the contents of these registers.

I0,I1,I3,I4 L0,L1,L2,L3,L4,L7

These registers may be altered, but must be restored on exit.

I2 M3,M7

These registers may be altered and need not be restored

UserEvent: I5,I6,I7 L5,L6, M0,M1,M2,M4,M5,M6

These registers may not even temporarily be overwritten, because there are interrupt functions, which depend on the contents of these registers.

I4 L0,L1,L2,L3,L4,L7

These registers may be altered, but must be restored on exit.

I0,I1,I2,I3 M3,M7

These registers may be altered and need not be restored


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6.5 Debugging tools Besides the debugging tools that are accessible through the PIXIE-4 Viewer, it is also possible to download data into the PIXIE data buffers and call the event processing routine. This allows for an in-situ test of the newly written code and allows exploring the valid parameter space systematically or through a Monte Carlo from the host computer. For this to work the module has to halt the background activity of continuous base line measuring. Next, data have to be downloaded and the event processing started. When done the host can read the results from the known address. The process is fairly simple. The host writes the length of the data block that is to be downloaded into the variable XDATLENGTH. Then the data are written to the linear output buffer, the address and length of which are given in the variables AOUTBUFFER and LOUTBUFFER. Next the user starts a data run, and reads the results after the run has ended.

PIXIE-4 Online Help Version 1.20, August 2004





PIXIE-4 Online- Help V1.20 XIA 2004. All rights reserved.

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• Getting Help for the Pixie-4 There are several ways to get help for the Pixie-4. You can use IGOR's built-in help browser to access the Pixie-4 specific help file by selecting Help -> Help Topics from the top menu bar. Choose "Pixie4-Help" in the popup menu on the left, and select the appropriate help topic from the list on the right. Each Pixie-4 Run Control Panel also has a "Help" button, which directly displays the help topic for that panel. In the help topics, click on blue underlined links to jump to cross references.

• Getting Started Preparations 1. Install Wavemetrics IGOR Pro. 2. Install the Pixie-4 software from XIA (see file readme.txt on CD-ROM). 3. Install the Pixie-4 modules and system controller in the PXI/CompactPCI crate with power switched

off. Connect detector signals to the Pixie-4 modules using the cables supplied by XIA. Then Switch on power of the chassis.

4. After the controller booted, find Pixie4.pxp in the installed folder and double-click it to open the

Pixie-4 Viewer. Initial Startup When the Pixie-4 Viewer has been loaded, the Pixie Start Up Panel should be prominently displayed in the middle of the desktop. It will prompt you to do the following: Specify the Pixie-4 modules:

First select the number of Pixie-4 modules in the system. Then specify the PXI slot number in which each module resides. Then click "Start Up System". In the IGOR history window, a message will show if the modules have been initialized successfully. You will now see the main Pixie Control Panel from which all work is conducted. The tabs in the Control Panel are arranged in logical order from left to right. For most of the actions the Pixie-4 Viewer interacts with one Pixie-4 module at a time. The number of that module is displayed at the top right corner of the Control Panel (inside the "Module" control). Next to the “Module” control is the “Channel” control which specifies the current channel the Pixie-4 viewer is interacting with. The "Module" and the “Channel” are the target for all actions executed from the Viewer. Proceed with the steps below to configure your system.

1. In the Calibrate tab, click on the Oscilloscope button.

This opens a graph that shows the untriggered signal input. Click "Refresh" to update the display. The pulses should fall between about 1600 and 15000 on the left axis. If no pulses are visible or if they are cut off above 16384 or below 0, click "Adjust Offsets" to automatically set the DC offset. There is a control called “Baseline [%]” on the Oscilloscope which can be used to adjust the DC offset for each channel. If the pulse amplitude is too large to fall in the display range, decrease the "Gain" in the Calibrate tab of the Pixie-4 Control Panel. Since the offsets might drift, for example after changes in input count rate, it is useful to leave the display open and check the offsets once in a while.

2. In the Calibrate tab, input an estimated preamplifier RC decay time for Tau in µs then click on "Auto


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Find" to determine the actual Tau value for the current channel of the current module. Repeat this for other channels if necessary. The Tau finder works best for a Tau value from 20 µs to 200 µs.

3. In the Settings tab, click on "Save" to save the system parameters found so far. You can save the

settings into either an existing settings file or a new file. 4. Click on the Run tab, set "Run Type" to 0x301 MCA Mode, “Polling time” to 1 second, and “Run

time/time out” to 30 seconds or so, then click "Start Run". After the run is complete, select the Analyze tab and click on the “MCA Spectrum” button. The MCA spectrum shows the MCA histograms for all four channels. You can deselect other channels while working on only one channel. You can do a Gauss fit on a peak by entering values in the "Min" and "Max" fields as the limits for a Gauss fit. You can also use the mouse to drag the Cursor A and B in the MCA spectrum to the limits of the fit. Enter the true energy value in the "Peak" field to calibrate the energy scale. If you are not getting a nice-looking spectrum, you may need to adjust some settings such as filter rise time and flat top etc. Refer to the User’s Manual for details.

• Pixie-4 Control Panel The Main Control Panel is displayed on the desktop after starting the IGOR experiment file "Pixie4.pxp". Using the four control tabs, arranged in logical order from left to right, you can set up the system, set run parameters, take data, and view the results. Control Tabs: Settings Calibrate Run Analyze It also has four buttons on the bottom of the panel: "Start System", "More", "Help", and "About" "Start System" can be used to re-initialize the modules "More" will show additional controls on the control panel "Help" will open this help file, at the entry corresponding to the currently active tab "About" will show software and hardware version information

• Settings The "Settings" Tab of the Pixie-4 Control Panel contains parameters that control the operation of the Pixie-4. Most settings are changed on a channel-by-channel basis. The only exceptions is the coincidence pattern, which affect the module as a whole. The "Settings" Tab also contains controls used to load, save, copy, and extract settings. If not all described controls are visible, click on the "More" button at the bottom of the panel. Energy and Trigger Filter In this section you can set the rise and flat top times for the energy and trigger filter of each channel. The units of time are µs. The energy filter uses averaging of the ADC data and then operates the same filter core at a decimated (i.e. reduced) clock rate. As a result, there are several filter ranges; with a granularity of 0.027µs for filter range 1 (1-bit decimation), 0.053µs for filter range 2 (2-bit decimation), and so on. You can select the filter range in the corresponding control. The trigger filter is always operated at the ADC sampling rate. Its rise time can be varied between 27ns and 413ns. Its flat top however is valid between 0ns and 387ns. The trigger filter will most often use a flat top comparable


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with the average signal rise time. In applications with very short rise times a flat top of zero will give the best pileup rejection performance. Employing a trapezoidal filter avoids the kind of ballistic deficit that occurs when a finite rise time signal is used in conjunction with a Gaussian shaper. The energy filter flat top time should thus be a little larger than the longest rise time expected. The output of the energy filter is sampled one decimated clock cycle before the end of the flat top, plus the signal arrival may jitter by up to one decimated clock cycle with respect to the decimated clock. You should therefore make the flat top two notches longer than the signal rise time. The sum of energy filter rise time and flat top cannot exceed 127 decimated clock periods. If you type in a rise time or flat top value that violates this bound, the Pixie-4 Viewer will adjust it accordingly. The trigger threshold can be set in units of ADC steps. You can get an idea of what the noise in your system is by looking at the trace acquired in the Oscilloscope located on the Calibrate Tab. Use the mouse to zoom in on parts of the displayed trace(s) and estimate the noise. Optimize Energy Filter An optimization of energy filter settings is carried out by scanning all possible combinations of energy filter rise and flat top within their respective limits specified by the user, examining the energy resolution at each combination, and picking the optimal combination which gives the best energy resolution. Results of this optimization, including energy filter rise time, flat top and energy resolution, are stored in an output file whose name is specified by the user in the beginning of the run. Another file which has the same name as the output file but with a different extension (*.tmp) is used to store step-by-step intermediate results. Before starting the optimization, all conditions listed on the "Auto Optimization of Energy Filter" panel should be fulfilled first. This is to ensure that valid MCA spectra will be produced during the optimization and Gauss Fit of energy peaks on the MCA spectra will generate meaningful results. The four channels of a Pixie-4 module can be used to optimize four different Auto Scanning Limits at the same time when the same detector signal is split and input into the four channels. This would speed up the scanning of a large range of energy filter rise time and flat top. You could change the Auto Scanning Limits of each channel by changing the "Channel" control on the left upper corner of the Pixie-4 Run Control panel. At any time, the Pixie-4 module used to carry out this optimization is the current module, i.e. the module indicated by the "Module" control on the left upper corner of the Pixie-4 Run Control panel. So if you want to use a different module, change the "Module" number before you set the Auto Scanning Limits for each channel. Pulse Shape Analysis The trace length and delay values to be entered here, both in units of µs, govern the waveform acquisition. Especially if you request pulse shape analysis these two parameters have to be set correctly. You can use the delay parameter to move the trace. Delay measures the trigger time with respect to the beginning of the recorded trace. For ordinary data taking the trace lengths are up to 13.6µs for each channel. The waveforms will be read in 13.3ns increments from FIFO memory. If event dead time is a concern, the trace length should be set as short as possible. In particular, if only energies and time stamps are of interest, the trace length can be set to zero. The PSA Start and PSA End specify the trace range for Pulse Shape Analysis (PSA). Currently Pixie-4 supports two types of PSA: XIA_PSA and USER_PSA. XIA_PSA reports the signal arrival time by measuring the time when the trace reaches a preset percentage level ("constant fraction") of its magnitude. The preset percentage threshold can be set defined in the CCSRAEditPanel. The arrival time is relative to the starting time of the trace. So for XIA_PSA, the PSA Start and PSA End should be set to include the rising edge of the trace. USER_PSA is a user-defined PSA value, calculated by customized user code linked to the general software.


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Action Buttons [Edit] (Channel Register) CCSRAEditPanel [Edit] (Module Register) HitEditPanel [Copy] (Copy settings) CopyPanel [Extract] (Extract settings) ExtractPanel [Files/Path] (Files and path) AllFilesPanel [Load] (Load settings) [Save] (Save settings) CCSRAEditPanel = Settings -> Channel Register Edit Each channel has its own channel control/status register (CCSRA) . Click a check box to set or clear particular bits. We give a brief description of all relevant bits here. In the CCSRAeditPanel they appear in top to bottom order. Bit 0: Group trigger mode This bit controls waveform acquisition. To stop the FIFO and store a waveform two conditions must be fulfilled. A fast trigger primes the FIFO to stop after a programmed delay, but only if by that time a valid trigger is recorded. When bit 0 is cleared the source for that valid trigger is the locally generated event trigger of this channel. When bit 0 is set, the trigger source will be a signal on the distributed DSP-trigger line. This allows for master slave operation as outlined in the User's Manual. Note that a module control determines how trigger signals are distributed within and between modules. If the checkbox "Share triggers with other modules" in the HitEditPanel is checked, the module issues and responds to triggers from other modules in the system through the backplane. If not, the module is disconnected from the backplane; group triggers are only distributed between the 4 channels of the module. This is a module-wide parameter. If no channel is set to respond to group triggers, this checkbox should be cleared. Rev. B modules are always connected to the backplane. Bit 1: Measure individual live time This bit will in almost all applications be opposite to bit 0. Its setting decides who asserts the live time control. When cleared, the DSP ensures that during the event interrupt no channel can generate another trigger and latch new event data, at least not after the coincidence time window (see HitEditPanel below). This setting is useful in master slave operation and almost in all cases where list-mode data are required. On the other hand, when channels are operating independently and only MCA information is needed (MCA mode), but not list mode data, then this bit should be set to achieve the highest throughput. Bit 2: Good channel Only channels flagged as good will be read out. This setting has no bearing on the channel's capability to issue a trigger. There can be a triggering channel whose data are discarded. Channels not marked as good will not be included in the automatic offset adjustment Bit 3: Read always Set this bit if you want a good channel to be read out even if it did not report a hit. It cannot report valid energy or timing data in that case, but if operated in group trigger mode you will get a valid waveform. This way you can collect waveforms not biased by trigger requirements. Bit 4: Enable trigger You can switch on any channel's ability to contribute to the event trigger with this bit. Bit 5: Trigger positive For channels with triggering enabled, this causes triggering on the rising edge of the input signal when the bit is set, and triggering on the falling edge when the bit is not set. The core of the trigger/filter


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FPGA can only trigger on a rising edge. So, if the bit is not set the FPGA will invert the signal before storing it in the FIFO and sending it to the core. Bit 6: GFLT required In a larger experiment you may want to exercise control over which events to accept and which to reject based on external logic. A logic signal inhibiting event triggers can be distributed on the PXI backplane. When bit 6 is set, a logic high on the GFLT (Veto) backplane line will inhibit latching data and issuing triggers for this channel. Bit 7: Histogram energies Switch on incrementing an energy histogram in the DSP's MCA memory with this bit. You can choose to have histogramming in list mode runs. The histograms will continue to be updated over multiple runs, started with the resume run command. Bit 10: Compute constant fraction time The DSP can use pulse shape analysis to compute a precise signal arrival time using the digital equivalent of a constant fraction discriminator. For this to work correctly the rising part of the signal should be fully contained in the recorded trace. The time computed is the arrival time after the start of the acquired waveform in units of 1/256th of an ADC sampling interval. This information can be used to replace the recorded channel time which is derived from a (digital) leading edge discriminator, cf the User's Manual. The DSP code shipped with the Pixie-4 has some pulse shape analysis capabilities already built in. One of these functions, the digital constant fraction discriminator takes an input parameter---the threshold percentage. The default value is 25% since it is a commonly used threshold fraction for this type of discriminator. The result of the computation is the time of signal arrival measured with respect to the start of the acquired waveform. The result is written into the channel header in the linear output data buffer, cf the User's Manual for details. Integrator: This variable controls the event energy reconstruction: 0: Normal code. 1: Use energy filter gap sum only. This is equivalent to simply integrating over the pulse. It is useful for scintillator applications where event energies can be derived by setting the energy filter flat top long enough to cover the whole scintillation pulses. 2: Ignore energy filter gap sum when reconstructing event energy. This is useful for step pulses whose amplitude is the difference between the high and low steps. HitEditPanel = Settings -> Module Register Edit The coincidence pattern mask is useful for Pixie-4 channels operating independently from each other, though they may be sharing clocks and triggers. With this mask you may require that an event as witnessed by an individual channel match any of the preset hit patterns to be accepted by the DSP. An example shall illustrate this feature. Assume a single module connected to 4 detectors which observe a Na-22 source, emitting back to back 511keV gamma-rays from positron annihilation. Channels 0 and 1 are connected to one pair of back to back detectors and channels 2 and 3 are connected to a second pair of back to back detectors. You are interested only in gammas from positron annihilation. Thus a coincidence in channel 0 and 1 or a coincidence in channel 2 and 3 is required. If all 4 channels were in coincidence, that would be fine too. So, the acceptable hit patterns would be (0,0,1,1), (1,1,0,0) and (1,1,1,1), where the right most digit indicates channel 0 and the left most is for channel 3. To achieve the desired behavior, you have to select the three acceptable hit patterns in the HitEditPanel by checking the appropriate boxes, and deselect all other hit patterns by not checking their boxes.


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Note the difference between "hit" and "trigger": A "hit" occurs if a pulse goes over threshold and passes pileup inspection. "Hits" can not be disabled. A "trigger" means there is a "hit" plus a request for event processing is sent to the module's DSP unit. "Triggers" can be disabled on a channel by channel basis in the CCSRAEditPanel. Event processing is still subject to the four channels showing an acceptable hit pattern. Furthermore, each channel is only processed if it shows a hit or is marked as "read always" in the CCSRAEditPanel. Only "hit" channels will have valid energy and timing information, but all channels will have waveforms. In general, with 4 channels there are 16 distinct possible hit patterns, and you can select any combination of these to be a valid event. If you want to disable this feature, you should check all boxes in the HitEditPanel, i.e. accept any hit pattern. Coincidence Window A delay time set in the Pulse Shape Analysis section, or a difference in peaking times between channels increases the overall event time. Consequently, the width of the coincidence window (in ns) has to be adjusted to accommodate the full event. Usually, this is done automatically by the Pixie Viewer and there is no need to edit the coincidence window manually. On the other hand, if the delay time is decreased, a smaller coincidence window is possible. This would reduce data processing time and allow for a higher event rate. However, to avoid overwriting a large coincidence window intentionally set by the user, the value is not adjusted automatically. Instead, the HitEditPanel displays both the minimum coincidence window and the actual coincidence window. The user can set the actual coincidence window, but it should not be smaller than the minimum coincidence window. Backplane Options If "group trigger" operation is requested in the CCSRAEditPanel, each channel will respond to distributed triggers rather than own local trigger. Triggers are always distributed within a module: Any channel with "trigger enabled" will issue a trigger for distribution, and any channel set to "group trigger" will respond to the distributed trigger, including those issued by itself. In addition, triggers can be distributed over the PXI backplane between modules. If the checkbox "Share triggers with other modules" is checked, the module issues and responds to triggers from other modules in the system. If not, the module is disconnected from the backplane; group triggers are only distributed between the 4 channels of the module. If no channel is set to respond to group triggers, this checkbox should be cleared. Rev. B modules are always connected to the backplane. CopyPanel = Settings -> Copy This panel can be used to copy parameter settings from one module to another. The source module and channel are selected at the top of the panel. The parameters to be copied are organized into list box in the left-hand column. The right-hand column shows the destination channels and modules for the copy operation. The Items to copy shown on the Copy Panel and the actual variables to be copied are listed below. Items Actual variables to be copied Gain Gain [V/V] Offset Offset [V] Filter Energy Filter Rise Time and Flat Top, Baseline Cut Trigger Trigger Filter Rise Time and Flat Top, Trigger Threshold FIFO Trace Length, Delay, dT [µs], PSA Start, PSA End, CFD Threshold CSR Channel CSRA, Channel CSRB, Module CSRB Coinc. Coincidence Pattern, Coincidence Window


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MCA Cut-Off Energy, Binning Factor TAU Tau [µs] INTEGRATOR Integrator After selecting source, destination and parameters, click on the "Copy" button to execute the copy operation. ExtractPanel = Settings -> Extract This panel can be used to extract parameter settings from a file to selected modules and channels. The source file is specified at the top of the panel. Clicking on the "Find" button to locate the source file. Parameters to be extracted and destination modules or channels are selected in the same manner as in the copy panel. Click the "Extract" button to execute the operation. AllFilesPanel = Settings -> Files/Paths This panel gives you access to the underlying files of the Pixie-4 software. Usually, these files are already loaded in the memory of the Pixie-4 Viewer. You only have to change these files when you receive updates from XIA. The directory locations are specified as complete (not relative) search paths: the DSP Path for the DSP code; and the FPGA Path for the trigger/filter FPGA configuration. Use a colon (:) as the separator between drive name, directory, and subdirectories. Do not use backslashes (\). For example use "D:XIA:data" rather than "D:\XIA\data". File and Path names should not exceed 80 characters.

• Calibrate If not all described controls are visible, click on the "More" button at the bottom of the panel. Analog Signal Conditioning In the Analog Signal Conditioning section you can set the gain and DC offset for the selected channel and module. Note that the ADCs are dc-coupled to the Pixie-4 inputs, and thus compensation for any DC-offset is necessary. You will rarely have to set this manually, as the DC-offsets can be adjusted automatically through clicking on “Adjust Offsets” on the Oscilloscope. The gain and offset settings are given in units of V/V and V, respectively. The voltage gain computed is the ratio between the pulse height at the module input to the pulse height at the ADC input. Note that the ADC has a 2.2V input range. Histogram Control This section shows the parameters controlling the operation of the multichannel analyzer built into the DSP memory. Energy values are calculated to 16-bit fixed-point numbers. This would correspond to a 64k spectrum. To map the full energy range into the available 32k spectrum, one has to combine bins. At minimum, 2 bins have to be combined into one, so the "Binning Factor" has to be set to 1 (combining 2^1 bins). Higher binning factors can be useful for low count rate or low resolution applications.


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If you want to see a certain range of the spectrum at higher resolution you can enter a "Minimum Energy". This will discard all energies below the minimum and start binning the spectrum from the minimum energy (Bin 0 = Emin). The minimum energy is not applied in MCA runs. Decay Time The "Decay Time" is the exponential RC time constant of the preamplifier. It is required in order to properly calculate corrections to measured energy values. To set and measure the decay time, enter an estimated value then click on the "Auto Find" button. You can also enter a known good value directly in the control. The RC calibration needs to be performed only once for a given preamplifier. The result is then stored in the parameter database, and can be saved in the settings file by clicking on the "Save" button in the Settings tab. Manual Fit "Manual Fit" is done on a channel-by-channel basis. First, choose the channel on which you want to do the manual fit by changing the "Channel" control on the left upper corner of the Pixie-4 Run Control panel. Then set proper dT on the TauDisplay panel, and click the "Run" button to read an untriggered trace for the chosen channel. The exponential fit range can be set either by putting the Cursors A and B on the trace or changing the "Fitting_start" and "Fitting_end" controls on the TauDisplay panel. Clicking the "Do exponential fit" button will perform the exponential fit on the portion of the trace specified by the fitting range. If possible, some of the baseline after the pulse should be included in the fit region. The fitted tau is going to be reported in the "Fitted tau" control and the deviation between the fitting curve and original ADC trace is shown in the "Deviation" control. Click the "Tau Ok" control to download the Tau value to the Pixie-4 module. Optimize Tau The Tau optimization is carried out by scanning all Tau values within the scanning limit specified by the user, examining the energy resolution at each Tau, and picking the optimal Tau value which gives the best energy resolution. Results of this optimization, including the Tau value and energy resolution, are stored in an output file whose name is specified by the user in the beginning of the run. Another file which has the same name as the output file but with a different extension (*.tmp) is used to store step-by-step intermediate results. Before starting the optimization, all conditions listed on the "Auto Optimization of Decay Time" panel should be fulfilled first. This is to ensure that valid MCA spectra will be produced during the optimization and Gauss Fit of energy peaks on the MCA spectra will generate meaningful results. The four channels of a Pixie-4 module can be used to optimize four different Decay Time Limits at the same time when the same detector signal is split and input into the four channels. This would speed up the scanning of a large range of Tau values. You could change the DecayTime Limits of each channel by changing the "Channel" control on the left upper corner of the Pixie-4 Run Control panel. At any time, the Pixie-4 module used to carry out this optimization is the current module, i.e. the module indicated by the "Module" control on the left upper corner of the Pixie-4 Run Control panel. So if you want to use a different module, change the "Module" number before you set the DecayTime Limits for each channel.

• Oscilloscope = Calibrate -> Oscilloscope The Oscilloscope shows 8192 untriggered ADC samples from the input for each channel. The time between samples can be set using the "dT" variable. The display is updated through its "Refresh" button. The DC offset of the preamplifier signal has to be compensated for in order to bring the DC-coupled input into the ADC range. The exact DC value has no bearing on the acquired spectrum and its origin, which is always at zero. The DC-adjustment is used only to ensure that the signals to be


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measured fall comfortably into the ADC range. When clicking the "Adjust Offsets" button, the Pixie-4 Viewer will set the DC offset to a percentage of the full ADC range specified in the “Baseline [%]” control. The offset calibration must be performed with the preamplifiers connected to the Pixie-4 inputs and with both the preamplifier power and detector HV switched on. One should also repeat the offset calibration each time measurement conditions change in any major way, e.g., when the count rate changes greatly. All such changes may influence the DC offset value of the preamplifier signal. To analyze the noise spectrum of the acquired trace, click on the "FFT Display" button, which opens the FFTDisplay.

• FFTdisplay You can analyze the noise spectrum in the trace captured in the Oscilloscope, by observing the Fourier transform of the signal. For best results, remove any source from the detector and only regard traces without actual events. The chart shows a plot of amplitude vs. frequency. The plot is calibrated such that a sine wave with 100 ADC units amplitude (200 units peak-to-peak) will show up with an amplitude of 100. To convert a noise floor measurement into ADC units/sqrt(Hz) use the variable FFTbin displayed at the top of the chart, which tells the width of each frequency bin in the Fourier spectrum. The conversion from amplitudes to rms ADC units/sqrt(Hz) is accomplished by multiplying with 1/sqrt(2*FFTbin). Now, observe that an ADC unit corresponds to 61µV. Using the known gain of the Pixie-4 you can convert the noise into an input noise voltage density measured in V/sqrt(Hz). Or, given a particular energy calibration, the noise density can be expressed as eV/sqrt(Hz). If you click on the “Apply Filter” button, you can see the effect of the energy filter simulated on the noise spectrum.

• Run If not all described controls are visible, click on the "More" button at the bottom of the panel. Run Type This popup menu is used to set the run type to one of the following modes: List Mode List mode is the general data acquisition run. Waveforms, energies and time stamps are collected on an event-by-event basis. The data is stored in various formats (see section 3.6 of the user manual for details): 0x100 full event data (9 words), plus waveforms 0x101 full event data (9 words), no waveforms 0x102 compressed event data (4 words), no waveforms 0x103 compressed event data (2 words), no waveforms Since available memory limits the number of events that each module can store in its buffer, the Pixie-4 Viewer computes the maximum number of events. When the maximum is reached, the run is stopped and the buffer is read out. For a longer run in list-mode, you can request several spills, or buffer fills. For example, if you request a run with 10 spills, you will get 10 list mode buffers worth of data. At start of the first run all previous run history is cleared. For instance MCA memory and run and live time information are cleared. The next nine sub-runs are started with a Resume Run command, which leaves previous run information intact. Run times and live times and spectra in MCA memory are incremented.


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You can also manually adjust the maximum number of events stored before the run is stopped. Some data acquisition systems, which are geared towards event-by-event readout and are not able to handle large buffers, may benefit from the capability to reduce the maximum number of events per spill. Fast List Mode Fast list mode is an event-by-event data acquisition run without waveforms. Since no traces are read out, the data acquisition is faster than a regular list mode; however, no pulse shape analysis (PSA) values are available. There will also be no run statistics and no checks if the event buffer is filled faster than the event processing rate. So the average trigger rate must be kept well below the processing rate. Otherwise, the data from the remainder of the run will be corrupted. The data is stored in various formats (see section 3.6 of the user manual for details): 0x200 full event data (9 words), no waveforms 0x201 full event data (9 words), no waveforms 0x202 compressed event data (4 words), no waveforms 0x203 compressed event data (2 words), no waveforms MCA Mode MCA mode puts all modules into a typical spectrum-only acquisition mode in which there are no list-mode data required. The event data is not stored in the output buffer, but only used to calculate the energy for incrementing the spectrum. Runs end after the time specified in the "RunTime/TimeOut" control counts down to zero. The “Maximum no. of Events” control is set to zero for MCA runs since it is not used to end the run. Any "Minimum Energy" entered in the Histogram Control is ignored for MCA runs. Polling Time The polling time indicates the time interval at which the Pixie-4 Viewer checks if the run in the selected modules has ended. If so, runs are stopped in all modules, if they have not stopped already, and the data are read out. Run Time/Time Out This variable is used to indicate the total run time for MCA runs or the timeout limit for list mode runs. Number of Spills The variable indicates the number of repeated runs. It is only used in list mode runs. Even if set to zero, there will be at least one spill. Maximum no. of Events This variable indicates the maximum number of list-mode events the Pixie-4 module can store in its buffer for each run. It should be zero (indicating unlimited events) for MCA runs. Synchronization The first check box asks if all modules should start and stop simultaneously. In almost all multi-module systems this will be the case and the box should be checked. Synchronization signals are distributed over a PXI backplane line. If a Pixie-4 module is present in the crate, but not part of the current data acquisition setup, it might inhibit the synchronization setup. If you also want all timers in all modules to be reset with the start of the next data acquisition run, click the box "Synchronize clocks". For this feature to be useful all Pixie-4 modules should be operating from the same master clock as described in the user's manual. Output File You can choose a base name and a run number in order to form an output file name. The run data will be written to a file whose name is composed of both. The run number is automatically incremented at the end of each run if you select “Auto update run number” on the Data Record Options panel, but you


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can set it manually as well. Data are stored in files in either the MCA folder if the run is a MCA run or the PulseShape folder if the run is a List Mode run. These files have the same name as the output file name but different extension as described below. ".bin" For list mode runs, buffer data are stored in a file with name extension ".bin". This is a binary file consisting of 16bit unsigned integers. ".dat" For list mode runs, a summary of event data is stored in a file with name extension ".dat". This is an ASCII file. ".mca" For both list mode runs and MCA runs, MCA spectrum data are stored in a file with name extension “.mca” if you select “Auto store spectrum data” on the Data Record Options panel. This is a binary file consisting of 32bit unsigned integers. It includes MCA data for all modules, ordered from channel 0 of module 0 to channel 3 of the last module ".set" Module settings are stored in a file with name extension “.set” after each run if you select “Auto store settings” on the Data Record Options panel. This is a binary file consisting of 16bit unsigned integers. It is equivalent to the ".itx" files saved from the Settings tab. Start Run After you have set all parameters, you can start a run to take data. During the run, the “Run time/time out” control shows the remaining time for MCA runs or time out count down for list mode runs. If you select multiple spills for list mode runs, the number of spills will also count down during the run. For list mode runs, when the first module reaching the preset maximum number of events stops its run, it will also stop the runs in all other modules if Module Synchronization is enabled. Then the data buffer of each Pixie-4 module will be read out and saved into a file. If more than one spill is requested, the run will resume in all modules. For MCA runs, when the “Run time/time out” control counts down to 0, the Pixie-4 Viewer will issue a run stop command to stop the runs in all modules. Then the MCA histogram of each module will be read out and saved into a file. Stop Run If you want to stop a run before it finishes by itself, you can click on this button to manually stop it. This will end runs in all modules and read out and save the data. Data Record Options This panel gives you three options for automating tasks after each run. They are all checked by default to ensure all data are saved for each data run. In addition, you can choose to automatically update the MCA spectrum every 5 seconds during MCA runs or every 5 spills during List mode runs. The last option changes the data readout for list mode runs. If checked, the module stores 32 data buffers in external memory, which then are read out in a fast block read. Each readout counts as one "spill". The total number of events will be 32 times the "Maximum no. of events" times the "Number of spills" shown in the Run Control Tab. External memory readout is not supported for Rev. B modules. If not checked, buffers are read one by one from internal memory. Each readout counts as one spill. The total number of events will be the "Maximum no. of events" times the "Number of spills" shown in the Run Control Tab. The readout deadtime will be higher in this mode.


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• Analyze On the top left part of the Analyze tab shows the run time and the measured event rate for the selected module. On the right part shows for each channel the fractional live time and the input count rate. Note that the run time is the sum of time spent in sub-runs (called spills), but ignoring the time it took the host to read out the data from Pixie-4 modules. Similarly, the live time was measured only while one of the sub-runs was ongoing. MCA Spectrum Pulse-height spectra accumulated in the internal Pixie-4 memory can be displayed after pressing the MCA Spectrum button. Pulse heights are computed to 16 bits precision, i.e. correspond to 64k spectra. As the memory allows for only 32k words per channel, bins have to be combined according to the Binning factor for each channel in the Histogram Control. You can select the module you want to inspect and you can add or remove individual channel displays by clicking the MCA check boxes. The "Fit" menu allows you to make Gaussian fits to peaks in the histograms. The fit range can be set channel by channel in the "Min" and "Max" fields, or by placing cursors on the spectrum with the mouse. The "Fit" menu starts a fitting routing for one or all channels. The routine does take a constant background term into account, though its value is not displayed. The fit results that are displayed include the peak position, the number of counts in the peak, and its relative and absolute full width at half maximum (FWHM), calculated from the Gaussian fit. For best results be sure to extend the fit range to cover some of the constant background. To calibrate your energy scale, you can after the fit type the true energy value into the field "Peak" and the scale will automatically be adjusted. The "Sum" menu gives you three options of summing the spectrum. You can either sum the range defined by the "Min" and "Max" fields without any corrections, sum the range and subtract the background, or sum the entire MCA. Summing is performed on all four channels at the same time. The calculated Sum is displayed in the "Peak Area" field, and the MCA maximum of the sum range is displayed in the "Peak" field. The "Files" popup menu allow to store individual spectra and read back stored spectra from disk. There are three operations: "Save MCA to Igor text file" will save the current MCA (4 channels) as a scaled wave with some added comments in a text file. This can be useful to import data into other applications "Read MCA from Igor text file" will read back a Igor text file saved as above. "Extract MCA from binary file" will read MCA data for the current module from a binary file, such as the .mca file automatically saved at the end of the run. The file is assumed to be in 32bit unsigned integer format. You can "Update" the MCA during a run at any time. List Mode Traces After a list mode run has finished, the pulse shape can be displayed on an event-by-event basis in the List Mode Traces panel. The most recently acquired data file will be searched for the event required in the Event number field. The display will show the ADC traces from the selected module, and the associated energy for those channels that reported a hit in this event. Traces and energies are scaled


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as 16-bit numbers. Note that the ADC traces shown in the Oscilloscope are raw 14-bit numbers, i.e. ADC traces have values divided by 4. In order to display traces from an earlier experimental run one needs to change the Data File name by entering it directly in the “Data File” control or clicking the “Find” button. If you want to see the response of the energy and trigger filters for the current event, click on the "Digital Filter" button, which opens the Filter Display tab. This window is mainly intended for diagnostic purposes. For information how to use the Pixie-4 for more detailed pulse shape analysis, please contact XIA. Filter Display This graph is used to see the simulated response of the energy and trigger filters in an event. You can browse the leading edge trigger filter response and the energy filter response of individual events. The latter requires a trace length of at least twice the peaking time plus the gap time to be displayed. The trace is shown in red. The trigger filter is shown in blue (FF is for fast filter), and the energy filter is shown in green (SF is for slow filter). List Mode Spectrum Pulse height spectra can be reconstructed from list mode data stored on the disk. The file shown in the "Data File" field will be processed and the resulting histograms will be displayed for the selected Pixie-4 module. Use [Read] after changing the data file to process the new data, and [Histo] to update the displayed spectrum. The full spectrum length is equal to 64k channels. Use "No. of bins" and "Delta E" settings to compress the spectrum such that it fits the display. Hint: use 8000 and 4 to see the full range of data, and then adjust these numbers to zoom into the range of interest. The number of bins and the deltaE variables are kept in memory for each channel individually. Be sure to select the channel of interest prior to changing these variables. Use the mouse to zoom in on peaks of interest. In the max and min fields you can select a fit range. [Gauss fit] will produce a Gaussian fit with constant background. Displayed results are the area under the peak and the energy resolution. Again the min and max variables are stored for each channel.

User's Manual

PXI Power Distribution Module

Version 1.0.0, June 2004




Disclaimer Information furnished by XIA is believed to be accurate and reliable. However, XIA assumes no responsibility for its use, or for any infringement of patents, or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under the patent rights of XIA. XIA reserves the right to change the DGF Pixie product, its documentation, and the supporting software without prior notice.

PXI PDM User’s Manual V1.00 XIA 2004. All rights reserved.

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Table of Contents ............................................................................................................ ii 1 Overview................................................................................................................1 2 Preamplifier Power Supply ....................................................................................2 3 Clock Distribution..................................................................................................3

3.1 Local clock only.................................................................................................... 4 3.2 PXI PDM is clock master ..................................................................................... 4

3.2.1 Distribute local clock via PXI clock ..................................................................... 4 3.2.2 Distribute local clock via daisy-chained line ........................................................ 5 3.2.3 Distribute local clock via bussed line ................................................................... 5

3.3 External clock is clock master .............................................................................. 5 3.3.1 Distribute external clock via PXI clock ................................................................ 5 3.3.2 Distribute external clock via daisy-chained line................................................... 6 3.3.3 Distribute external clock via bussed line .............................................................. 6

3.4 Clock master on backplane ................................................................................... 6 3.4.1 PXI clock input ..................................................................................................... 6 3.4.2 Bussed clock input ................................................................................................ 7 3.4.3 Daisy-chained clock input..................................................................................... 7 3.4.4 Other Clock Options ............................................................................................. 7

4 Backplane Triggers ................................................................................................8 4.1 FPGA operation modes......................................................................................... 8 4.2 Description of Backplane Lines............................................................................ 9

4.2.1 Bussed backplane lines ......................................................................................... 9 4.2.2 Neighboring backplane lines............................................................................... 11 4.2.3 Star Trigger lines................................................................................................. 12

5 Application Example ...........................................................................................13 6 Optional High Voltage.........................................................................................15

6.1 Operation............................................................................................................. 15 6.2 HV shutdown (JP35)........................................................................................... 15

7 Default Jumper settings........................................................................................16 8 Front Panel Connector Pinout..............................................................................17


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1 Overview The PXI Preamplifier Power and Trigger Breakout Module (PXI PDM) is a module to support XIA’s Pixie-4 data acquisition modules. It is manufactured in a 3U CompactPCI/PXI form factor and can reside in any peripheral slot (2-8) of a standard 3U chassis, together with Pixie-4 modules or by itself. Slot 2, the PXI Star Trigger slot, is the preferred location, as it allows the use of some additional functions. Though manufactured in the CompactPCI/PXI form factor, the PXI PDM does not have a PCI interface and is thus not recognized by the PCI bus controller or host computer. It only uses power from the PCI backplane and connects to the PXI backplane lines used for clock and trigger distribution by Pixie-4 modules. The power is used to generate a low noise preamplifier power supply; the clock and trigger lines can be brought to the PXI PDM front panel to connect to external electronics. The PXI PDM provides four principal functions, namely

• Preamplifier power supply for the detector • Clock distribution • Access to backplane trigger signals • High Voltage suppy for the detector bias (optional)


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2 Preamplifier Power Supply

The PXI PDM provides +/-12V and +/-24V power through a DB9 connector on its front panel. This enables a compact experimental setup of detector and Pixie-4 data acquisition boards without the need for external power supplies. Moreover, powering the detector and the Pixie-4 boards from the same source eliminates potential grounding problems. The power supply output currents are rated according to the following table:

Supply Voltage Maximum Current +12V 100mA -12V 100mA +24V 40mA -24V 40mA

Table 1: Maximum currents for the preamplifier power supply.

The pinout of the front panel DB9 connector follows the common pattern in nuclear instrumentation, shown in the table below. Some normally unused pins can carry logic signals from the backplane if the corresponding jumper is set.

Pin Number Signal Notes 1 GND 2 GND 3 EventTrigger Only if Jumper 38 is set 4 +12V 5 Veto Only if Jumper 36 is set 6 -24V 7 +24V 8 Time Only if Jumper 37 is set 9 -12V

Table 2: Pinout of the DB9 front panel connector. See section 4 for a description of the signal lines


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3 Clock Distribution Note: This description assumes that the board has been modified after production. There should be an additional wire on the back side of the board near the clock jumpers. In experimental setups with more than one Pixie-4 module, all Pixie-4 modules should run off the same clock to synchronize triggers and timestamps between them. There are a number of options to share clocks between Pixie-4 modules without the need for a PXI PDM module. The PXI PDM allows additional configurations. In particular, it allows the use of the low skew PXI clock from the PXI backplane, and it allows input from and output to external clock sources. There are five possible clock sources for the PXI PDM:

1. The local clock crystal on the module 2. An external differential (LVDS) clock connected to the front panel 3. The PXI clock provided by the chassis. By default, it runs at a frequency of 10MHz

and is only useful for Pixie-4 clock distribution if it has been overridden by a 37.5MHz clock signal.

4. A clock from a module distributed through a bussed backplane line 5. A clock from left neighboring module distributed through a daisy-chain

One of these clock sources can be selected for the PDM’s local FPGA. A clock is required to distribute the trigger signals as described in section 4. The clock signal can also be distributed to other modules one of in four different ways:

1. The PDM always sends out a differential (LVDS) clock to the front panel 2. The PDM can override the PXI clock created by the backplane, which is distributed

to all slots in the PXI chassis. 3. The PDM can send out the clock to a bussed backplane line to all slots in the chassis. 4. The PDM can send out the clock to the right neighboring slot .

To local FPGA

To front panel output

To PXI clock override

Output to right neighbor

To BUS clock output

Local clock JP1: 3-1

always always JP5: 2-3 through FPGA JP5: 2-1

Front panel input JP1: 4-6; JP6

always always JP5: 2-3 through FPGA JP5: 2-1

PXI clock input JP1: 3-5

always always illegal jumper setting

through FPGA JP5: 2-1

BUS input JP1: 4-2

always always JP5: 2-3 through FPGA illegal jumper setting

Left neighbor input (if signal present)

not possible (use local)

not possible not possible with jumper bypass (disable FPGA output)

not possible

Table 3: Summary of clock distribution options for the PXI PDM. Choose one of the input options (rows) and one of the three backplane output options, as described in detail below.


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The different options for clock distribution are summarized in Table 3 and explained in detail below. In practice, the following three options should cover most applications:

1. The PXI PDM is not used for clock distribution, and runs of its local clock, as described in section 3.1

2. The PXI PDM, with its local clock source, is used to override the PXI clock from the backplane to distribute the clock signal to all modules, as described in section 3.2.1

3. The PXI PDM is used to run all modules in the chassis from an external clock, as described in section 3.3.1

3.1 Local clock only To run the PXI PDM from its local clock, independent of any other clocks in the system, set a shunt on jumper JP1 such that pins 1 and 3 are connected. Do not set jumpers JP3, JP4, and JP6 and do not set any shunt on jumper JP5. Any signal on the front panel clock input (pins 1 and 2 of the 2mm connector) will be ignored. Note that the front panel clock output (pins 15 and 16 of the 2mm connector) always carries a differential clock signal (LVDS). Furthermore, the daisy-chained clock output to the right neighbor (PXI_LBR0) is driven by the FPGA unless shunts on J10 are set correctly. To avoid driving conflicts, do not set Jumper JP10 (to connect left and right neighboring lines) if there is a signal source signal driving the clock line from the left, and remove jumper JP3 on the (right) neighboring Pixie-4 board.

3.2 PXI PDM is clock master The PXI PDM can distribute its local clock to the other modules in the chassis in 3 different ways. An LVDS clock output signal is also available on pins 15 and 16 of the front panel I/O connector to distribute the clock to other chassis. Any signal on the front panel clock input (pins 1 and 2 of the 2mm connector) will be ignored. The three options for clock distribution are

3.2.1 Distribute local clock via PXI clock If the PXI PDM resides in slot 2 of the chassis, it can override the 10MHz clock provided by the backplane with its local clock. The backplane will distribute the local clock with low skew buffering to each slot in the chassis. This is the preferred configuration if slot 2 is available. To do so, set a shunt on jumper JP1 such that pins 1 and 3 are connected. Do not set jumpers JP3, JP4, and JP6. Set a shunt on jumper JP5 such that pins 2 and 3 (the middle and the upper pin) are connected. To avoid conflicts with the daisy-chained backplane clock, either set the shunts on J10 to disable the clock output (see Table 4), or remove both Jumper JP10 on the PXI PDM and JP3 on the neighboring Pixie-4 module.


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3.2.2 Distribute local clock via daisy-chained line If slot 2 is not available, the daisy-chained clock output can be used to send the clock to the neighboring module, which will pass it on to its neighbor etc. For the PXI PDM to work as he clock master, all Pixie-4 modules have to be located to the right of the PXI PDM. To do so, set a shunt on jumper JP1 such that pins 1 and 3 are connected. Do not set jumpers JP3, JP4, and JP6 and do not set any shunt on jumper JP5. Set the shunts on J10 to enable the clock output (see Table 4). Make sure the Pixie-4 boards are configured to use the daisy-chained clock as an input.

3.2.3 Distribute local clock via bussed line If the PXI PDM can not sit in slot 2 or to the right of all Pixie-4 modules, it can send the external clock through a bussed clock line to all modules. This mode is not recommended for systems with more than three Pixie-4 modules. To do so, set a shunt on jumper JP1 such that pins 1 and 3 are connected. Do not set jumpers JP3, JP4, and JP6. Set a shunt on jumper JP5 such that pins 1 and 2 (the lower and the middle pin) are connected To avoid conflicts with the daisy-chained backplane clock, either set the shunts on J10 to disable the clock output (see Table 4), or remove both Jumper JP10 on the PXI PDM and JP3 on the neighboring Pixie-4 module.

3.3 External clock is clock master The PXI PDM can use an external differential (LVDS) clock signal, connected to pins 1 and 2 of the front panel I/O connector for its local FPGA and distribute it to all modules in the chassis in 3 different ways. A repeated LVDS clock signal is available on pins 15 and 16 to distribute the clock to other chassis. The three options for clock distribution are

3.3.1 Distribute external clock via PXI clock If the PXI PDM resides in slot 2 of the chassis, it can override the 10MHz clock provided by the backplane with the external clock. The backplane will distribute the external clock with low skew buffering to each slot in the chassis. This is the preferred configuration if slot 2 is available. To do so, set a shunt on jumper JP1 such that pins 4 and 6 are connected. Set jumper JP6 but not jumpers JP3 and JP4. Set a shunt on jumper JP5 such that pins 2 and 3 (the middle and the upper pin) are connected. To avoid conflicts with the daisy-chained backplane clock, either set the shunts on J10 to disable the clock output (see Table 4), or remove both Jumper JP10 on the PXI PDM and JP3 on the neighboring Pixie-4 module.


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3.3.2 Distribute external clock via daisy-chained line If slot 2 is not available, the daisy-chained clock output can be used to send the clock to the neighboring module, which will pass it on to its neighbor etc. For the PXI PDM to work as he clock master, all Pixie-4 modules have to be located to the right of the PXI PDM. To do so, set a shunt on jumper JP1 such that pins 4 and 6 are connected. Set jumper JP6 but not jumpers JP3, JP4. Do not set any shunt on jumper JP5. Set the shunts on J10 to enable the clock output (see Table 4). Make sure the Pixie-4 boards are configured to use the daisy-chained clock as an input.

3.3.3 Distribute external clock via bussed line If the PXI PDM can not sit in slot 2 or to the right of all Pixie-4 modules, it can send the external clock through a bussed clock line to all modules. This mode is not recommended for systems with more than two Pixie-4 modules. To do so, set a shunt on jumper JP1 such that pins 4 and 6 are connected. Set jumper JP6 but not jumpers JP3, JP4. Set a shunt on jumper JP5 such that pins 1 and 2 (the lower and the middle pin) are connected. To avoid conflicts with the daisy-chained backplane clock, either set the shunts on J10 to disable the clock output (see Table 4), or remove both Jumper JP10 on the PXI PDM and JP3 on the neighboring Pixie-4 module.

Note: Both the front panel clock input and the clock output are LVDS differential signals. The signal amplitude is about 400mV. The incoming clock is terminated with 100Ohm between the two differential lines if JP6 is set. The outgoing clock has to be terminated likewise at the receiving end. For longer distances, a twisted or shielded cable is recommended, rather than the flat cable used for the trigger lines.

3.4 Clock master on backplane In cases where another module in the chassis is the clock master, the PXI PDM can connect to that clock and bring it out to the front panel as a differential clock. Pins 15 and 16 of the I/O connector always carry the clock output signal. The clock for the local FPGA is always connected to the selected inputs. The backplane master clock input can be selected as follows:

3.4.1 PXI clock input If the master clock is distributed through the PXI clock, set a shunt on jumper JP1 such that pins 3 and 5 are connected. Do not set jumpers JP3, JP4, and JP6. Do not set a shunt on jumper JP5. Any signal to the front panel clock input (pins 1 and 2 of the 2mm connector) will be ignored.


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To avoid conflicts with the daisy-chained backplane clock, either set the shunts on J10 to disable the clock output (see Table 4), or remove both Jumper JP10 on the PXI PDM and JP3 on the neighboring Pixie-4 module.

3.4.2 Bussed clock input If the master clock is distributed by another module through the bussed clock line, set a shunt on jumper JP1 such that pins 2 and 4 are connected. Do not set jumpers JP3, JP4, and JP6. Do not set a shunt on jumper JP5. Any signal to the front panel clock input (pins 1 and 2 of the 2mm connector) will be ignored. To avoid conflicts with the daisy-chained backplane clock, either set the shunts on J10 to disable the clock output (see Table 4), or remove both Jumper JP10 on the PXI PDM and JP3 on the neighboring Pixie-4 module.

3.4.3 Daisy-chained clock input In its current revision, the PXI PDM does not connect to daisy-chained clocks coming in from the left, neither for its local FPGA nor for distribution to other chassis. It can be operated on its local clock and at the same time pass through the backplane clock signal from left to right if JP10 is set. However, if JP10 is set, the shunts on J10 should be set (see Table 4) to disable the FPGA from sending out its local clock to the right neighbor line, which would cause a conflict.

3.4.4 Other Clock Options In principle, though rarely necessary, it is also possible to distribute the master clock back onto the backplane (e.g. the PXI PDM receives the master clock through the bussed clock line and sends it out through the PXI clock to other modules). To do so, set the jumpers according to the clock input as described above. To send out the clock as a PXI clock, if the PXI PDM is in slot 2, set a shunt on jumper JP5 such that pins 2 and 3 (the middle and the lower pin) are connected. For a bussed clock, connect pins 1 and 2. To send out the clock to the right neighbor, set the shunts on J10 to enable the clock and remove JP10, but not JP3 on the neighboring Pixie-4 module. Note that some jumper settings are illegal, as the same clock option can not be source and destination simultaneously.


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4 Backplane Triggers

The trigger signals of the Pixie-4 modules on the backplane can be accessed through the I/O connector on the front panel of the PXI PDM. An FPGA between the backplane and the front panel connector acts as a configurable logic gate to implement combinations of backplane signals, which are then routed to the front panel. For direct access to a few most common signals, three backplane lines are also included in the DB9 power connector, without going through the FPGA (see Table 2). The configuration of the FPGA can be adapted to specific applications. Below we describe the standard configuration PDM 1.0, generated 6/11/2004. For custom configurations, contact XIA. Note: Care should be taken to only connect appropriate 3.3V signals at the front panel inputs and to avoid shorts on the signal outputs, as they are connected directly to the FPGA with no intermediate buffers! The 30 pins of the front panel connector include input and output signals, ground and power, as listed in Table 5. The connector is a shrouded header with 2mm pitch. A matching receptacle is for example Molex part 87568-3091. Usually signals will be brought out to some external electronics with a 30x flat cable. The external electronics can then distribute clocks and triggers among all chassis. With some limitations, inputs and outputs can also be daisy-chained with a 14x flat cable from chassis to chassis. For complete trigger distribution, the daisy-chain should be closed back from the last to the first chassis, however as described below, the Sync line can not be closed from the last to the first module. Furthermore, any external input signal (such as veto) has to be introduced at some point into the daisy-chain.

4.1 FPGA operation modes In the standard FPGA configuration, the FPGA can be in different modes. The main difference between the modes is the disabling of certain backplane outputs, to avoid conflicts between the PXI PDM and another module on the backplane driving the same line. In addition, connections between the front panel and the backplane might differ if the PXI PDM is located in the most left, middle, or most right slot. By setting shunts on the connector J10, these modes can be selected as described in Table 4.


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Mode Shunt connects Function “Pixie-4 ok” Pins 8-9 Without shunt, all those backplane lines are

disabled that are used for Pixie-4 functions that are not yet implemented. This is to avoid conflicts with accidentally driven lines. Currently, these lines are always disabled

“enable” Pins 6-7 Without shunt, all backplane outputs are disabled. Backplane inputs are still active and are brought to the front panel

“left” Pins 4-5 Set shunt to indicate that the PXI PDM is in the most left position in the chassis. Disables outputs to left neighbors and uses the alternative the Token Ring input on the backplane

“bypass” Pins 2-3 Set shunt to indicate that the bypass shunts on jumpers JP10-22 are set to connect left and right neighboring lines, usually when module in middle position. Disables outputs on all neighboring lines (including clock).

“right” Pins 0-1 Set shunt to indicate that the PXI PDM is in the most right position in the chassis. Disables outputs to right neighbors (including clock ) and uses the alternative Token Ring output on the backplane

Table 4: Shunts on J10 to set FPGA modes. Shunts can be set simultaneously for all modes, except setting both “left” and “right”. Pin 0 of J10 is the upper right pin, closest to the backplane connector and to the edge of the board. The clock output to the right neighbor is disabled if any of the following is true: a shunt is placed on pins 0-1, a shunt is placed on pins 2-3, or no shunt is placed on pins 6-7.

4.2 Description of Backplane Lines The Pixie-4 trigger signals use several of the designated PXI lines on the backplane. These lines come in three different types: bussed lines, neighboring lines and the star trigger lines.

4.2.1 Bussed backplane lines Bussed backplane lines connect all slots of a PXI backplane. (In a chassis with more than 8 slots, the bussed lines can be divided in several segments, see manufacturer’s details.) In the Pixie-4 trigger setup, four of these lines are used as wire-OR busses (active low with pullup) to distribute trigger and synchronization signals: FastTrigger, EventTrigger, Sync, and Time.


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• FastTrigger signals that in at least one module an input signal pulse crossed over the trigger threshold. The FastTrigger signal is used to stop the FIFOs for waveform acquisition in all modules simultaneously.

• EventTrigger signals that the pulse passed pileup inspection and is indeed a pulse with a valid energy measurement. This signal causes an interrupt in the Pixie-4 DSP to read out and process the event data.

• Sync is used to start and stop runs synchronously. While a module is setting up a data acquisition run (clearing memory, resetting pointers, etc), it pulls this line low. When ready to take data, the line is released. The last module to release the line lets it go high, which signals a runstart to all modules. The first module to finish a run pulls the line low again to stop the data acquisition in all other modules.

• Time is currently unused The PXI PDM connects the wire-OR bussed lines through its FPGA to an input and an output on the front panel. For all signals except Sync, the falling edge of an input pulse will create a ~100ns pulse on the corresponding backplane line. The front panel output is equal to the corresponding backplane line. The Sync backplane line will be pulled low for as long as the front panel input is low. If the front panel input goes high, the backplane line may still be pulled low by a module in the chassis. The front panel output is equal to the backplane line. Note: Since only one backplane line is used for run synchronization, it is not possible to inhibit runs externally (by pulling the backplane low through the PDM) and at the same time know if the Pixie-4 modules are not ready (pulling the line low themselves). This means that in the current implementation, either the PDM output is used to know the status of the backplane, or the PDM input is used to inhibit data acquisition. Limited run synchronization in a multiple chassis system can be set up in 2 ways:

- Either the Sync inputs of all PDMs are controlled in parallel by external electronics, which inhibits data acquisition for an estimated time until all modules are assumed to be ready. While the run is in progress, the external electronics can monitor the signals from the Sync outputs, and stop the run whenever the first output goes low (by pulling the Sync inputs low).

- Alternatively, crates can be daisy-chained (Sync output of one PDM to Sync input of the following PDM). The daisy-chain can not be closed from the last to the first PDM as the system could be locked in an inhibited state. The modules and chassis have to be set up such that the first chassis is in control of the synchronization The Sync output of the PDM in first chassis is determined by state of the backplane line controlled by the Pixie-4 modules in the chassis. While the Pixie-4 moules are not ready to take data, the Sync output will be low and thus inhibit the second chassis, which in turn inhibits the following chassis and so on. When the Pixie-4 modules in the first chassis are ready, its backplane Sync line goes high and the modules in the first crate will begin taking data. The PDM Sync output line will also go high, and if all the Pixie-4 modules in the second chassis were ready before, data acquisition will begin in the second chassis at the same time, and also in any additional chassis further


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down the daisy chain. When a module in the first chassis is finished with the run, it will inhibit all modules in its chassis and also further down the daisy-chain.

Full external run synchronization can be implemented by using 2 backplane lines in future software revisions.

The backplane lines for EventTrigger and Time are also directly accessible in the DB9 preamp power connector, if Jumpers JP37 and JP 38 are set. Jumper JP8 can be set to bypass the FPGA and bring the backplane FastTrigger line directly to the front panel I/O connector (pin 4). Besides the above wire-OR lines, the Pixie-4 modules use two additional bussed backplane lines: Veto and TRreturn

• Veto has to be driven by an external source. If high, it inhibits event triggers of Pixie-4 modules that have the GFLT bit set. There is no pullup on this line. The PXI PDM connects a front panel input through its FPGA to the backplane veto line. Jumper JP32 should be set to connect the front panel input directly to the front panel output for distribution to other chassis. The backplane signal Veto is also directly accessible in the DB9 preamp power connector, if Jumper JP36 is set.

• TRreturn is currently unused, output disabled. It is reserved to implement a token ring for multiplicity information.

The FPGA also connects to all other bussed lines on the backplane, which are unused in the current Pixie-4 configuration (outputs disabled). These signals are currently not available on the front panel.

4.2.2 Neighboring backplane lines Neighboring or daisy-chained backplane lines connect a module to its left and right neighbors. (In slot 2, which has no left neighbor, the lines going to the left are used for the Star Trigger.)

4.2.2.1 Clock One pair of these neighboring lines (PXI_LBR0 and PXI_LBL0) is used for clock distribution. On a Pixie-4 module, the clock coming in from the left neighbor can be configured as the module’s clock input. The module’s clock is always sent out to the right neighbor, independent of the clock source.


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In the PXI PDM, the incoming clock from the left neighbor is not used. The PDM’s FPGA will send out its clock to the right neighbor, unless it is disabled by setting a shunt on J10 in any of the following ways: connecting pins 0-1 (“right” mode), connecting pins 2-3 (“bypass” mode), or disconnecting pins 6-7 (not “enabled” mode). To pass through the clock from a left neighbor to a right neighbor, set a shunt on JP10 to directly connect left input to right output, and connect pins 2-3 on J10 to put the FPGA in “bypass” mode (which disables driving the output).

4.2.2.2 Trigger In the Pixie-4 trigger setup, three of the neighboring lines are reserved to distribute trigger information: Token Ring and Nearest Neighbor (2 lines). They are not yet implemented in the current Pixie software release. In the PXI PDM, the outputs to these backplane lines are currently disabled.

4.2.2.3 Other lines The FPGA also connects to all other PXI neighbor lines on the backplane, which are unused in the current Pixie-4 configuration (outputs disabled). These signals are currently not available on the front panel. For all PXI neighbor lines, there are bypass jumpers (JP10-22) on the PXI PDM, to directly connect lines to/from the left to the corresponding lines from/to the right. If these jumpers are used, the connect pins 2-3 on J10 to put the FPGA in “bypass” mode (which disables driving the outputs).

4.2.3 Star Trigger lines Designated “Star Trigger” lines on the PXI backplane connect each module to slot 2. These lines can be used by the Pixie-4 modules to share trigger or multiplicity information (not yet implemented). If the PDM sits in slot 2, it can access these lines, and bring out an AND of the signal from all modules to the front panel. Set the shunts on J10 to indicate the module is in the “left” position.


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5 Application Example As an example, we consider the case of two chassis with one Pixie-4 and one PXI PDM each. Both chassis will also have their own system controller to set up and control the Pixie-4 modules. In this setup, chassis 1 will be the Sync master and the PDM in chassis 1 will be the clock master. Triggers are distributed from all modules to all modules. The Veto signal is driven by an external source. In each chassis, the system controller sits in slot 1, the PDM in slot 2, and the Pixie-4 module in slot 3. Both Pixie-4 modules in chassis 1 and chassis 2 are configured to receive their clock input from the left neighbor (the PDM) by setting a shunt on Jumper JP3 and no shunts on JP1 or JP2. On PDM 1, in chassis 1, the clock master, we use the local clock crystal as the clock source, which is connected to the front panel clock output and the local FPGA. Thus we set a shunt on JP1 to connect pins 1 and 3 and no shunts on JP 3,4,5, or 6. To enable the clock output from the FPGA to the right neighbor, we set a shunt on J10 such that pins 6 and 7 are connected (“enable” mode1). A shunt is placed on JP 32 to pass through the Veto signal from front panel input to output. All other jumpers (JP8, JP10-22, JP 30-31, JP33-34, JP35-38) have no shunts. On PDM 2, in chassis 2 we use the front panel clock input as the clock source, which is connected to the local FPGA. (The front panel output is also connected, but is ignored as an input in PDM 1.) Thus we set a shunt on JP1 to connect pins 4 and 6, a shunt on JP6 to terminate the incoming LVDS clock, and no shunts on JP 3,4, or 5. To enable the clock output from the FPGA to the right neighbor, we set a shunt on J10 such that pins 6 and 7 are connected (“enable” mode). A shunt is placed on JP 32 to pass through the Veto signal from front panel input to output. All other jumpers (JP8, JP10-22, JP 30-31, JP33-34, JP35-38) have no shunts. The PDM front panel connectors are connected input to output with a flat cable (1mm pitch). For each PDM module, there is a 30x 2mm connector, in which the first 14 lines are the inputs, the second 14 lines are the outputs, and the last 2 lines are power, not used for signal distribution. A cable can be fabricated with pieces of 14x flat cable: one strand of flat cable goes from the outputs of the first connector to the inputs of the second; a second strand from the outputs of the second to the inputs of the first. In the second strand, the Sync output line (of PDM 2) is cut. Furthermore, to introduce a veto signal from an external source, the veto line is cut in an arbitrary position and one of the ends connected to the external source. (Alternatively, JP36 could be set and the external signal introduced in pin 5 of the DB9 connector in both PDMs)

1 Pins 4-5 can be connected in addition to put the module in “left”mode, but this is only important if some of the not yet implemented functions were to be used.


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The Pixie-4 modules can be set up as usual through the user software. One or both can be enabled for triggers, and to share triggers through backplane and PDM they should “respond to group trigger”. When starting data acquisition runs, the checkbox “start/stop modules simultaneously” should be checked. Since chassis 1 is the Sync master, runs must be started in chassis 2 first, which will be kept waiting by chassis 1 until a run is started in chassis 1. During the run, while the veto line is high, no events are recorded in either of the modules. If the run is finished in chassis 1, it will also stop the run in chassis 2 through the Sync line, but not the other way round. Therefore the system should be set up such that the module in chassis 1 will always finish the run first, i.e. it receives much more pulses than the module in chassis 2.


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6 Optional High Voltage The PXI PDM has a double slot High Voltage variant providing a maximum of 0.8mA of current for voltages up to 1.2kV. This variant comes with factory set positive or negative polarity.

6.1 Operation High voltage bias for the detector is provided at the SHV connector labeled “”HIGH VOLTAGE OUT”. For detectors with thermal shutdown protection, connect the shutdown line to the LEMO connector labeled “L/N INHIBIT”. Make sure the jumper settings for the shutdown logic matches your particular detector. When the PXI PDM is switched on, either the “+” or the “-“ LED on the front panel is green, indicating the module polarity. The HV bias can be adjusted from 0 to 1.2kV on the front panel. Use a small screwdriver to turn the potentiometer labeled “ADJUST” to set the voltage. The absolute set voltage is shown in the LCD display. To turn on the high voltage, push the red “ENABLE” button. The LCD display will now show the actual absolute output voltage, ramping up from zero to the set voltage, and the “ENABLED” LED will turn red. Pushing the button a second time will ramp down the high voltage back to zero. Due to detector sensitivity, please refer to your detector user’s manual for bias voltage ramp steepness before making any connection.

6.2 HV shutdown (JP35). Detectors with thermal shutdown protection usually come in two variants: Either logic high (one) indicates shutdown or logic low (zero) indicates shutdown. In order to match the shutdown circuitry to either variant, set JP35 to the logic level indicating the shutdown.


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7 Default Jumper settings By default, jumpers should be set as follows: Jumper Setting Function Caution JP1 connect pins 1-3 local clock source JP3, JP4 remove never used JP5 remove no clock to backplane JP6 set incoming LVDS clock

termination

JP8 remove no FPGA bypass for Fast Trigger to front

JP10-22 remove bypass daisy-chained lines left to right

If set, disable FPGA outputs by setting shunts on J10 to “bypass” mode

JP30-31 remove FPGA bypass for front panel input to output

Do not set. Will cause driver conflict between FPGA and input

JP32 set FPGA bypass for front panel input to output for Veto signal

JP33-34 remove FPGA bypass for front panel input to output

Do not set. Will cause driver conflict between FPGA and input

JP35 remove HV inhibit polarity - optional JP36-38 remove connect backplane trigger to

unused DB9 lines Do not set if detector uses DB9 lines; do not use as input if FPGA “enabled” to drive backplane

J10 do not connect

pins 8-9 reserved to disable output on reseverd lines

<currently unused>

connect pins 6-7 if connected, globally enables FPGA outputs to backplane

do not use DB9 as inputs to backplane when FPGA outputs are enabled (remove JP36-38)

do not connect pins 2-3

if connected, disables FPGA output on daisy-chained lines

must be connected when any of JP10-22 are used to bypass daisy-chained lines

do not connect pins 0-1, 4-5

routes and disables lines according to module position


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8 Front Panel Connector Pinout

Table 5: Pinout of the 2mm front panel I/O connector. The signals can either be brought out to external electronics, or inputs and outputs can be connected from PDM to PDM with a split cable. Notes: 1) For Token Ring, set jumpers according to module position. Currently not implemented 2) The NN distribution only works fully only for 2 chassis. Currently not implemented. 3) Veto out should connect directly to Veto in via JP32; not driven by FPGA or backplane When looking at the front panel, pin 1 is to the top and right.

Front panel pin

Split cable line

Front panel connection type

Backplane pin name

Backplane connection type

Pixie function

1 1A Clock In 2 2A Clock In*

LBR0, TRIG7, or PXI CLK

to right, bussed, or all

clock (depening on jumper setting

3 3A GND 4 4A Input TRIG0 bussed Fast Trigger 5 5A Input TRIG1 bussed Event Trigger 6 6A Input TRIG2 bussed Veto 7 7A Input TRIG3 bussed Sync 8 8A Input TRIG4 bussed Time 9 9A Input LBR8 or

TRIG51 to right (or most left)

Token Ring

10 10A GND 11 11A Input LBR102 to right Nearest neighbor 1 12 12A Input LBL92 to left Nearest neighbor 0 13 13A reserved 14 14A reserved 15 1B Clock Out 16 2B Clock Out* 17 3B GND 18 4B Output TRIG0 bussed Fast Trigger 19 5B Output TRIG1 bussed Event Trigger 20 6B Output N/A3 Veto 21 7B Output TRIG3 bussed Sync 22 8B Output TRIG4 bussed Time 23 9B Output LBL8 or

TRIG51 from left (or most right)

Token Ring

24 10B GND 25 11B Output LBR92 from right Nearest neighbor 0 26 12B Output LBL102 from left Nearest neighbor 1 27 13B Output LBL0..5 from slot 3..8 AND of Star Triggers 28 14B reserved <test pulse out> 29 N/A 3.3V 30 N/A 5V

PIXIE-4 ManualsPixie_Set_Current_ModChan. This will give API programmers more flexibility when using...

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Transcript of PIXIE-4 ManualsPixie_Set_Current_ModChan. This will give API programmers more flexibility when using...