Pipelining I

Pipelining I

TopicsTopics Pipelining principles Pipeline overheads Pipeline registers and stages

Systems I

2

Overview

What’s wrong with the sequential (SEQ) Y86?What’s wrong with the sequential (SEQ) Y86? It’s slow! Each piece of hardware is used only a small fraction of time We would like to find a way to get more performance with

only a little more hardware

General Principles of PipeliningGeneral Principles of Pipelining Goal Difficulties

Creating a Pipelined Y86 ProcessorCreating a Pipelined Y86 Processor Rearranging SEQ Inserting pipeline registers Problems with data and control hazards

3

Real-World Pipelines: Car Washes

IdeaIdea Divide process into independent stages Move objects through stages in sequence At any given times, multiple objects being processed

Sequential Parallel

Pipelined

4

Laundry example

Ann, Brian, Cathy, Dave Ann, Brian, Cathy, Dave each have one load of clothes each have one load of clothes to wash, dry, and foldto wash, dry, and fold

Washer takes 30 minutesWasher takes 30 minutes

Dryer takes 30 minutesDryer takes 30 minutes

““Folder” takes 30 minutesFolder” takes 30 minutes

““Stasher” takes 30 minutesStasher” takes 30 minutesto put clothes into drawersto put clothes into drawers

A B C D

Slide courtesy of D. Patterson

5

Sequential Laundry

Sequential laundry takes 8 hours for 4 loadsSequential laundry takes 8 hours for 4 loads

If they learned pipelining, how long would laundry take? If they learned pipelining, how long would laundry take?

30Task

Order

B

C

D

ATime

3030 3030 30 3030 3030 3030 3030 3030

6 PM 7 8 9 10 11 12 1 2 AM


6

Pipelined Laundry: Start ASAP

Pipelined laundry takes 3.5 hours for 4 loads!Pipelined laundry takes 3.5 hours for 4 loads!

Task

Order

12 2 AM6 PM 7 8 9 10 11 1

Time

B

C

D

A

303030 3030 3030


7

Pipelining Lessons

Pipelining doesn’t help Pipelining doesn’t help latencylatency of single task, it helps of single task, it helps throughputthroughput of entire workload of entire workload

MultipleMultiple tasks operating tasks operating simultaneously using simultaneously using different resourcesdifferent resources

Potential speedup = Potential speedup = Number Number pipe stagespipe stages

Pipeline rate limited by Pipeline rate limited by slowestslowest pipeline stagepipeline stage

Unbalanced lengths of pipe Unbalanced lengths of pipe stages reduces speedupstages reduces speedup

Time to “Time to “fillfill” pipeline and time ” pipeline and time to “to “draindrain” it reduces speedup” it reduces speedup

Stall for DependencesStall for Dependences

6 PM 7 8 9

Time

B

C

D

A

303030 3030 3030Task

Order


8

Latency and Throughput

Latency: time to complete an operationLatency: time to complete an operation

Throughput: work completed per unit timeThroughput: work completed per unit time

Consider plumbingConsider plumbing Low latency: turn on faucet and water comes out High bandwidth: lots of water (e.g., to fill a pool)

What is “High speed Internet?”What is “High speed Internet?” Low latency: needed to interactive gaming High bandwidth: needed for downloading large files Marketing departments like to conflate latency and

bandwidth…

9

Relationship between Latency and Throughput

Latency and bandwidth only loosely coupledLatency and bandwidth only loosely coupled Henry Ford: assembly lines increase bandwidth without

reducing latency

My factory takes 1 day to make a Model-T ford.My factory takes 1 day to make a Model-T ford. But I can start building a new car every 10 minutes At 24 hrs/day, I can make 24 * 6 = 144 cars per day A special order for 1 green car, still takes 1 day Throughput is increased, but latency is not.

Latency reduction is difficultLatency reduction is difficult

Often, one can buy bandwidthOften, one can buy bandwidth E.g., more memory chips, more disks, more computers Big server farms (e.g., google) are high bandwidth

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Computational Example

SystemSystem Computation requires total of 300 picoseconds Additional 20 picoseconds to save result in register Must have clock cycle of at least 320 ps

Combinationallogic

Reg

300 ps 20 ps

Clock

Delay = 320 psThroughput = 3.12 GOPS

11

3-Way Pipelined Version

SystemSystem Divide combinational logic into 3 blocks of 100 ps each Can begin new operation as soon as previous one passes

through stage A.Begin new operation every 120 ps

Overall latency increases360 ps from start to finish

Reg

Clock

Comb.logic

A

Reg

Comb.logic

B

Reg

Comb.logic

C

100 ps 20 ps 100 ps 20 ps 100 ps 20 ps


12

Pipeline Diagrams

UnpipelinedUnpipelined

Cannot start new operation until previous one completes

3-Way Pipelined3-Way Pipelined

Up to 3 operations in process simultaneously

Time

OP1

OP2

OP3

Time

A B C

A B C

A B C

OP1

OP2

OP3

13

Operating a Pipeline

Time

OP1

OP2

OP3

A B C

A B C

A B C

0 120 240 360 480 640

Clock

Reg

Clock

Comb.logic

A

Reg

Comb.logic

B

Reg

Comb.logic

C

100 ps 20 ps 100 ps 20 ps 100 ps 20 ps

239

Reg

Clock

Comb.logic

A

Reg

Comb.logic

B

Reg

Comb.logic

C

100 ps 20 ps 100 ps 20 ps 100 ps 20 ps

241

Reg

Reg

Reg

100 ps 20 ps 100 ps 20 ps 100 ps 20 ps

Comb.logic

A

Comb.logic

B

Comb.logic

C

Clock

300

Reg

Clock

Comb.logic

A

Reg

Comb.logic

B

Reg

Comb.logic

C

100 ps 20 ps 100 ps 20 ps 100 ps 20 ps

359

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Limitations: Nonuniform Delays

Throughput limited by slowest stage Other stages sit idle for much of the time Challenging to partition system into balanced stages

Reg

Clock

Reg

Comb.logic

B

Reg

Comb.logic

C

50 ps 20 ps 150 ps 20 ps 100 ps 20 ps


Comb.logic

A

Time

OP1

OP2

OP3

A B C

A B C

A B C

15

Limitations: Register Overhead

As try to deepen pipeline, overhead of loading registers becomes more significant

Percentage of clock cycle spent loading register:1-stage pipeline: 6.25% 3-stage pipeline: 16.67% 6-stage pipeline: 28.57%

High speeds of modern processor designs obtained through very deep pipelining

Delay = 420 ps, Throughput = 14.29 GOPSClock

Reg

Comb.logic

50 ps 20 ps

Reg

Comb.logic

50 ps 20 ps

Reg

Comb.logic

50 ps 20 ps

Reg

Comb.logic

50 ps 20 ps

Reg

Comb.logic

50 ps 20 ps

Reg

Comb.logic

50 ps 20 ps

16

CPU Performance Equation

3 components to execution time:3 components to execution time:

Factors affecting CPU execution time:Factors affecting CPU execution time:

Cycle

Seconds

nInstructio

Cycles

Program

nsInstructio

Program

Seconds timeCPU

Inst. Count CPI Clock RateProgram XCompiler X (X)Inst. Set X X (X)Organization X XMicroArch X XTechnology X

• Consider all three elements when optimizing• Workloads change!

17

Cycles Per Instruction (CPI)

Depends on the instructionDepends on the instruction

Average cycles per instructionAverage cycles per instruction

Example:Example:

RateClock n instructio of timeExecution iCPIi

n

i tot

iiii IC

ICFFCPICPI

1

where

Op Freq Cycles CPI(i) %timeALU 50% 1 0.5 33%Load 20% 2 0.4 27%Store 10% 2 0.2 13%Branch 20% 2 0.4 27%

CPI(total) 1.5

18

Comparing and Summarizing Performance

Fair way to summarize performance?Fair way to summarize performance?

Capture in a single number?Capture in a single number?

Example: Which of the following machines is best?Example: Which of the following machines is best?

Computer A Computer B Computer CProgram 1 1 10 20Program 2 1000 100 20Total Time 1001 110 40

19

Means

Arithmetic mean

Geometric mean

n

iiTn 1

1

nn

i

iT

1

1

Can be weighted: aiTi

Represents total execution timeShould not be used for aggregating

normalized numbers

Consistent independent of referenceBest for combining resultsBest for normalized results

n

iiTn

Geo1

)ln(1

)ln(

20

What is the geometric mean of 2 and 8?What is the geometric mean of 2 and 8? A. 5 B. 4

21

Is Speed the Last Word in Performance?Depends on the application!Depends on the application!

CostCost Not just processor, but other components (ie. memory)

Power consumptionPower consumption Trade power for performance in many applications

CapacityCapacity Many database applications are I/O bound and disk

bandwidth is the precious commodity

22

Revisiting the Performance Eqn

Instruction Count: No changeInstruction Count: No change

Clock Cycle TimeClock Cycle Time Improves by factor of almost N for N-deep pipeline Not quite factor of N due to pipeline overheads

Cycles Per InstructionCycles Per Instruction In ideal world, CPI would stay the same An individual instruction takes N cycles But we have N instructions in flight at a time So - average CPIpipe = CPIno_pipe * 1/N

Thus performance can improve by up to factor of NThus performance can improve by up to factor of N

Cycle

Seconds

nInstructio

Cycles

Program

nsInstructio

Program

Seconds timeCPU

23

Data Dependencies

Result from one instruction used as operand for anotherRead-after-write (RAW) dependency

Very common in actual programs Must make sure our pipeline handles these properly

Get correct resultsMinimize performance impact

1 irmovl $50, %eax

2 addl %eax, %ebx

3 mrmovl 100( %ebx ), %edx

Time

OP1

OP2

OP3

24

Data Hazards

Result does not feed back around in time for next operation Pipelining has changed behavior of system

Reg

Clock

Comb.logic

A

Reg

Comb.logic

B

Reg

Comb.logic

C

Time

OP1

OP2

OP3

A B C

A B C

A B C

OP4 A B C

25

SEQ Hardware Stages occur in sequenceStages occur in sequence

One operation in process One operation in process at a timeat a time

One stage for each logical One stage for each logical pipeline operationpipeline operation Fetch (get next instruction

from memory) Decode (figure out what

instruction does and get values from regfile)

Execute (compute) Memory (access data

memory if necessary) Write back (write any

instruction result to regfile)

Instructionmemory

Instructionmemory

PCincrement

PCincrement

CCCC ALUALU

Datamemory

Datamemory

NewPC

rB

dstE dstM

ALUA

ALUB

Mem.control

Addr

srcA srcB

read

write

ALUfun.

Fetch

Decode

Execute

Memory

Write back

data out

Registerfile

Registerfile

A BM

E

Registerfile

Registerfile

A BM

E

Bch

dstE dstM srcA srcB

icode ifun rA

PC

valC valP

valBvalA

Data

valE

valM

PC

newPC

26

Instructionmemory

Instructionmemory

PCincrement

PCincrement

CCCC ALUALU

Datamemory

Datamemory

PC

rB

dstE dstM

ALUA

ALUB

Mem.control

Addr

srcA srcB

read

write

ALUfun.

Fetch

Decode

Execute

Memory

Write back

data out

Registerfile

Registerfile

A BM

E

Registerfile

Registerfile

A BM

E

Bch

dstE dstM srcA srcB

icode ifun rA

pBch pValM pValC pValPpIcode

PC

valC valP

valBvalA

Data

valE

valM

PC

SEQ+ Hardware Still sequential

implementation Reorder PC stage to put at

beginning

PC StagePC Stage Task is to select PC for

current instruction Based on results

computed by previous instruction

Processor StateProcessor State PC is no longer stored in

register But, can determine PC

based on other stored information

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Instructionmemory

Instructionmemory

PCincrement

PCincrement

CCCCALUALU

Datamemory

Datamemory

Fetch

Decode

Execute

Memory

Write back

icode, ifunrA, rB

valC

Registerfile

Registerfile

A BM

E

Registerfile

Registerfile

A BM

E

pState

valP

srcA, srcBdstA, dstB

valA, valB

aluA, aluB

Bch

valE

Addr, Data

valM

PC

valE, valM

valM

icode, valCvalP

PC

Adding Pipeline Registers

PCincrement

PCincrement

CCCCALUALU

Datamemory

Datamemory

Fetch

Decode

Execute

Memory

Write back

Registerfile

Registerfile

A BM

E

Registerfile

Registerfile

A BM

E

valP

d_srcA, d_srcB

valA, valB

aluA, aluB

Bch valE

Addr, Data

valM

PC

W_valE, W_valM, W_dstE, W_dstMW_icode, W_valM

icode, ifun,rA, rB, valC

E

M

W

F

D

valP

f_PC

predPC

Instructionmemory

Instructionmemory

M_icode, M_Bch, M_valA

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Pipeline Stages

FetchFetch Select current PC Read instruction Compute incremented PC

DecodeDecode Read program registers

ExecuteExecute Operate ALU

MemoryMemory Read or write data memory

Write BackWrite Back Update register file

PCincrement

PCincrement

CCCCALUALU

Datamemory

Datamemory

Fetch

Decode

Execute

Memory

Write back

Registerfile

Registerfile

A BM

E

Registerfile

Registerfile

A BM

E

valP

d_srcA, d_srcB

valA, valB

aluA, aluB

Bch valE

Addr, Data

valM

PC

W_valE, W_valM, W_dstE, W_dstMW_icode, W_valM

icode, ifun,rA, rB, valC

E

M

W

F

D

valP

f_PC

predPC

Instructionmemory

Instructionmemory

M_icode, M_Bch, M_valA

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Summary

TodayToday Pipelining principles (assembly line) Overheads due to imperfect pipelining Breaking instruction execution into sequence of stages

Next TimeNext Time Pipelining hardware: registers and feedback paths Difficulties with pipelines: hazards Method of mitigating hazards

Pipelining I

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