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Pipelining

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Pipelining

Cycle

F

Instruction

R X M W

F R X M W

F R X M W

F R X M W

F R X M

F R X

1 2 3....

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Reservation Table for a Simple Pipeline

1 2 3 4 5

I-MEM X

REGS-R X

ALU X

D-MEM X

REGS-W X

CYCLE

I-Mem

A DO

RegFile

RW

D-Mem

A DO

DI

IR

IR

B

AC

D

IR IR

E

+4 PC PC

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Single Cycle, Multiple Cycle, vs. Pipeline

ClkCycle 1

Ifetch Reg Exec Mem Wr

Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

Load Ifetch Reg Exec Mem Wr

Ifetch Reg Exec Mem

Load Store

Ifetch Reg Exec Mem WrStore

Clk

Load Store Waste

Ifetch

R-type

Ifetch Reg Exec Mem WrR-type

Cycle 1 Cycle 2

Multiple Cycle Implementation:

Pipeline Implementation:

Single Cycle Implementation:

Slide courtesy of D. Patterson

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Why Pipeline?

Suppose we execute 100 instructions Single Cycle Machine

45 ns/cycle x 1 CPI x 100 inst = 4500 ns

Multicycle Machine

10 ns/cycle x 4.6 CPI (due to inst mix) x 100 inst = 4600 ns Ideal pipelined machine

10 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = 1040 ns

Slide courtesy of D. Patterson

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Why Pipeline? Because the resources are there!

I

n

s

t

r.

O

r

d

e

r

Time (clock cycles)

Inst 0

Inst 1

Inst 2

Inst 4

Inst 3

ALUIm Reg Dm Reg

ALUIm Reg Dm Reg

ALUIm Reg Dm Reg

A

LUIm Reg Dm Reg

ALUIm Reg Dm Reg

Slide courtesy of D. Patterson

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Benefits of Pipelining

Before pipelining: Throughput: 1 instruction per cycle

(or lower cycle time and CPI=5)

After pipelining (multiple instructions in pipe at one time) Throughput: 1 instruction per cycle

WMXRFclktttttt !

latchWMXRFclkttttttt ! ),,,,max(

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Pipelining Rules

Forward travelling signals at each stage arelatched

Only perform logic on signals in the same stage signal labeling useful to prevent errors,

e.g., IR

R, IR

A, IR

M, IR

W

Backward travelling signals at each stagerepresent hazards

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Pipeline Hazards

Data hazards an instruction uses the result of a previous instruction (RAW)

ADD R1, R2, R3 or SW R1, 3(R2)ADD R4, R1, R5 LW R3, 3(R2)

Control hazards

the location of an instruction depends on a previous instructionJMP LOOP

LOOP: ADD R1, R2, R3

Structural hazards two instructions need access to the same resource

e.g., single memory shared for instruction fetch andload/store

collision in reservation table

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Data Hazards (RAW)

Cycle

F

Instruction

R X M W

F R X M W

Write Data to R1 Here

Read from R1 HereADD R1, R2, R3

ADD R4, R1, R5

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Control Hazards

Cycle

F

Instruction

R X M W

F R X M W

Destination Available Here

Need Destination HereJR R25

...

XX: ADD ...

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Resolving Hazards: Pipeline Stalls

Can resolve any type of hazard data, control, or structural

Detect the hazard

Freeze the pipeline up to the dependent stage

until the hazard is resolved

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Example Pipeline Stall (Diagram)

Cycle

F

Instruction

R X M W

F R X M W

Write Data to R1 Here

Read from R1 Here

ADD R1, R2, R3

ADD R4, R1, R5

Bubble

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Resolving Hazards: Bypass (Forwarding)

If data is available elsewhere in the pipeline,there is no need to stall

Detect condition

Bypass (or forward) data directly to the

consuming pipeline stage Bypass eliminates stalls for single-cycle operations

reduces longest stall to N-1 cycles for N-cycleoperations

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Simple Pipeline with Bypass Multiplexers

I-Mem

A DO

Reg

File

RW

D-Mem

A DO

DI

IR

IR

B

AC

D

IR IR

E

+4 IP IP

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Data Hazards With Bypassing

Cycle

F

I

nstruction

R X M W

F R X M W

R1 computed

R1 used

ADD R1, R2, R3

ADD R4, R1, R5

SUB R5, R1, R6

XOR R7, R8, R1

F R X M W

F R X M W

ADD

SUB

XOR

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Summary

Pipelining principles Hazards

Hazard prevention