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Picowatt, 0.45-0.6 v Self-Biased Subthreshold CMOS Voltage Reference

Article in Circuits and Systems I: Regular Papers, IEEE Transactions on · December 2017

DOI: 10.1109/TCSI.2017.2754644

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Arthur Campos de Oliveira

Delft University of Technology

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David Cordova

Université Bordeaux 1


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Hamilton Klimach

Universidade Federal do Rio Grande do Sul


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Sergio Bampi

Universidade Federal do Rio Grande do Sul

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 1

Picowatt, 0.45-0.6 V Self-Biased SubthresholdCMOS Voltage Reference

Arthur Campos de Oliveira, Student Member, IEEE, David Cordova, Student Member, IEEE, HamiltonKlimach, Member, IEEE, and Sergio Bampi, Member, IEEE

Abstract—In this paper, a self-biased temperature-compensated CMOS voltage reference operating at picowatt-levelpower consumption is presented. The core of the proposedcircuit is the self-cascode MOSFET (SCM) and two variantsare explored: a self-biased self-cascode MOSFET (SBSCM)and a self-biased NMOS (SBNMOS) voltage reference. Powerconsumption and silicon area are remarkably reduced bycombining subthreshold operation with a self-biased scheme.Trimming techniques for both circuits are discussed aiming atthe reduction of the process variations impact. The proposedcircuits were fabricated in a standard 0.18-µm CMOS process.Measurement results from 24 samples of the same batch showthat both circuits herein proposed can operate at 0.45/0.6 Vminimum supply voltage, consuming merely 55/184 pW at roomtemperature. Temperature coefficient (TC) around 104/495ppm/oC across a temperature range from 0 to 120 oC wasmeasured. By adding a trimming scheme one can reduce theaverage TC to 72.4/11.6 ppm/oC for the same temperaturerange. Both variants of the proposed circuit achieve a linesensitivity of 0.15/0.11 %/V and a power supply rejection betterthan -44/-45 dB from 10 Hz to 10 kHz. In addition, SBSCM andSBNMOS prototypes occupy a silicon area of 0.002 and 0.0017mm2, respectively.

Index Terms—Subthreshold, voltage reference, self-biased, lowpower, low voltage, picowatt.

I. INTRODUCTION

THE advent of the Internet of Things (IoT) has been atechnological booster for the research efforts towardsthe design of low-power and low-voltage integrated circuits.The main target of these designs are intra-body and portablebiomedical devices [1], [2], energy harvesting systems [3], andenergy-autonomous wireless sensors platforms [4], [5]. Sincesuch systems are very power constrained, their building blocksmust also operate with very limited power.

One of the fundamental blocks for analog and mixed-signalapplications is the voltage reference (VR). Its most com-mon implementation strategy is the so-called bandgap voltagereference (BGR). In the BGR, temperature compensation isachieved when the junction diode (usually implemented asa bipolar transistor) complementary-to-absolute-temperature(CTAT) voltage behavior is counterbalanced by a proportional-to-absolute-temperature (PTAT) source, resulting in the siliconbandgap voltage as the reference output, which is approxi-mately 1.2 V. Although BJT based BGR presents adequateperformance for many applications, it cannot operate with

A. C. de Oliveira, H. Klimach and S. Bampi are with the InformaticsInstitute, Federal University of Rio Grande do Sul, Porto Alegre, RS, 91509-900, Brazil (e-mail: [email protected]; [email protected];[email protected]).

D. Cordova is with IMS Laboratory, Université de Bordeaux, Bordeaux,France (e-mail: [email protected]).

power supplies lower than around 1.5 to 1.8 V, implying thatsupply voltage scaling of such BGRs is impractical. Voltagedividers [7], [8] or Schottky barrier diodes (SBD) [22] are analternative strategy to realize lower supply voltage references.Nonetheless, the minimum supply voltage and current remainconstrained by BJT and SBD characteristics. In contrast,MOSFET subthreshold operation [6] can offer an interestingalternative for both low power and low voltage operation.

Throughout the years, several MOSFET subthreshold solu-tions were proposed in order to improve the design of voltagereferences for both low power and low voltage operation [6–21]. In [9], the usage of transistors with different VT s inboth weak and strong inversion allows complete suppressionof mobility temperature dependence while consuming tens ofnanowatts operating below 1 V. A reference voltage based onSCM with different VT s was presented in [10], however currentsource transistors operating in moderate inversion restrain theminimum supply voltage. A temperature-compensated NMOSload in weak inversion was proposed in [11], which consumesless than 3 nW. The authors in [15] proposed a bulk-drivenscheme that allows low voltage and low power operation evenwith transistors operating in moderate inversion. A voltagereference based on the zero temperature coefficient (ZTC)point was proposed in [17], yet not only its moderate inversionoperation limits the minimum supply but also low poweroperation results in larger silicon area. Although presentinggood performance for some applications, the works describedabove require additional current references to bias the voltagereference core, thus increasing area and total power consump-tion. Here we refer to the aforementioned circuits as non-self-biased (Non-SB). Such circuits can consume units to tens ofnW whereas current leading-edge building blocks for ultra-low power (ULP) applications, e.g. miniature sensing systems,require reduction to the pW level range.

Just a few voltage references operating at such pW con-sumption levels have been proposed in the literature so far[12–14], [18–21], but these circuits do not offer a well definedcurrent to bias the voltage reference main core since theyare biased with the leakage current of a native MOS [12],[14], [18], [20], of a standard NMOS [13], [19] or of aPMOS transistor [14]. Even though leakage based strategyprovides a solution for pW voltage reference biasing, thecurrent generated by these structures cannot be simultaneouslymirrored through PMOS and NMOS branches for subsequentblocks.

In this work, we explore the usage of a self-biasing schemeto further reduce power consumption of subthreshold voltagereferences further providing an alternative for biasing subse-quent blocks. Two self-biased variants are presented. The first

mailto:[email protected]:[email protected]:[email protected]:[email protected]

2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS

M2

M3K2I

K1I

VREF1

(a)

M2

M3

K1I

VD2

VREF2

(b)

Fig. 1. Simplified scheme of the voltage reference variants.

one is a self-biased self-cascode MOSFET (SBSCM) and thesecond one is a temperature-compensated self-biased NMOS(SBNMOS) active load in weak inversion. Results show that,by employing the proposed approach, power consumption andsilicon area can be remarkably reduced when compared tonon-self-biased solutions, while staying among the best lowpower all-CMOS voltage references in the literature.

This paper is organized as follows: Section II presents theoperation principle of the proposed circuit and its variants;Section III discusses the key design considerations of the pro-posed structure; Section IV reports the prototype measurementresults; compensation after fabrication process is presentedin Section V; Section VI compares the obtained results ofthe proposed circuits with other voltage references published.Finally, the paper conclusions are drawn in Section VII.

II. OPERATION PRINCIPLE

The simplified circuit schematics of both proposed voltagereferences are shown Fig 1. In both cases, the SCM [6] iscomposed of transistors with different threshold voltages: M2is a high-VT transistor (3.3 V) and M3 is the standard one(1.8 V). The threshold voltage values specifically used in thispaper are derived from the target process herein used for ICprototyping, but the design principle itself is applicable toother CMOS processes as well.

A. Unified Current Control Model

Since the circuit under study is based on subthresholdMOSFET operation aiming for low power consumption, atransistor model appropriate for the weak inversion regionmust be used. According to the Unified Current Control Model(UICM) [23], the drain current of a MOSFET can be describedas the superposition of a forward (IF ) and a reverse (IR) currentcomponents

ID = IF − IR = IS(i f − ir) (1)where IS = ISQS, S is the transistor aspect ratio W/L and

W and L are the channel width and length, respectively. Theinversion coefficients i f and ir are the forward and reversenormalized currents; ISQ = µC′oxn

φ2t2 is the sheet normalization

current, which is process related, µ represents the carrier

mobility, n the subthreshold slope factor, C′ox is the gatecapacitance per unit area, and φt = kT/q the thermal voltage.The relationship between the normalized currents and voltagesis given by

VG−VT −nVS(D)nφt

=√

1+ i f (r)−2+ ln(√

1+ i f (r)−1)

(2)

where VG, VS and VD are the gate, source and drain voltagesreferenced to the bulk terminal, and VT is the threshold voltage.

From expressions (1) and (2), the drain current of a longchannel NMOS transistor operating in WI (i f �1) is given by

ID = 2eIS exp(

VG−VTnφt

)[exp(−VS

φt

)− exp

(−VDφt

)](3)

in which, for VD ≥ 3 ∼ 4φt the drain current becomesalmost independent of the drain voltage expressed inside thebrackets in (3). Such current saturation at low drain-to-sourcevoltages is observed in long channel MOSFETs, in which thedrain-induced barrier lowering effect (which affects the short-channel VT by raising the drain voltage) is negligible.

B. Self-Biased Self-Cascode Voltage Reference - SBSCM

As Fig. 1(a) shows, VREF1 is generated through the self-cascode MOSFET (SCM) connection of M2 and M3 whichhave the same gate-to-bulk voltage. The SCM, in turn, isbiased by two current branches that allow independent controlof the inversion coefficient of M2 and M3. The generation ofa voltage reference through the SCM is a good choice for lowpower since it can operate at very low current levels.

Usually, the bottom transistor of the self-cascode (M2)is considered to be in triode. However, since the value ofVREF1(VD2) is expected to be much greater than 4φt , M2is considered to be saturated in both cases of Fig. 1. Thedrain currents in Fig. 1(a) can be estimated through (1)-(2).Supposing that M2 and M3 are saturated (ir2,3 = 0), bothoperate in WI (i f 2,3 � 1) and, with all voltages referencedto their bulk terminals, which are connected to ground, theycan be written as

ID2 = 2eIS2 exp(

VG2−VT 2n2φt

)(4)

ID3 = 2eIS3 exp(

VG3−VT 3n3φt

− VREF1φt

)(5)

Since ID2 =(K1+K2)I, ID3 =K1I and VG2 =VG3, the voltagereference of Fig. 1(a) is given by

(6)VREF1 =

VT 2 −VT 3n3

+φtn3

ln(

In3S3(K1 + K2)n2

In2S2Kn31

)+

n2 − n3n3

φt ln(

I2e

)Therefore, the SCM of Fig. 1(a) provides an output voltage

reference that is mainly defined by the difference between thethreshold voltages of the 3.3 V and 1.8 V transistors, as shownin (6). The second component in (6) is PTAT and depends

DE OLIVEIRA et al.: PICOWATT, 0.45-0.6 V SELF-BIASED SUBTHRESHOLD CMOS VOLTAGE REFERENCE - PRE-PRINT 3

Mc

M2

M3

M1

M5M4 M6

VREF1

VDD

ID1

(a) SBSCM

M4

M2

M3

M1

M6M5

VREF2

VD2

VDD

ID1

(b) SBNMOS

Fig. 2. Schematic of the proposed voltage references.

on geometric and process parameters only. Additionally, itcan also be seen that a last PTAT component is added whichdepends on the bias current (I) and results from the differenceof subthreshold slope factors (n) of the transistors M2 and M3,which have different threshold voltages.

For the SCM to operate with a current as low as possible,the bias current I is derived from the SCM output voltage itselfthrough a feedback path, as in the current reference proposedin [11]. Hence, our voltage reference circuit herein proposed iscalled a self-biased self-cascode MOSFET (SBSCM) voltagereference.

The schematic of the proposed SBSCM voltage referenceis shown in Fig. 2(a) where M2 and M3 compose the SCM,and M1 defines the current reference ID1. The SBSCM uses ahigh-VT transistor for M1 (for which the nominal supply canbe as high as 3.3V), since the target is a sub-nA bias current.The PMOS transistors form the current mirror and define thecurrent ratios K1 = S5/S4 and K2 = S6/S4. Additionally, pathsK1 and K2 provide an alternative way for a trimming schemeto compensate TC for fabrication variations, as it will bepresented further in section V. The Mc transistor implementsa cascode current source that can be used to improve theline sensitivity (LS) at the cost of increasing the minimumsupply voltage, making its usage conditional on the targetperformance. In the fabricated version of the SBSCM, the coregenerated current is simply the drain current of M1 withoutthe use of Mc.

The core generated current of the proposed circuit is simplythe drain current of M1

ID1 = 2eIS1 exp(

VREF1−VT 1n1φt

)(7)

By replacing (7) in (6), and defining ε = 1− n2−n3n1n3 , theSBSCM generated voltage reference is now given by

(8)VREF1 =

VT 2 −VT 3n3ε

+φt

n3εln

((K1 + K2)n2 I

n3S3 I

n2−n3S1

In2S2Kn31

)

+

(n3 − n2n1n3ε

)VT 1

The threshold voltage has an approximately linear negativedependence on temperature that can be expressed as [24]

VT (T ) =VT (T0)−αT (T −T0) (9)

where VT (T0) is the threshold voltage at room temperatureand αT is the first derivative of the threshold voltage withrespect to temperature.

Replacing (9) in (8) and setting ∂VREF1∂T = 0, the optimalratio between aspect rations S3 and S2 of M3 and M2,respectively, can be expressed as(

Sn33Sn22

)OPT

=Kn31 I

n2SQ2

In3SQ3(K1 + K2)n2 In2−n3S1

× exp[

qk

(n1(αT 2 − αT 3)− (n2 − n3)αT 1

n1

)](10)

From expressions (8)-(10) the temperature compensatedvoltage reference is given by

(11)VREF1 =

VT 2(T0)−VT 3(T0)n3ε

+

(n3 − n2n1n3ε

)VT 1(T0)

+ T0

(n1(αT 2 − αT 3)− (n2 − n3)αT 1

n1n3ε

)As shown by (11) the proposed SBSCM provides at its

output a reference that is mainly defined by the differencebetween threshold of the 3.3 V and the 1.8 V transistors, sincethe αT term is negligible at room temperature.

C. Self-Biased NMOS Load Voltage Reference - SBNMOS

With the expression of the SBSCM at hand, the analysis ofthe SBNMOS output (VREF2) can be simplified. As Fig. 1(b)shows, the NMOS load voltage VREF2 is simply voltage VG2,which is

VREF2 =VT 2 +n2φt ln(

ID22eIS2

)(12)

The temperature behavior of (12) can be compensated sinceits first term is CTAT and its second, PTAT.

Fig. 2(b) presents the complete circuit where all transistoroperate in WI. Besides, M1, which is a 3.3 V transistor, definesthe bias current, M4 acts as a cascode to shield M1 from supplyvoltage variations, and transistors M5 and M6 act as a currentmirror thus defining K1 = S6/S5. The necessity of using thecascode transistor M4 arises from the fact that the LS of VREF2is directly dependent on the LS of the current source.

From the circuit of Fig. 2(b), through expressions (4)-(12),considering VD2 =VREF1 with K2 = 0, and knowing that ID2 =K1ID1, VG2 = VG3 = VREF2, β = n2n1n3 and γ = n2 +β(n2− n3),the resulting output voltage is given by

VREF2 = VT 2(β + 1)− β(VT 3 + n3εVT 1) + φt ln

Kγ1IγS1IS3 n2n1IS2n2(β+1)

(13)

Considering the linear approximation of VT presented by(9) and replacing it into (13), and again setting ∂VREF2∂T = 0,


the optimal S2 ratio for temperature compensation can beexpressed by

S2OPT =(K1IS1)

γn2(β+1) IS3

1n1(β+1)

ISQ2

× exp(

qk

[αT 2(β + 1)− β(αT 3 + n3εαT 1)

n2(β + 1)

])−1(14)

Thus, by satisfying (14), the temperature compensated VREF2is now expressed as

(15)VREF2 = VT 2(T0)(β + 1)− β [VT 3(T0) + n3εVT 1(T0)]+ T0 [α2(β + 1) + β(α3 + n3εα1)]

Since the generated current (ID1) also depends on M2, theoutput reference voltage is expected to depend to depend onits threshold voltage VT 2 by a factor higher than 1 (i.e. β+1),as represented in the first term of (15). Thus, the proposedcircuit provides a reference voltage that depends on thresholdvoltages of M1, M2 and M3, being VT 2 the major contributor.

It is important to notice that, for expressions (10) and (14),if µ1 ≈ µ2 ≈ µ3 ≈ µ is assumed, temperature dependent terms(

µ φ2t

2

)of the specific currents (ISQ) cancel each other. For this

reason, the ISQ temperature dependency is not considered inthis analysis.

III. DESIGN CONSIDERATIONS

A. Current Consumption Minimization

As depicted in Fig. 2(a) the total current consumed by theSBSCM circuit is given by

IDD1 = ID1(1+K1 +K2) (16)

Since the ratios S3 and S2 set a fixed temperature com-pensated reference voltage, and its value is applied to thegate of M1, the generated current will be defined only by theratio S1. Therefore, the current consumption can be minimizedby setting S1 to the smallest possible ratio (WMIN/LMAX), atthe cost of temperature coefficient degradation, and also byreducing K1 and K2 current gains. To further reduce ID1 thethird branch can be eliminated (K2 = 0) and thus temperaturecompensation can be made by increasing S3/S2. In this case,the trade-off between power consumption and M2,3 area willdepend on the threshold voltage temperature slope (αT ).

The total current consumption of the SBNMOS circuit (Fig.2(b)) is simply (16) with K2 = 0. It is straightforward thatthe decrease of the bias current ID1 depends on the reductionof both S1 and VD2, which can be reduced by increasing S2while reducing S3. Yet this strategy is not practical since theS2 ratio for optimal temperature compensation defined by (14)implies that S2 must also be reduced for a S1,3 reduction.Thus, for a small S1 ratio, S3 ratio must increase to reduce thecurrent consumption while keeping a reasonable temperaturecoefficient.

B. Minimum Supply Voltage

Proper operation of the proposed circuits under the assump-tions made in the previous sections requires the definition ofa minimum supply voltage. This value is set to the minimumvoltage needed to make both circuits as independent as pos-sible of VDD variations. In order to satisfy this condition, thesaturation condition must be guaranteed. In the subthresholdregion, the current of a MOS saturates when its drain-to-sourcevoltage is greater than 3 to 4 times the thermal voltage, i.e.,VDS ≥ 3∼ 4φt . Hence, in SBSCM without Mc, we have

VDD1MIN =max{

8φt + 250 mV︷︸︸︷VDS5 +VDS3 +VREF1,

4φt + 250 mV︷︸︸︷VDS6 +VREF1}

(17)

Considering that the drain-to-source voltage (VDS) of alltransistors must be at least 4φt and that from (8) the roughlyexpected voltage reference value is around 250 mV, theresulting minimum supply voltage will be around 450 mVaccording to (17). This value can be further reduced by usingdevices M2 and M3 with closer VT values, thus reducing VREF1.

From (13), the expected value for the SBNMOS voltagereference is around 390 mV. Estimating the minimum VDDsupply as done previously, the minimum for the SBNMOSwould be simply VREF2 +4φt . From measurement results, theobserved minimum supply voltage was 0.6 V. This is becauseVREF2 depends directly on the minimum supply voltage to driveVD2 high enough to create the bias current ID1. Therefore,the minimum supply voltage for the SBNMOS will have anadditional of 4φt to the value expected by only consideringthe voltage drop paths.

C. Supply Voltage Sensitivity

The sensitivity of a reference voltage with respect to supplyvoltage variations is commonly evaluated through the linesensitivity (LS) parameter. The LS is defined as

LS =∆VREF

∆VDD×VREFµ×100% (18)

in which ∆VDD is the VDD range of operation, ∆VREF(VREFMAX−VREFMIN) is the absolute difference of the refer-ence voltage in the VDD range considered and VREFµ is themean value of the voltage reference for the ∆VDD range. Theoptimization of the LS lies on the minimization of ∆VREF.Therefore, for both circuits of Fig. 2 this can be done byreducing currents gains K1 and K2 (the last one only for theSBSCM).

The line sensitivity of SBSCM can be substantially reduced(around 10× or more) by adding the transistor Mc at the costof increasing the minimum supply voltage from 0.45 V to 0.6V. Mc acts as a cascode device with an output impedancemuch larger than that of M1. Accordingly, Mc shields M1from supply voltage variations, thus improving the LS. Thesimulation results of the TC sensitivity with respect to VDDfor the SBSCM with and without Mc are shown in Fig. 3.Typical simulations of the SBSCM without Mc present a TCof 7 ppm/oC at minimum supply voltage (0.45 V) while the


0 0.5 1 1.5 2 2.5 3 3.50

20

40

60

80

100

120

VDD (V)

TC

(ppm

/oC

)without Mcwith Mc

Fig. 3. Comparison of the simulated TC supply voltage dependence with andwithout Mc transistor.

1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.60

100

200

300

400

500

(Sn33 /Sn22 ) and S2

TC

(ppm

/oC

)

SBSCMSBNMOS

Simulated Optimal

Eq. (10)

Eq. (14)

Fig. 4. Simulated transistors sizing for optimal TC.

maximum TC is less than 70 ppm/oC at 3.3 V. The additionof Mc results in a TC lower than 10 ppm/oC for all voltagesupply range at the cost of increasing the minimum VDD to0.6 V.

The channel length modulation was neglected in this circuitdesign since this effect is not relevant for MOS transistorsoperating in subthreshold, where drain output impedance de-pends mainly on drain-induced barrier lowering effect (DIBL).DIBL is significantly reduced by increasing the channel length,therefore the high impedance transistors (SBSCM: M1, M5 andM6; SBNMOS: M1, M4 and M6) were designed with large Lto minimize the LS of the proposed circuits.

D. Sizing for Optimal Temperature Compensation

Fig. 4 represents the simulated TC as function of transistorratios for both SBSCM and SBNMOS. The simulation wasperformed by properly sizing all other transistors besides M2and varying its W/L ratio.

The calculated optimum ratios of (Sn33 /Sn22 ) (for SBSCM)

and S2 (for SBNMOS) are 1.34 and 1.78 respectively, aspredicted by (10) and (14). As can be seen in Fig. 4 the sim-ulated optimal ratios of the same parameters are 1.4 and 1.92respectively. The proximity between calculated and simulatedvalues validates the proposed approach. Taking into accountthe previous considerations as well as layout regularity, theproposed circuits were sized as presented in Table I.

TABLE ITRANSISTORS SIZING FOR SBSCM AND SBNMOS.

Transistor Size (W/L)SBSCM SBNMOSM1 1/10 4×4/10M2 2×8/10 2×9.6/10M3 2×11/10 4/2M4 2×6/10 2×4/10M5 2×6/10 2×5/10M6 4×6/10 2×5/10

64 µm

32.7

µm

M1, M2, M3

M4, M5, M6

M1, M2, M3, M4

M5, M6

39 µm

46µm

SBNMOS

SBSCM

Fig. 5. Chip photo of the proposed voltage references and their layouts.

IV. MEASUREMENT RESULTS

The proposed CMOS voltage references were fabricatedin a standard 0.18-µm CMOS process. The chip photo andthe layout of the proposed circuits are shown in Fig. 5. Thetotal occupied areas are 0.0020 mm2 and 0.0017 mm2 forthe SBSCM and SBNMOS, respectively. Measurements wereperformed using a Keysight 4156C Semiconductor ParameterAnalyzer for DC biasing and voltage/current measurement. Athermal chamber was used for temperature control. Power Sup-ply Rejection (PSR) was measured using a Keysight B2961ALow Noise Power Source and a Keysight MSO9104A scope.A total of 24 chips from the same batch were packaged inceramic [25] and measured.

Fig. 6(a) shows the measured results of the supply voltagedependence for average samples of both proposed circuits at 20oC. As reported, the SBSCM starts to operate at 0.45 V supply,while the SBNMOS at 0.6 V supply. The average measuredline sensitivity (LS) from VDDMIN to 3.3 V was 0.15 %/V(SBSCM - Fig. 6(b)) and 0.11 %/V (SBNMOS - Fig. 6(c)).

The spread of VREF across the 24 measured samples of bothcircuits at 20 oC and minimum supply voltage are presentedin Fig. 7. The VREF mean reference voltages for the SBSCMand SBNMOS are 225.3 mV and 378 mV, respectively, andthe VREF variation coefficient (σ/µ - where σ and µ are thestandard deviation and mean value) are 0.63 % and 0.8 %,respectively.

The simulated and measured temperature sensitivity from0 oC to 120 oC for both circuits are shown in Fig. 8. The


0 0.5 1 1.5 2 2.5 3 3.50

0.1

0.2

0.3

0.4

Supply Voltage (V)

V RE

F(V

)SBSCMSBNMOS

(a) VREF×VDD

0.5 1 1.5 2 2.5 3 3.5

225

225.2

225.4

225.6

225.8

226

226.2

226.4

226.6

VDD (V)

V RE

F1(m

V)

(b) VSBSCM [0.45-3.3 V]

0.5 1 1.5 2 2.5 3 3.5378

378.2

378.4

378.6

378.8

379

379.2

VDD (V)

V RE

F2(m

V)

(c) VSBNMOS [0.6-3.3 V]

Fig. 6. Measured VREF supply voltage dependence.

221 222 223 224 225 226 227 2280

1

2

3

4

5

6

VREF1 (mV)

Sam

ples

µ = 225.3 mVσ = 1.42 mV

(a) SBSCM

370 372 374 376 378 380 382 3840

1

2

3

4

5

6

7

VREF2 (mV)

Sam

ples

µ = 378 mVσ = 3 mV

(b) SBNMOS

Fig. 7. Distribution of VREF of the 24 samples @ 20 oC and VDDMIN .

temperature coefficient (TC) is evaluated using the following

0 20 40 60 80 100 120210

220

230

240

250

260

270

280

290

Temperature (oC)

V RE

F1(m

V)

Typical SimulationAverage Measured

+3σ

-3σ

(a) SBSCM

0 20 40 60 80 100 120320

340

360

380

400

420

440

Temperature (oC)V R

EF2

(mV

)

Typical SimulationAverage Measured

+3σ

-3σ

(b) SBNMOS

Fig. 8. Average measured and typical simulated temperature behavior showingthe ±3σ range.

expression:

TC =VREFMAX−VREFMIN

(TMAX−TMIN)VREF27 oC×106 (19)

A TC between 68 ppm/oC and 150 ppm/oC, with a meanof 104 ppm/oC was measured from the 24 samples in the caseof the SBSCM, as shown in Fig. 8(a), while for the SBNMOSthe mean measured TC was 495 ppm/oC. The simulated worstcase TCs at minimum supply voltage across all corners were65 ppm/oC and 136 ppm/oC for the SBSCM and SBNMOS,respectively. The difference between simulated and measuredbehaviors may be partially caused by the inaccuracy of theBSIM3v3.2 model for the temperature behavior in deep weakinversion [26].

Fig. 9 shows the measured temperature behavior of thepower consumption for different values of VDD for both cir-cuits. Since they are biased with the subthreshold current, thepower consumption of the references increases exponentiallywith temperature. The SBSCM consumes typically 54.8 pWat 0.45 V and 27 oC and reaches a maximum of 8.6 nWat 3.3 V and 120 oC as shown in Fig. 9(a). The SBNMOSmeasured typical (0.6 V and 27 oC) and maximum (3.3V and 120 oC) power consumption are 184 pW and 24.2nW, respectively, as reported in Fig. 9(b). Simulated resultsof typical and maximum power consumption were 93 pWand 12.5 nW, respectively, for the SBSCM, while for theSBNMOS they were of 350 pW and 41.6 nW. Some dis-


0 20 40 60 80 100 120

0

2

4

6

8

10

Temperature (oC)

Pow

er(n

W) VDD = 0.45 V

VDD = 1.4 VVDD = 2.35 VVDD = 3.3 V

(a) Power consumtion of SBSCM

0 20 40 60 80 100 1200

5

10

15

20

25

Temperature (oC)

Pow

er(n

W) VDD = 0.6 V

VDD = 1.5 VVDD = 2.4 VVDD = 3.3 V

(b) Power consumtion of SBNMOS

Fig. 9. Measured temperature dependence of the power consumption fordifferent values of supply voltage.

crepancy between measured and simulated power consumptionis expected for both circuits. The SBSCM measured outputvoltage was around 25 mV less than that from simulation,which means that its consumption was also smaller than thatpredicted by simulations. The measured SBNMOS outputvoltage presented a CTAT behavior, indicating that the circuitis not biased with sufficient current to compensate the NMOSactive load temperature dependence, thus reducing the powerconsumption.

Fig. 10 presents the measured PSR for both circuits atminimum supply voltage and 100 Hz resulting -44 dB forthe SBSCM and -47 dB for the SBNMOS. Worst case PSRfrom 10 Hz to 10 kHz are -44.5 dB (SBSCM) and -45 dB(SBNMOS). PSR measurements were done with a high inputimpedance buffer presenting a total input capacitance of about4 pF.

Measured start-up time for VDD from 0 V to 3.3 V was 92ms and 32 ms, for the SBSCM and SBNMOS, respectively.This time increases by 10× when the voltage supply goes from0 V to VDDMIN .

V. TRIMMING ANALYSISIt is well known that sensitivity to process variations of

circuits with transistors in subthreshold increases dramatically.Due to the exponential I-V characteristics of MOS transistor inweak inversion, any small variation in threshold voltage causes

101 102 103 104−56

−54

−52

−50

−48

−46

−44

−42

−40

Frequency (Hz)

PSR

(dB

)

SBSCMSBNMOS

Fig. 10. Measured PSR for both proposed circuits @ VDDMIN.

an exponential change in drain current. Voltage referencesoperating at such region are very much process dependentand present a large spread of both output reference voltageand TC [7], [11], [12]. These variations can be compensatedthrough trimming techniques. From expressions (8) and (13),process variations of the generated reference voltages can becompensated by either increasing or decreasing the currentgains K1 and K2 through a digital control.

From the corner simulations presented in Fig. 12, theSBSCM and SBNMOS are expected to have a ∆VREF at roomtemperature of approximately ±6% and ±8%, respectively. Aspresented in [27], the number of bits of the trimming circuitis determined by the following expression

BITS≥ln(

VFSVLSB

+1)

ln(2)(20)

where VLSB is the least significant bit voltage and VFS is thefull-scale voltage.

The trimming circuit must be designed to cover the entireoutput voltage variation range while a reasonable VLSB mustbe chosen in order to reduce the spread of VREF, compensat-ing the output voltage for a target TC [12]. Therefore, thetrimming circuit is designed to cover the maximum rangeat room temperature while having a small VLSB for fine TCcompensation. Thus, for SBSCM, choosing VFS = 6%VREF1and VLSB = 0.25%VREF1 lead to a 5-bit trimming circuit.

The SBNMOS can be adjusted by increasing or decreasingthe current gain K1, which is equivalent to adding or sinkingcurrent at the reference voltage node. This can be achieved byusing a current-trimming technique [15], where the trimmingcircuit can cover all the variation of the output voltage atroom temperature. Defining VFS = 8%VREF2 and using thesame 5 bits as for the SBSCM, lead to VLSB = 0.3%VREF2.The schematic of the 5-bit trimming circuit of the proposedvoltage references is shown in Fig. 11.

The simulation of the trimming circuit, as well as the vari-ation of the output voltage with process corners, is shown inFig. 12. For both circuits, the increase/decrease of the currentgain is defined by the control bits B[4:0], where B[4] is a sign


Mc

M2

M3

M1

M5M4 M6

VREF1

B[0] B[3]

B[4]

B[0] B[3]

B[4]

VDD

(a) SBSCM

M4

M2

M3

M1

M6M5

VREF2

B[0] B[1] B[2] B[3]

B[4]

B[0] B[1] B[2] B[3] B[4]

VREF2

VDD

(b) SBNMOS

Fig. 11. 5-bit trimming scheme for the proposed circuits.

0 20 40 60 80 100 120

230

240

250

260

270

Temperature (oC)

V RE

F1(m

V)

tt ff ssfs sf VREF27 oC

10000 11000 00000 01000 01111Trimming Code

(a) SBSCM

0 20 40 60 80 100 120

340

360

380

400

420

Temperature (oC)

V RE

F2(m

V)

tt ff ssfs sf VREF27 oC

01111 01000 00000 11000 10000Trimming Code

(b) SBNMOS

Fig. 12. Simulated 5-bit trimming range for the proposed circuits.

bit that determines the direction of the resulting trim to theoutput voltage, and B[3:0] are the binary codes proportionallycontrolling the current mirror gains [16]. As clearly shown byFigures 12(a) and 12(b), the proposed trimming circuits cancover all process variations.

Even though the trimming circuits were not fabricated dueto silicon access restrictions, they can be emulated with theassistance of the measurement equipment, since each DC chan-nel of Keysight-4156 can perform a precision programmable

0 20 40 60 80 100 120245

250

255

260

265

270

275

280

Temperature (oC)

V RE

F1(m

V)

Sample 1Sample 2Sample 3Sample 4Sample 5

(a) SBSCM

0 20 40 60 80 100 120446

448

450

452

454

456

458

460

462

464

Temperature (oC)

V RE

F2(m

V)

Sample 1Sample 2Sample 3Sample 4Sample 5

(b) SBNMOS

Fig. 13. Measured temperature dependence of VREF for five samples aftertrimming emulation.

current source at the same time it measures the node VREF. Thisemulation can be made by increasing or decreasing the currentat the voltage reference node through the following process: 1)By processing the measured data of a given sample through amathematical software, an optimal temperature-compensatedVREFOPT is obtained; 2) Experimentally, at 27 oC a current(IT ) is sunk or applied to the reference node of the processedsample in order to achieve the same value as VREFOPT inthis temperature; 3) The generated currents of the proposedcircuits increase exponentially with temperature, hence the


TABLE IICOMPARISON WITH PUBLISHED LOW POWER CMOS VOLTAGE REFERENCES

Specification [9] [10] [11] [12]a [13] [14] [15]a [17]a [18]a This WorkSBSCM SBNMOSTechnology (µm) 0.35 0.35 0.18 0.13 0.18 0.18 0.18 0.35 0.18 0.18VDD (V) 0.9-4 1.1-4 0.45-2 0.5-3 0.15-1.8 1.2-2.2 0.45-1.8 0.9-3 1.4-3.6 0.45-3.3 0.6-3.3VREF (mV) 670 96.6 263.5 176 17.69 986.2 118.41 713 1250 225.3 256.6a 378 457.1aTemp. Range (oC) 0-80 -20-80 0-120 -20-80 0-120 -40-85 -40-85 -20-80 0-100 0-120TC (ppm/oC) 10 11.4 142 29 1462 124 59.4 26 31 104 72.4a 495 11.6aLS (%/V) 0.27 0.09 0.44 0.036 2.03 0.38 0.033 0.3 0.31 0.15 0.11PSR @ 100Hz (dB) -47 -60 -45 -51 -64 -42 -50.3 - -41 -43.9 -46.8Power (pW) 36,000 22,000 2,600 29.5 26.1 114 15,600 2,970 35 54.8 147a 184 664aArea (mm2) 0.045 0.0189 0.045 0.0093 0.0012 0.0048 0.0132 0.054 0.0025 0.002 0.0017FoMb (oC3/W×mm2) 0.0004 0.002 0.0009 1.25 0.315 0.23 0.0013 0.0025 3.68 1.26 1.1

aAfter trimming; b1021;

10−11 10−10 10−9 10−8 10−71017

1018

1019

1020

1021

1022

47.5× power

[9]

[10]

[11]

[12]

[13]

[14]

[15][17]

[18]

Power (W)

FoM

(oC

3 /W×

mm

2 )

Non-SBLeakage basedSBSCMSBNMOS

improvement

(a)

10−3 10−2 10−11017

1018

1019

1020

1021

1022

[9]

[10]

[11]

[12]

[13] [14]

[15]

[17]

[18]

7.75× area

Silicon Area (mm2)

FoM

(oC

3 /W×

mm

2 )

Non-SBLeakage basedSBSCMSBNMOS

improvement

(b)

Fig. 14. FoM comparison between the proposed circuits and prior works with respect to (a) power and (b) silicon area.

applied/sunk IT trimming current must follow this behavior.Using the obtained IT from the previous step as starting point,the current that must be applied to the other temperature pointsis achieved by approximating it with a function that increasesexponentially.

The measured results after the trimming emulation, as ex-plained before, for five randomly selected samples at minimumsupply voltage are shown in Fig. 13. The measured TCs withtrimming emulation for the 5 samples of the SBSCM were34, 60.7, 75.4, 100 and 93 ppm/oC, while for the SBNMOSthey were 13.2, 16, 7.25, 9 and 12.7 ppm/oC. The TCs forthe SBNMOS were expected to be lower when comparing tothose from the SBSCM since the latter circuit presented a moredefined CTAT behavior. The TC and power consumption were72.4 ppm/oC and 147 pW for the SBSCM, and 11.6 ppm/oCand 664 pW for the SBNMOS. Since the trimming circuitswere not included in the fabricated references due to siliconaccess restrictions, the presented emulation approach can helpvalidate the process compensation trimming scheme that wasproposed.

VI. COMPARISON WITH PUBLISHED WORKS

The performance of a voltage reference circuit is quantifiedby many specification parameters as presented in the previoussections, meaning that the performance comparison amongdifferent circuit designs and approaches is a complex task. For

this reason a Figure of Merit (FoM) can be defined to providea comparative number that represents the overall performanceof a given design.

A FoM that considers the main performance parameters of avoltage reference, such as temperature range, TC, power, andsilicon area, can be expressed as [28]

FoM =(TMAX−TMIN)2

TC×Power×Area (21)

First-order compensated voltage references usually presenta parabola-like curve across temperature, meaning that as thetemperature goes far from the reference point, typically roomtemperature, the output reference voltage temperature sensitiv-ity increases. Therefore, the temperature range (TMAX−TMIN)is squared in the FoM expression proposed, benefit designswhere a wider temperature range is covered. The productbetween TC, power at room temperature and silicon area mustbe as low as possible, meaning that resistorless solutions arebenefited since integrated resistors tend to occupy large areaswhen designed for low currents.

Table II and Fig. 14 summarize the performance of theSBSCM and the SBNMOS in comparison with publishedlow power CMOS voltage references. When compared withthe non-self-biased works (Non-SB), the proposed circuitspresented a 47.5× and 7.75× of power and area improvement,respectively, while having the best FoM performance. As


Fig. 14 explicitly shows, besides presenting better FoM thanNon-SB, the leakage based solutions have the smallest areaand power consumption. The performance of both circuitsproposed concerning power, area, and FoM are among thebest in literature. Although [18] presents a higher FoM, itsminimum supply voltage is 1.4 V, which is not suitable forlow voltage applications. The SBSCM 0.45 V operation is inthe range of ultra-low voltage applications.

VII. CONCLUSION

Low power and low voltage self-biased subthreshold CMOSvoltage references were herein presented. The voltage ref-erences are generated with the usage of NMOS deviceswith different threshold voltages. The power consumptionis remarkably reduced by combining subthreshold operationwith a self-biased scheme. By employing this approach, twovariants of this design were presented: the SBSCM and theSBNMOS. A trimming scheme for both circuits was proposedand analyzed. The proposed circuits were fabricated in astandard 0.18-µm CMOS process. The measurement resultsfrom 24 samples show that both circuits can operate at 0.45/0.6V minimum supply voltage, consuming 55/184 pW at roomtemperature. The calculated FoM reveals that both circuitsare among the best in recent literature. The performance ofthe proposed circuits makes them suitable for extreme power-constrained applications such as battery voltage supervisorsfor IoT systems.

REFERENCES[1] Y. Shi, M. Choi, Z. Li, Z. Luo, G. Kim, Z. Foo, H. S. Kim, D. D.

Wentzloff, and D. Blaauw, “A 10 mm3 Inductive Coupling Radio forSyringe-Implantable Smart Sensor Nodes,” IEEE Journal of Solid-StateCircuits, vol. 51, no. 11, pp. 2570–2583, Nov 2016.

[2] R. Mohan, S. Zaliasl, G. G. E. Gielen, C. V. Hoof, R. F. Yazicioglu, andN. V. Helleputte, “A 0.6-V, 0.015-mm2, Time-Based ECG Readout forAmbulatory Applications in 40-nm CMOS,” IEEE Journal of Solid-StateCircuits, vol. 52, no. 1, pp. 298–308, Jan 2017.

[3] S. Bandyopadhyay, P. P. Mercier, A. C. Lysaght, K. M. Stankovic, andA. P. Chandrakasan, “A 1.1 nW Energy-Harvesting System with 544pW Quiescent Power for Next-Generation Implants,” IEEE Journal ofSolid-State Circuits, vol. 49, no. 12, pp. 2812–2824, Dec 2014.

[4] Y. Lee, S. Bang, I. Lee, Y. Kim, G. Kim, M. H. Ghaed, P. Pannuto,P. Dutta, D. Sylvester, and D. Blaauw, “A Modular 1 mm3 Die-StackedSensing Platform With Low Power I2 C Inter-Die Communication andMulti-Modal Energy Harvesting,” IEEE Journal of Solid-State Circuits,vol. 48, no. 1, pp. 229–243, Jan 2013.

[5] Y. Chen, N. Chiotellis, L. X. Chuo, C. Pfeiffer, Y. Shi, R. G. Dreslinski,A. Grbic, T. Mudge, D. D. Wentzloff, D. Blaauw, and H. S. Kim,“Energy-Autonomous Wireless Communication for Millimeter-ScaleInternet-of-Things Sensor Nodes,” IEEE Journal on Selected Areas inCommunications, vol. 34, no. 12, pp. 3962–3977, Dec 2016.

[6] E. Vittoz and O. Neyroud, “A Low-Voltage CMOS Bandgap Reference,”IEEE Journal Solid-State Circuits, vol. 14, no. 3, pp. 573–579, June1979.

[7] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V SubbandgapReference Circuits for Nanowatt CMOS LSIs,” IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1530–1538, June 2013.

[8] O. E. Mattia, H. Klimach, and S. Bampi, “Resistorless BJT bias andcurvature compensation circuit at 3.4 nW for CMOS bandgap voltagereferences,” Electronics Letters, vol. 50, no. 12, pp. 863–864, June 2014.

[9] G. D. Vita and G. Iannaccone, “A Sub-1-V, 10 ppm/oC, NanopowerVoltage Reference Generator,” IEEE Journal of Solid-State Circuits,vol. 42, no. 7, pp. 1536–1542, July 2007.

[10] W. Yan, W. Li, and R. Liu, “Nanopower CMOS sub-bandgap referencewith 11 ppm/oC temperature coefficient,” Electronics Letters, vol. 45,no. 12, pp. 627–629, June 2009.

[11] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, “A2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS VoltageReference,” IEEE Journal of Solid-State Circuits, vol. 46, no. 2, pp.465–474, Feb 2011.

[12] M. Seok, G. Kim, D. Blaauw, and D. Sylvester, “A Portable 2-TransistorPicowatt Temperature-Compensated Voltage Reference Operating at 0.5V,” IEEE Journal Solid-State Circuits, vol. 47, no. 10, pp. 2534–2545,Oct 2012.

[13] D. Albano, F. Crupi, F. Cucchi, and G. Iannaccone, “A Sub-kT/q VoltageReference Operating at 150 mV,” IEEE Transactions on Very LargeScale Integration (VLSI) Systems, vol. 23, no. 8, pp. 1547–1551, Aug2015.

[14] Q. Dong, K. Yang, D. Blaauw, and D. Sylvester, “A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracyfor nW systems,” in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), June 2016, pp. 1–2.

[15] Z. Zhu, J. Hu, and Y. Wang, “A 0.45 V, Nano-Watt 0.033 % LineSensitivity MOSFET-Only Sub-Threshold Voltage Reference With noAmplifiers,” IEEE Transactions on Circuits and Systems I: RegularPapers, vol. 63, no. 9, pp. 1370–1380, Sept 2016.

[16] Y. Wang, Z. Zhu, J. Yao, and Y. Yang, “A 0.45-V, 14.6-nW CMOSSubthreshold Voltage Reference With No Resistors and No BJTs,” IEEETrans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 7, pp. 621–625, July2015.

[17] P. Luong, C. Christoffersen, C. Rossi-Aicardi, and C. Dualibe,“Nanopower, Sub-1 V, CMOS Voltage References With Digitally-Trimmable Temperature Coefficients,” IEEE Transactions on Circuitsand Systems I: Regular Papers, vol. 64, no. 4, pp. 787–798, April 2017.

[18] I. Lee, D. Sylvester, and D. Blaauw, “A Subthreshold Voltage ReferenceWith Scalable Output Voltage for Low-Power IoT Systems,” IEEEJournal of Solid-State Circuits, vol. 52, no. 5, pp. 1443–1449, May2017.

[19] A. C. de Oliveira, J. G. Caicedo, H. D. Klimach, and S. Bampi, “0.3 VSupply, 17 ppm/oC 3-Transistor Picowatt Voltage Reference,” in 2016IEEE 7th Latin American Symposium on Circuits Systems (LASCAS),Feb 2016, pp. 263–266.

[20] D. Cordova, A. C. de Oliveira, P. Toledo, H. Klimach, S. Bampi,and E. Fabris, “A 0.3 V, High-PSRR, Picowatt NMOS-Only VoltageReference using Zero-VT Active Loads,” in 2016 29th Symposium onIntegrated Circuis and Systems Design (SBCCI), Sept 2016.

[21] A. C. de Oliveira, D. Cordova, H. D. Klimach, and S. Bampi, “A 0.45 V,93 pW Temperature-Compensated CMOS Voltage Reference,” in 2017IEEE 8th Latin American Symposium on Circuits Systems (LASCAS),Feb 2017, pp. 1–4.

[22] L. Lu, B. Vosooghi, L. Dai, and C. Li, “A 0.7 V Relative TemperatureSensor With a Non-Calibrated ± 1 oC 3 σ Relative Inaccuracy,” IEEETransactions on Circuits and Systems I: Regular Papers, vol. 62, no. 10,pp. 2434–2444, Oct 2015.

[23] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design UsingAll-Region MOSFET Modeling, 1st ed. New York, NY, USA: Cam-bridge University Press, 2010.

[24] Y. Tsividis, Operation and Modeling of the MOS Transistor. New York,NY, USA: McGraw-Hill, Inc., 1987.

[25] F. Sebastiano, L. Breems, K. A. A. Makinwa, S. Drago, D. Leenaerts,and B. Nauta, “Effects of packaging and process spread on a mobility-based frequency reference in 0.16-µm CMOS,” in 2011 Proceedings ofthe ESSCIRC (ESSCIRC), Sept 2011, pp. 511–514.

[26] L. Magnelli, F. Crupi, P. Corsonello, and G. Iannaccone, “A Sub-1V Nanopower Temperature-Compensated Sub-threshold CMOS VoltageReference with 0.065 %/V Line Sensitivity,” International Journal ofCircuit Theory and Applications, vol. 43, no. 4, pp. 421–426, 2013.

[27] J. P. M. Brito, S. Bampi, and H. Klimach, “A 4-Bits Trimmed CMOSBandgap Reference with an Improved Matching Modeling Design,” in2007 IEEE International Symposium on Circuits and Systems, May2007, pp. 1911–1914.

[28] W. Sansen, “Lecture Notes on Advanced Analog Circuit Design,” , imecAcademy, 2015.


Arthur Campos de Oliveira (S’13) received theB.Sc. degree in electrical engineering from the Fed-eral University of Pampa, Brazil, in 2015, and theM.Sc. degree in microelectronics from the FederalUniversity of Rio Grande do Sul, Brazil, in 2017.

His current research interests include analog sub-threshold circuit design, power management, sensingsystems and energy-efficient VLSI design.

David Cordova (S’12) received the B.Sc. degree inelectronics engineering from the Pontifical CatholicUniversity of Peru, Lima, Peru, in 2007, and theM.Sc. degree in microelectronics from the FederalUniversity of Rio Grande do Sul, Porto Alegre,Brazil, in 2014. He completed the IC-Brazil programwith RFIC design specialization at the IC BrazilTraining Center 1, Porto Alegre, Brazil, in 2010.He is currently working toward the Ph.D. degreewith the Conception Group on IMS and Universitéde Bordeaux, Bordeaux, France, where he works on

frequency generator circuits toward 5G.His research interests include analog and RF IC design in CMOS technolo-

gies.Mr. Cordova is a student member of the IEEE Circuits and Systems Society

and the IEEE Solid-State Circuits Society

Hamilton Klimach (S’03-M’09) received theB.Eng. and M.Sc. degrees in electrical engineeringfrom the Federal University of Rio Grande do Sul(UFRGS), Porto Alegre, Brazil, in 1988 and 1994,respectively, and the Dr.Eng. degree in ElectricalEngineering from the Federal University of SantaCatarina (UFSC), Florianopolis, Brazil, in 2008.

Since 1990 he is a full Professor at the ElectricalEngineering Department of Federal University ofRio Grande do Sul, where he was the Head of theDepartment from 2010 to 2011, and a Dr.Eng. and

M.Sc. advisor in the Microelectronics Graduate Program (PGMicro) of thesame university. Since 2016 he is the local Coordinator of the Training Center1 of the brazilian design training program (IC Brazil Program) where he isalso serving as Lecturer since 2009.

His research interests are in the areas of analog, mixed-signal and RF ICdesign, in semiconductor device modeling and in variability modeling. He isa member of the IEEE Circuits and Systems Society.

Sergio Bampi (M’86) received the B.Sc in elec-tronics and the B.Sc. in physics from the FederalUniversity of Rio Grande do Sul (UFRGS, 1979),and the M.Sc. and Ph.D. degrees in electrical engi-neering from Stanford University (USA) in 1986.

He joined the UFRGS Microelectronics group atInformatics Institute in 1986, where currently isa full professor. He serves as Ph.D. advisor andprincipal investigator in the Microelectronics andComputer Science Programs at UFRGS since 1988.He was a Distinguished Lecturer (2009-10) of IEEE

Circuits and Systems Society, worked as the technical Director of theMicroelectronics Center CEITEC (2005-2008) and is the past President of theFAPERGS Research Funding Foundation. He was a visiting research professorat Stanford University (1998-99), and director of the National SupercomputerCenter (1993-96).

His research interests are in the area of IC design and modeling, mixedsignal and RF CMOS circuits design, architectures and SoCs for image andvideo processing, nano-CMOS devices, ultra-low power digital CMOS design,dedicated complex algorithms and architectures. He has co-authored morethan 350 papers in these fields and in MOS devices, circuits, technologyand CAD. He was Coordinator of the Graduate Program in Microelectronicsat Federal University UFRGS (2003-2007), and since 1989 has advised 41Master´s and 18 Ph.D. thesis. He served as Chair of IEEE LASCAS 2013,track-Chair of ICM 2010/2011, IEEE/IFIP VLSI-SoC 2011/2012 Symposium,and other adhoc and consulting roles. He chaired the Program Committee ofSBCCI and SBMICRO conferences and was the chair of the Ibero-AmericanMicroelectronics Conference (1995), the X and XVIII Symposium on Inte-grated Circuit Design (1997 and IEEE SBCCI 2005), the X Congress of theBrazilian Microelectronics Society, and of the II Brazilian MicroelectronicsSchool (1992). Served as president of scientific societies SBPC and SBMICRO(2002-2004), and Council member of IEEE SSC Society, Brazilian ComputerSociety and Brazilian Society for Advancement of Science. He is an IEEEmember of CASS, SSCS, and ED Societies, and member of CEDA.

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IntroductionOperation PrincipleUnified Current Control ModelSelf-Biased Self-Cascode Voltage Reference - SBSCMSelf-Biased NMOS Load Voltage Reference - SBNMOS

Design ConsiderationsCurrent Consumption MinimizationMinimum Supply VoltageSupply Voltage SensitivitySizing for Optimal Temperature Compensation

Measurement ResultsTrimming AnalysisComparison With Published WorksConclusionReferencesBiographiesArthur Campos de OliveiraDavid CordovaHamilton KlimachSergio Bampi

Picowatt, 0.45-0.6 v Self-Biased Subthreshold CMOS Voltage ...Sergio Bampi Universidade Federal do...

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