Physical Verification Signoff for DDR IP using PVS

Tobing Soebroto, Cadence IP GroupPresented at Signoff SummitNov 21, 2013

Physical Verification Signoff for DDR IP using PVS

2 © 2013 Cadence Design Systems, Inc. All rights reserved.

Agenda

1. Cadence IP Factory

2. Signoff Challenges

3. Why PVS for Physical Verification

4. Conclusions


Growing IPG with the Best

Pre - 2013

Expansion to existing Analog Team

Acquisition of key IP

Tensilica joins IPG

Cosmic joins IPG

Q3+ 2013 …

Evatronix to join IPGDenali joins Cadence Systems

Cadence Confidential

Denali acquisition - strong memory IP and models Analog team – expands analog capabilities IP acquisition provides key mobile IP technology Tensilica adds innovative and system level IP to portfolio Cosmic expands AMS IP and provides key mobile IP Evatronix will complement USB and memory IP offering

Q2 2013

Building a comprehensiv

e ecosystem…

partners, customers, foundries,

design houses, etc.


Cadence IP FactoryNext Gen SoCs

DRAMCtrl.+PHY

DDR1/2

DDR3

DDR4

LPDDR1/2

LPDDR3

LPDDR4

Wide I/O

HMC

NANDCtrl.+PHY

SD/SDIO Host

1/2/3/3.2/4

SDIO Device

MMC/eMMC4.2/4.4/5.0

ONFi 1/2/3

Toggle 1/2

Async

EthernetMAC+PCS+PHY

10/100 MAC

1G MAC

10G MAC

40G MAC

100G MAC

AVB

Auto Ethernet

10G–KR

PCIeCtrl.+PHY

Gen1

Gen2

Gen3

Gen3L1 substate

USBCtrl.+PHY

USB 2

USB 3

HSIC

USB 3 PHY

USB 2 PHY

USB OTG

AMSAnalog Mixed

Signal

ADC/DAC

AFE

PLL/DLL

PVT mon

SERDES

PowerMgmt

MIPICtrl.+PHY

DSI

CSI

DigRF

M-PCIe

PCIe PHY

BIF

D-PHY

M-PHY

SLIMbus

USB Hub

Wide I/O 2

UHS – I/II

SENSORS


Cadence DDR PHY IPSilicon proven, highest performance PHY

• Robust PHY IP ready for system integration– First to market – DDR2400, WideIO, LPDDR4– Complete jitter analysis and char. reports– Verified with leading memory models– System Design-In Kit : PCB modeling: SI/PI analysis

• HS PHY – Scalable to 3200 performance– Per bit de-skewing, per rank leveling– DDR3/4/3L, LPDDR2/3/4 support– DDR2400 silicon characterization

• LP PHY– Up to 1600 performance– Lowest power/area, integrated hard controller– DDR2/3/3L LPDDR2/3 support– High volume production

• IP around your chip, not other way round– 8 bit hardened slices + IO + PLL integration ready– Flexible IO ordering, bump pitch, form factor– Custom, fully hardened PHY option

Synthesizable PHY logic

IO Pads

Delay lineon DQS

Per-bit DQDelay line

DRAM interface

HS PHY

DFI 2.1/3.1 Interface


• With shorter design cycle, IP is a key component of the design realization

• Foundry– Foundries like to work with IP companies and make available the

widest range of IP to win new design customers

• Cadence IP Group– Be first to market with differentiated IP

– Cover a broad range of customer needs

– Get as many customers fast

Motivation to Develop IPs Early


• Foundry:– The IP has to developed early and be available to customers,

before the new designs come for production– This requires the infrastructure to be ready early for IP companies,

like rule decks, techfiles, PDKs,…

• Cadence IP Group– IP products support multiple new foundries – Tools used must support leading edge technologies/process nodes

for example, TSMC 16FF technologies– Must help to improve productivity and achieve fastest time to market– Design impact needs to be understood

– Mixed Signal flows– Reduce debugging time– Reduce Iterations/loops to signoff

Signoff Challenges to Overcome


• Previously– PVS rule decks were available by request to the foundry

and Cadence foundry team

• Now– PVS is available online at selected foundries early with

other signoff tools

• Decision:– PVS is our plan of record where decks are available and

has been used on numerous tapeouts

Primary Requirement: Rule Deck AvailabilityPVS History and Status


We liked the tight integration of PVS in Virtuoso• No translation of Verilog to CDL. Verilog is

read directly.• No manual translation of dfII to CDL.• No need prepare mapping for probing in

dfII.• No need to merge netlists.• No need to create scripts.

Mixed Signal Design ChallengesMixed verilog and schematic view

Convert Verilog to CDL

Convert dfII to CDL + mapping

One pass submission

Batch oriented submission

PVS GUI submission Significant gain for mixed analog/digital schematics

Merge netlists


• Mixed Signal Designs input schematic is mix of dfII, Verilog and CDLs:

• PVS LVS Debug Environment eases probing by providing:

– From error report to dfII.

– From error report to Verilog

– From error report to CDL/SPICE

Reduced Probing TimeProbing from error report to dfII.

Probing from error report to Verilog

Probing from error report to CDL/SPICE


PVS ISL Facilitates One-Pass Short IsolationDebugging Time savings

• Conventional way of debug– Hundreds shapes

of net 122 to investigate

• PVS ISL reduced the number of shapes to debug to ~10 and exactly pointed to the short.


• Conventional way of debug: thousands shapes of ground net ‘gnd’ to investigate.

• PVS ISL reduced number of shapes to debug to ~30 and exactly points to short.

We start Debugging While Run is in ProgressAs soon as first results are available


• PVS is the plan of record for Cadence IP group• PVS has many technologies which ease and fasten signoff

time to tapeout– In-design applications which reducing debugging time– Timing aware dummy metal fill– Interactive DRC with IPVS– Advanced node technology support

• Cadence IP group have completed numerous production tape-outs with PVS

Conclusion

Physical Verification Signoff for DDR IP using PVS

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