PHYSICAL REVIEW APPLIED 11, 054009...

PHYSICAL REVIEW APPLIED 11, 054009 (2019)

Voltage-Controlled Topological Spin Switch for Ultralow-EnergyComputing: Performance Modeling and Benchmarking

Shaloo Rakheja,1,* Michael E. Flatté,2 and Andrew D. Kent31Department of Electrical and Computer Engineering, New York University, Brooklyn, New York 11201, USA

2Department of Physics and Astronomy and Optical Science and Technology Center, University of Iowa, Iowa

City, Iowa 52242, USA3Center for Quantum Phenomena, Department of Physics, New York University, New York, New York 10003, USA

(Received 21 February 2018; revised manuscript received 11 January 2019; published 3 May 2019)

A voltage-controlled topological spin switch (VTOPSS) that uses a hybrid topological insula-tor–magnetic insulator multiferroic material is presented that can implement Boolean logic operationswith sub-10-aJ energy per bit and an energy-delay product on the order of 10−26 J s. The device uses atopological insulator, which has the highest efficiency of conversion of the electric field to spin torque yetobserved at room temperature, and a low-moment magnetic insulator that can respond rapidly to a givenspin torque. We present the theory of operation of the VTOPSS, develop analytic models of its perfor-mance metrics, elucidate performance scaling with dimensions and voltage, and benchmark the VTOPSSagainst existing spin-based and CMOS devices. Compared with existing spin-based devices, such as all-spin logic and charge-spin logic devices, the VTOPSS offers 10–70 times lower energy dissipation and70–1700 times lower energy-delay product. With experimental advances and improved material proper-ties, we show that the energy and energy-delay product of the VTOPSS can be lowered to a few attojoulesper bit and 10−28 J s, respectively. As such, the VTOPSS technology offers competitive metrics com-pared with existing CMOS technology. Finally, we establish that interconnect issues that dominate theperformance in CMOS logic are relatively less significant for the VTOPSS, implying that highly resistivematerials can indeed be used to interconnect VTOPSS devices.

DOI: 10.1103/PhysRevApplied.11.054009

I. INTRODUCTION

Spin-based logic and memory devices use nanomag-nets as digital spin capacitors to store and manipulateinformation [1]. Typically, spin-polarized electric currentsor magnetic fields are used to control the magnetizationvector of nanomagnets while reading and writing infor-mation [2]. Compared with their charge-based counter-parts, spin-based devices offer nonvolatility of informa-tion and superior logical efficiency (i.e., fewer devicesto implement a given Boolean function [3]). However,most spin-based devices suffer from high energy dissipa-tion resulting from a large electric current density on theorder of 106 A/cm2 required to reorient the magnetiza-tion vector [4,5]. Such large current densities not only leadto excessive Joule heating in the device but could causeelectromigration issues in metallic interconnects [6]. Atthe same time, reversal of metallic ferromagnetic bodiesusing antidamping spin-transfer torque (STT) proceeds ona timescale on the order of hundreds of picoseconds to a

*[email protected]

few nanoseconds [7]. As such, existing spin-based deviceshave an energy-delay product (EDP) that is 1000 to 10 000times larger than that of their CMOS counterparts [8].

To harness the full potential of spintronics technology,it is imperative to develop methods for energy-efficientand fast manipulation of the magnetic order parame-ter. Actuation methods, such as voltage control of mag-netic anisotropy and coercivity, use of magnetoelectricand exchange coupling in multiferroic-ferromagnetic het-erostructures, and charge-carrier-density-mediated ferro-magnetism control, have been investigated [9,10]. Yet,these effects are generally weak at room temperature,which limits their practical use. For example, full 180◦reversal of a ferromagnet via the magnetoelectric effectrequires the assistance of electric currents or magneticfields or can be accomplished with the resonant pulsedswitching mode, which requires precise pulse timing[11–14]. Magnetoelastic effects that are used to tune themagnetic properties of thin films via epitaxial strain orpiezoelectric substrates are generally observed in low-aspect-ratio nanomagnets [15,16]. However, in high-aspect-ratio nanomagnets it is difficult to use strain effectsto tune the magnetic properties.

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RAKHEJA, FLATTÉ, and KENT PHYS. REV. APPLIED 11, 054009 (2019)

A promising research direction is “topological spin-tronics,” which has been driven by the demonstration ofefficient room-temperature spin-charge conversion in het-erostructures with a topological insulator (TI) interfacingwith a ferromagnetic metal [17]. The key property respon-sible for this advance is the combination of large spin-orbit-coupling (SOC) strength and time-reversal symmetrythat leads to the formation of helical Dirac surface statespossessing an inherent spin-momentum locking [18–21].The distinctive feature of TIs is that even without carriersnear the chemical potential in the bulk, the spin Hall con-ductivity can be finite and significantly larger than that ofheavy metals such as Pd, Pt, and W [22–24].

Here we use electric fields across a TI, resulting incoherent transport of spins across the material, to gen-erate a spin torque on the magnetization of an adjacentmagnetic insulator (MI) layer [25]. Unlike for a ferro-magnetic metal, there is no shunting of electric currentin the MI layer and current is restricted to flow on thesurface of the TI layer. Furthermore, the MI can inducea gap in the TI surface states, rendering the TI surfacestate insulating, which is (counterintuitively) beneficial forthe device operation. The spin-based device, a voltage-controlled topological spin switch (VTOPSS), decouplesthe elements of a magnetoelectric material [26], allowingus to simultaneously optimize the choice of both TI andMI materials, thereby enabling ultralow-energy comput-ing. One of the most important properties of the MI layeris its low damping [27,28], which is highly desirable indevice applications where switching is realized throughmagnetization precession, as in a VTOPSS.

The transduction principle of charge current to magne-tization to charge current is an old one, used prominentlyby Datta and Das [29] in their first spin-FET proposal, andalso in later spin FETs, such as the device proposed by Halland Flatté [30] in 2006. A similar transduction principle isalso used in the charge-spin logic (CSL) device proposedby Datta et al. [31,32] in 2012. Unlike prior device pro-posals, the VTOPSS is purely electric field driven suchthat charge-to-magnetization transduction is accomplishedwithout the flow of electric current. The magnetoelectriceffect in the VTOPSS allows efficient charge-spin con-version at the TI-MI interface solely by application of anelectric field across the TI. Given that a TI possesses a largespin Hall conductivity even without carriers near the chem-ical potential in its bulk, it avoids the dissipative chargecurrents present in heavy-metal layers [33] used as spingenerators in the CSL device. Although both devices use amagnetic tunnel junction (MTJ) to read the magnetizationinformation, in the VTOPSS the free layer of the MTJ isexchange-coupled to the MI layer, making the read processmore robust against the effects of thermal noise.

The remainder of this paper is organized as follows.In Sec. II, the physics of operation of the VTOPSS ispresented. In Sec. III, analytic models of performance

metrics of the VTOPSS are presented, followed by bench-marking results against existing spin- and charge-baseddevices in Sec. IV. In Sec. V, implementation of univer-sal Boolean logic gates and the logical efficiency of theVTOPSS resulting from its innate polymorphism are high-lighted. Section V summarizes the key findings of thiswork while also offering an outlook on future researchdirections.

II. PHYSICS OF OPERATION

The evolution of the wave functions of the full bandsof the TI, under the influence of an electric field, pro-duces coherent transport of spins across the material [34],which can be used to efficiently manipulate the magneti-zation state of an adjacent magnetic layer [35]. The chargeHall conductivity and bulk dissipative charge currents van-ish or are small in the TI, but the spin Hall conductivityis finite and can be much larger than that of a large-SOCmetal [36]. A TI has the highest efficiency of conversionof the electric field to spin torque yet observed at roomtemperature [37,38]. Hybrid TI-MI structures decouplethe constituent features of a multiferroic material, allow-ing independent optimization of both components of theresponse of magnetization to an electric field (i.e., genera-tion of spin torque from the electric field and response ofthe magnetic moments to the spin torque).

The total Berry curvature of a full band measures theintegrated correlation between spin and orbital degrees offreedom. For a so-called trivial insulator this correlationintegrates to zero across the entire full band. Thus, if at oneregion of the Brillouin zone the wave functions of the bandhave spin and orbit correlated preferentially parallel, therewill be another region of the zone in which the wave func-tions are correlated preferentially antiparallel. An exampleis the valence band in a trivial direct-gap semiconductor,such as GaAs, which is of p-orbital character, for whichthe wave functions near the valence maximum are heavy-hole states, with spin and orbit degrees of freedom parallel,whereas at energies below the split-off energy, the spinand orbit degrees of freedom are preferentially orientedantiparallel.

TIs differ from these trivial insulators in that this spin-orbit correlation does not integrate to zero. The spin-orbitcorrelation is described quantitatively by the Berry curva-ture of the band, and thus the electronic ground state in a TIpossesses a nonzero integrated Berry curvature. The spinHall conductivity in the clean static limit, evaluated as thelinear response of the spin current to an electric field by theKubo approach, depends directly on the Berry curvature:

σyx = e�V∑

n

∑

k

fnk�znk, (1)

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VOLTAGE-CONTROLLED TOPOLOGICAL SPIN SWITCH. . . PHYS. REV. APPLIED 11, 054009 (2019)

where e is the elementary charge, � is the reduced Planckconstant, V is the volume of the system, k is the crystalmomentum, n is a band index, and is �znk is the Berrycurvature,

�znk = 2∑

n�=n′Im

〈unk|j zy |un′k

〉 〈un′k|vx|unk〉(Enk − En′k)2 . (2)

Here the Fermi-Dirac function fnk ensures that the sum isover filled states, corresponding to all the filled bands atzero temperature. The spin-current and velocity operators,ĵ ji and v̂i, are

ĵ ji =�

4(v̂iσj + σj v̂i), �v̂i = ∇ki Ĥ , (3)

where σj is the spin operator along direction j and Ĥ is theHamiltonian of the material. The current and velocity oper-ators are evaluated between the states with Bloch functionsunk and un′k with energies Enk and En′k, respectively.

As the integrated Berry curvature of the full band doesnot vanish for a TI, and the spin Hall conductivity isdirectly related to the total Berry curvature of the filledstates of the TI, even without any carriers near the chemi-cal potential in the bulk, the spin Hall conductivity doesnot vanish. This characteristic clearly identifies the spincurrent involved as nondissipative until it encounters otherregions, such as an interface. Here we take advantage ofthis localized effect to drive the VTOPSS shown in Fig. 1.The device relies on the accumulation of spins at an inter-face, originating from the voltage (Vin) applied to the TI.The spin Hall conductivity for a TI can be as large as(or larger than) that of a large-SOC metal, but the dis-sipative longitudinal charge current will vanish for theTI. Thus, a TI provides the advantages of a large spinHall conductivity, but without the intrinsic dissipation ofa metallic material. The resulting spin current producedby the electric field on the TI generates a torque on thespin in the magnetic material through exchange couplingor antidamping torque. In the case of effective exchangecoupling, the torque forces the magnetization to precessand eventually reverse.

The spin current density created by application of anelectric field ETI is

Js = σyxETI. (4)The resulting magnetization dynamics of the ferromag-netic insulator can be described by the Landau-Lifshitz-Gilbert-Sloncewski equation in a macrospin limit [39]:

1γ ′

dm̂dt

= −μ0m̂ × Heff − αμ0m̂ ×(m̂ × Heff

)

− cexjsm̂ × p̂︸︷︷︸Field like torque

+ jsm̂ ×(m̂ × p̂)

︸︷︷︸Slonczewski torque

, (5)

V–

Vout

y

z

xV+V inGND

Topological insulatorMagnetic insulator

Fixed magnetFree magnet Exchange coupling

Write unitRead unit

FIG. 1. Copy and invert functions implemented with theVTOPSS. In the write unit, an input voltage signal applied acrossthe TI layer causes spin accumulation at the interface of the TIand MI layers, which exerts a spin torque on the magnetizationof the MI layer to reverse it. The read unit has a MTJ exchange-coupled to the MI layer that allows reading of the information inthe MI layer. The polarity of the output voltage can be changedon the fly by change of the polarity of the voltages V+ and V− onthe MTJ stack, allowing both inverting and noninverting logicto be realized with the same primitive/layout. Typical systemmaterials include Bi2Se3/(BixSb1−x)2Te3 as the TI, Y3Fe5O12,(Ni0.65Zn0.35)(Al0.2Fe0.8)O4, BaFe12O19, or Tm3Fe5O12 as theMI, (Co,Fe)B-MgO-(Co,Fe)B/Ru/CoFe/IrMn (synthetic antifer-romagnet) as the MTJ, and metallic or semiconducting nanointer-connects with effective resistivity less than 100 μ� cm as wires.GND, ground.

where m̂ is a unit vector in the magnetization direction,γ ′ = γ /(1 + α2), where γ is the gyromagnetic ratio, μ0is the vacuum permeability, and α is the Gilbert damp-ing coefficient. The last two terms describe a spin torquefrom a spin current polarized in a direction p̂, gener-ally perpendicular to the electric field and in the plane ofthe TI-MI interface. Js = 2MstMIjs, where Ms is the mag-netization of the MI layer and tMI is its thickness. (Weassume a thin ferromagnetic insulator with area in contactwith the topological insulator Aint and thickness tMI.) Thefirst spin-torque term describes the precession of the mag-netization about the spin-polarization direction, with anexchange-coupling parameter cex. (For an estimate of thisparameter, see Ref. [35].) This term is often referred to asa fieldlike interaction. The second spin-torque term char-acterizes the Slonczewski “antidamping” torque, a torquethat can oppose the dissipative term (the second term onthe right-hand side of the equation), leading to precessionalmagnetization dynamics and switching.

The effective field Heff characterizes the magneticanisotropy of the free layer. For a uniaxial magnet witheasy-magnetization direction in the y direction

Heff = 2Ebmy/(μ0MsVMI), (6)

where Eb is the energy barrier to magnetization reversaland VMI is the volume of the MI layer. The magnetization-switching mechanism depends on the orientation of the

054009-3


magnetic easy axis relative to the direction of spin polar-ization p̂. When the two are orthogonal, the switchingcan occur due to precession about the spin-polarizationdirection and can be very fast (less than 100 ps)[40–42]. However, typically precise electric pulse timingis required to ensure switching. When the spin polariza-tion is collinear with the easy-axis direction, the switchingis slower but the pulse time is not a critical parameter;in general, the write error rate decreases monotonicallywith either increasing pulse amplitude or increasing pulseduration [43]. The electric field polarity determines thesense of reversal (i.e., from my = 1 to −1 and vice versa).The threshold spin current density for antidamping spin-current switching follows from Eq. (5), Js,th = 4αEb/Aint.The antidamping switching mechanism is considered in theanalysis presented in Sec. III.

We note a key difference between the current in theVTOPSS and that in a STT device. In a STT device, thecurrent, carried by individual carriers, is parallel to theapplied electric field and Joule heating is produced. Thatcontrasts with our device, in which the current flows per-pendicular to the surface of the topological insulator (notalong it) and is perpendicular to the applied electric field,making it nondissipative. The current itself in the bulk ofthe topological insulator is carried by the full band (notindividual carriers), corresponding to a protected spin cur-rent similar to the quantized charge current in a quantumHall state, which cannot scatter. Moreover, the current inthe VTOPSS does not need to be on during the entireswitching cycle since we are using the spin accumulationthat results from the applied voltage to switch the device.

As shown in Fig. 1, the readout in the VTOPSS isaccomplished by exchange coupling a small section ofthe MI layer (storing information) to the free layer of aMTJ, which could operate with sub-100-mV supply volt-ages (V+ or V−) to generate sufficient output voltage (Vout)with intrinsic gain and the ability to fan out. This separatesthe robust information-storage aspect from the transduc-tion within a hybrid magnetoelectric device, allowing oneto probe the magnetization without disturbing the state.

While the device schematic in Fig. 1 shows the TI andthe MTJ integrated laterally on the MI layer, the layers canbe integrated vertically to achieve a smaller footprint ofthe device and higher integration density. The top view ofthe device for lateral and vertical integration schemes isshown in Fig. 2. In Sec. III, we highlight key differences inthe scaling behavior of delay and energy dissipation withdevice dimensions for both layouts. For the purpose of per-formance benchmarking in Sec. IV, we consider only thevertically integrated VTOPSS.

III. PERFORMANCE MODELING

In most spin-based devices, the operating speed is lim-ited by the time it takes to reverse the magnetization of

FIG. 2. Vertically integrated layers (left) and laterally inte-grated layers (right) in the VTOPSS. The interface area in thevertical layout is Aint = WMILMI, while that in the lateral layoutis Aint = WTILTI.

the metallic ferromagnetic layer, which is typically on theorder of 1 ns. Spin-based devices using the spin Hall effectin heavy metals, such as Pt, Pd, and W, require largeelectric fields in the heavy metal to generate sufficientelectric current to cause STT switching of nanomagnets.The VTOPSS takes advantage of the unique propertiesof TI and MI material systems to achieve the followingcriteria for energy-efficient logic applications: (i) non-volatility of operational states, (ii) fully-voltage-drivenswitching of the MI magnetization with voltages less than100 mV, (iii) absence of dissipative electric currents dur-ing the write process, and (iv) ultrafast switching of the MImagnetization due to its low Gilbert damping.

In this section, analytic models of latency and energydissipation of the VTOPSS are presented, followed by acomparison of metrics against those of existing spin-basedand charge-based devices. Analytic models are obtainedfor a uniaxial MI layer subjected to antidamping STTresulting from spin accumulation at the TI-MI interfacewhen the TI is subjected to an external electric field.Micromagnetic effects in magnetization reversal, such asreversed domain nucleation and expansion in the MI layer,are not considered in this paper. Experiments have shownthat such multidomain effects could lead to faster magne-tization reversal, particularly in the absence of defects andpinning sites in the magnet [44,45]. The essential physicsof magnetization reversal is determined by the transferof angular momentum (the total angular momentum thatneeds to be switched and the rate at which angular momen-tum can be changed by the interactions present). As such,the macrospin model provides the correct order of mag-nitude for magnetization-switching thresholds and timeseven in the presence of nucleation and reversed domainexpansion. Here we adopt the macrospin approximation,which affords analytic insight into the device performancelimits and can be used readily for the optimization ofdevice geometry and materials.

A. Device latency

To estimate VTOPSS latency, the rate of spin accumula-tion at the TI-MI interface must be calculated. For a given

054009-4


electric field (ETI) and spin Hall conductivity (σSHC) of theTI layer, the accumulation rate of interface spins is givenas

dnspinsdt

= σSHC�/2

ETI = σSHC�/2

VinWTI

, (7)

where Vin is the voltage applied across the TI layer and WTIis the width of the TI layer, measured along the y axis inFig. 1 and also marked in Fig. 2. For a given efficiency εof coupling of spins at the TI-MI interface and the mag-netic moment of the MI layer, the following condition issatisfied:

Nspins,MI = εnspinsAint, (8)

where Nspins,MI is the total number of spins in the MI layersubjected to spin torque due to the interface spin accumu-lation and Aint is the interface cross-section area. The totalnumber of spins in a magnetic body is given as

Nspins,MI = MsVMIμB

= 2EbμBHK

, (9)

where HK is the anisotropy field of the MI layer andμB = 9.3 × 10−24 J/T is the Bohr magneton. Assumingantidamping switching of the MI layer in the ballistic limit(JMI � Jth), the rate of spin accumulation at the interfacewill balance the rate of magnetization reversal of the MIlayer. Here JMI is the input spin current density in theMI layer, while Jth is the threshold spin current densityrequired for STT-induced magnetization reversal. In thiscase, the reversal time of the MI layer is [44]

τMI,0 = Nspins,MIεAintdnspins/dt

= 2eEb�μBHKσ0Vin

WTIAint

, (10)

where σSHC = σ0(�/2e). The interface area depends on thedevice layout as indicated in the caption for Fig. 2. TheSTT-driven reversal of the MI layer will be subject to ther-mal fluctuations, which could result in switching errors. Toaccount for switching errors (Perr), the switching delay ofthe MI layer is modified according to

τMI = τMI,0ηst, (11a)

ηst = −0.5 ln(

− ln(1 − Perr)4Eb/kBT

). (11b)

For Perr = 10−12 and Eb = 30kBT, the stochastic parame-ter ηst ≈ 16, which gives τMI = 16τMI,0. With new error-tolerant computing paradigms related to approximate andprobabilistic computing with spin-based devices, one maynot need such low error rates [46–48]. For Perr = 0.5, ηst ∼2.58. We choose ηst = 10 and Eb = 30kBT (Perr = 10−7)

for performance benchmarking in Sec. IV. These parame-ters (Eb = 30kBT and Perr = 10−7) allow us to have a fairand consistent comparison of the VTOPSS against existingspin-based devices, including all-spin logic (ASL), mag-netoelectric spin-orbit (MESO) logic, and CSL devices, inwhich the energy barrier of the magnetic layer is approxi-mately (5–40)kBT [31,49–51]. Issues pertaining to circuit-and system-level error analyses are beyond the scope ofthis work.

Increases in σSHC of the TI layer and the spin-couplingefficiency are particularly beneficial toward reducing thedevice latency. While the total latency of the device mustinclude the time needed to charge and discharge the devicecapacitance (sum of interconnect and TI input capaci-tance), the analysis presented in Sec. III E shows thatthe dominant time constant is due to the rate of spinaccumulation at the TI-MI interface.

B. Thermal stability

The reversal delay of the MI layer can be reduced bylowering of the energy barrier Eb; however, this comesat the cost of reduced thermal stability of the MI layer.The reversal time of a uniaxial magnet subjected only tothermal noise is given as [52,53]

τstable =√

π(α + α−1)

2γ HK√

eb0

(1 + 1

eb0+ 7

4e2b0

)eeb0 , (12)

where eb0 = Eb/kBT is the normalized energy barrier ofthe magnet. For α = 3 × 10−3, HK = 0.1 T, and eb0 =30, we find τstable = 3.39 × 104 s (0.392 days). The stabil-ity increases for α = 10−4, with τstable = 1.0171 × 106 s(11.8 days). For most computing applications with clockfrequency fclock = 3 GHz and activity factor αact = 10%(1%), a device will switch on average once per 3.3ns (33 ns). Over the device-relevant computational time(�t), the probability of error at a fixed τstable is Perr =1 − exp (−�t/τstable). For �t = 33 ns and τstable = 3.39 ×104 s, Perr = 9.73 × 10−13. As shown in Fig. 3, for eb0 =30, the error rate stays well under 10−10 for �t = 100 ns(corresponding to αact = 0.33% at fclock = 3 GHz). Theseresults quantitatively show that an energy barrier of 30kBTcould provide sufficient thermal stability for most comput-ing applications.

C. Minimum input voltage

The input voltage, Vin, across the TI is a critical param-eter that affects the dynamics and the switching time ofthe VTOPSS. The model in Eq. (11) is valid only whenJMI > 2Jth. Therefore, an estimate of the minimum inputvoltage Vmin,STin is found by considering JMI = 2Jth, which

054009-5


10–15 10–10 10–5 100

Error probability

5

10

15

20

25

30

35

40e b

0 = Eb/k BT

t = 100 nst = 10 ns

= 3 10–3

= 10–4

FIG. 3. Required energy barrier in a uniaxial magnet subjectedto a random thermal field for a given probability of error withina time duration �t.

results in

Vmin,STin =8eαEb�σ0

WTIAint

. (13)

From thermodynamic considerations, however, the min-imum input voltage will be limited by the Johnson-Nyquist (JN) noise. Considering that the output node ofthe VTOPSS can be represented as a low-pass RC fil-ter, the spectral density of the thermal noise is given asV2n = 4kBTReq, where Req is the equivalent resistance forcharging and discharging the output capacitor, Cout. To findthe total noise, we integrate the spectral density over thenoise bandwidth �f , which is given as

�f = 12π

∫ ∞

0

dω

1 + (ωReqCout)2 =

14ReqCout

. (14)

The total noise voltage across the output capacitor istherefore given as vmin,JNn =

√V2n�f =

√kBT/Cout.

If we combine the limits due to spin-torque reversal andJN noise in the system, the minimum input voltage for theVTOPSS is given as

Vminin = max(Vmin,STin , vmin,JNn ). (15)

For α = 3 × 10−3, Eb = 30kBT, WTI = 100 nm, Aint =50 × 100 nm2, and σ0 = 2 × 105 (� m)−1, we getVmin,STin ∼ 0.5 mV. For Cout ≈ 20 aF (sum of intercon-nect capacitance and capacitance of the fan-out TI layer),vmin,JNn ∼ 15 mV. Therefore, in this case, Vminin = vmin,JNn =15 mV. For Vin = 100 mV, � = 0.5, and ηst = 10, τMI =860 ps. The other parameters are the same as noted ear-lier. With larger spin Hall conductivity, we can expect thereversal delay of the VTOPSS to be well under 500 ps evenfor an error rate of 10−7.

D. Minimum read voltage

In the VTOPSS, the read unit is a MTJ stack coupledto the MI layer as depicted in Fig. 1. The read voltagesare labeled as V+ and V− and have the same magnitudebut opposite polarity; that is, V+ = Vread and V− = −Vread,where Vread is the magnitude of the voltage applied to theMTJ to read the magnetization state of the MI layer. Thesupply voltages are clocked such that the writing and read-ing of a given logic stage happen in concurrent cycles. Thevoltage generated at the output node Vout of the nth stagedrives the write unit of the (n + 1)th stage. The outputvoltage must meet the Vminin criterion in Eq. (15).

The equivalent-circuit model of the VTOPSS is shownin Fig. 4. The interconnect is modeled as a lumped RC net-work with Ric and Cic representing the total interconnectresistance and capacitance, respectively [54]. For a giveninterconnect length Lic, Ric = ricLic and Cic = cicLic, whereric and cic are the per-unit-length interconnect resistanceand capacitance, respectively. The per-unit-length inter-connect resistance ric = ρeff/Aic, where ρeff is the effectiveresistivity of the wire and depends on the material aswell as grain-boundary and sidewall carrier scatterings ininterconnects with scaled cross-section area [55], whileAic = 2W2ic is the cross-section area of the interconnectassuming that the interconnect thickness is twice the inter-connect width, Wic. The conductances of the parallel andantiparallel configurations of the free layer and the fixedlayer in the MTJ stack are denoted as GP and GAP, respec-tively. These conductances are typically determined fromtunneling-magnetoresistance (TMR) and resistance-area-product (RA) measurements of the MTJ structure. TMRis given as (GP − GAP)/GP, while the RA is given asAMTJ/(GP + GAP), where AMTJ is the cross-section area ofthe MTJ stack. For all results reported in this paper, AMTJ= Aint unless otherwise specified.

The capacitance of the TI layer is CTI, while the leakageof electric current through the TI is modeled with theleakage conductance GTI. The TI capacitance is given as

Cic

Ric

CTI GTI

Vout(t)

I3(t)V1(t)

I1(t) I2(t)GP GAP

V +(Vread) V −(−Vread)

FIG. 4. Equivalent electric circuit of the read unit of a stagedriving the write unit of the following stage. The MTJ stack con-ductances are given as GP (parallel) and GAP (antiparallel). Thetotal interconnect resistance and capacitance are Ric and Cic. TheTI layer is modeled as a leaky capacitor with capacitance CTI andshunt conductance GTI. The MTJ read voltages have the samemagnitude but opposite polarity.

054009-6


CTI = �0�rAint/W, where �0 = 8.85 × 10−12 F/m and �ris the static relative dielectric permittivity of the TI layer.For Bi2Se3, �r ≈ 110 [56]. The leakage conductance GTI =GsheetL/W, where Gsheet = ensμ [57], where ns and μ cor-respond to the density and the effective mobility of surfacecarriers, respectively.

The leakage in the TI layer results from the conductanceof topologically trivial and nontrivial surface states as wellas the bulk conductivity resulting from unavoidable self-doping effects [58]. Attempts to suppress bulk conductivityinclude thinning the TI layer until the surface contributiondominates or use of compensation doping to suppress freecarriers in the bulk. For example, in the work reported inRef. [59], copper doping was used in Bi2Se3 films to fullysuppress bulk states and decouple the surface states in sam-ples as thin as 20 nm. A sheet resistance of approximately1000 �/� at room temperature (300 K) was experimen-tally measured in a 20-nm-thick Bi2Se3 film, while thesheet resistance increased to 1400 and 3000 �/� in filmsof thickness 10 and 2 nm, respectively, in the same sam-ple. More recently, sheet resistances on the order of tens ofkilo-ohms per square have been experimentally achievedat room temperature in 5–60-nm-thick Bi2Se3 films grownon an insulating In2Se3/(Bi0.5In0.5)2Se3 buffer layer onsapphire substrates [60].

The time-domain response of the output voltage,obtained by our solving Kirchoff’s laws in the circuitshown in Fig. 4, is given as

Vout(t) = Vf(

1 − e− tτeq)

+ Vie−t

τeq , (16a)

Vf = �GGtVread

1 + RintGTI = νVread, (16b)

τeq = 1 + RintGtGt (1 + RintGTI)︸︷︷︸Req

Cout, (16c)

where �G = GP − GAP, Gt = GP + GAP, and Vf and Viare the final and initial voltages, respectively, at the outputnode. At the end of the read or write cycle, the voltage Voutis reset to 0 V. Therefore, for all results presented in thispaper, Vi = 0 V. The minimum read voltage required onthe MTJ stack to ensure correct functionality is obtainedby our equating Eqs. (15) and (16). Assuming that theread pulse duration is significantly greater than τeq, Vminreadis given as

Vminread = (1 + RintGTI)Gt�G

Vminin . (17)

In Fig. 5, the ratio of the minimum read voltage to the min-imum input voltage is plotted as a function of the TMR ofthe MTJ in the VTOPSS. The values of the TMR and theRA are taken from Ref. [61] and are reproduced in the inset

R (Ω m2)

Con

duct

ance

(Ω)

100 T (%)

100 T (%)

100

T (%

)

FIG. 5. Ratio of the minimum read voltage to the minimuminput voltage as a function of the TMR. The left inset shows thescaling of the TMR with the RA (experimental data taken fromRef. [61]). The right inset shows the impact of the TMR on thetotal conductance (Gt) and the differential conductance (�G) ofthe MTJ for two values of the cross-section area, AMTJ = 30 ×30 nm2 (solid line) and 50 × 50 nm2 (dashed line). Increasing theMTJ cross-section area increases all conductance values withoutaffecting the ratio of the minimum read voltage and the minimuminput voltage.

in Fig. 5. As the RA increases, the TMR increases in pro-portion and saturates at approximately 350% for RA greaterthan 1000 � μm2. The minimum read voltage needed toreliably read the state of the VTOPSS is approximately2Vminin for TMR in excess of 200% (dotted line in the mainplot). Assuming Vminin ≈ 15 mV (JN limit), Vminread ≈ 30 mV.While the cross-section area of the MTJ does not affect theVminread/V

minin ratio, the values of Gt and �G are affected sig-

nificantly by the MTJ cross-section area as shown in theinset on the right-hand side in Fig. 5.

E. Energy dissipation

The total energy dissipation consists of the energyrequired to charge and discharge the output node volt-age, Vout, and the direct path conduction between V+ andV−. Assuming that the read phase lasts for time τpulse,the energy supplied by the voltage V+ is given by thefollowing integral:

Eread =∫ τpulse

0dtI1(t)V+ =

∫ τpulse

0dt[I2(t) + I3(t)]V+,

(18)

where Ij (t) (j = 1,2,3) denotes the electric currentflowing in the j th branches as shown in Fig. 4,I2(t) = GAP[V1(t) − V−], and I3(t) = CoutdVout(t)/dt +GTIVout(t), where Cout = CTI + Cint is the net capacitive

054009-7


loading at the output node. By our substituting V1(t) interms of Vout(t) and using Eq. (16), the energy dissipationof the circuit is given by Eq. (19):

Eread = V2readGAPτpulse [1 + ν(1 + RintGTI)ζ ]︸︷︷︸Eread,1

+ νV2readGTIτpulseζ︸︷︷︸Eread,2

+ νV2readCout (1 + GAPRint)(1 − e−τpulse/τeq)

︸︷︷︸Eread,3

, (19)

where

ζ =[

1 − τeqτpulse

+ τeqτpulse

exp(

− τeqτpulse

)].

The term Eread,1 in Eq. (19) is dominated by the energy dis-sipation due to the MTJ leakage. The second term, Eread,2,is due to electric conduction through the TI, while the thirdterm, Eread,3, is due to the energy consumed in charging anddischarging the output-node capacitance.

To reduce the leakage through the MTJ, Gt should belower for a fixed TMR. Unfortunately, this will increaseτeq and therefore the net delay of the VTOPSS. For exam-ple, for rint = 1.25 × 107 �/m, Lint = 100 nm, TMR of222%, RA of 4.6 × 10−11 � m2, AMTJ = 50 × 50 nm2, andCout = 0.1 fF, τeq ≈ 1.85 ps. For TMR of 350% and RA of2.2 × 10−9 � m2, τeq increases to approximately 89 ps. Inthe latter case, the charging time of the output capacitancewill be comparable to the reversal delay of the MI layerand cannot be ignored. The parameter ζ in Eq. (19) willreduce below unity when τeq ∼ τMI (see the discussion inSec. IV A).

F. Dimensional scaling

The scaling of the performance metrics of the devicewith its dimensions depends on the interface area, Aint,which depends on the integration scheme adopted for thedevice (see layout options in Fig. 2.) Table I shows thescaling of the MI reversal delay and the energy dissipa-tion due to leakage for vertically integrated (option A) andlaterally integrated (option B) device layouts. We assume

that even as the cross-section dimensions of the MI layerare scaled, the energy barrier is fixed so that the thermalstability of the MI layer is not compromised with scaling.For a fixed value of the uniaxial energy density, this canbe achieved by appropriate variation of the thickness ofthe MI layer. Table I shows that for both layouts the speedof the writing mechanism in the VTOPSS scales inverselywith a relevant length scale. This length scale is the lengthof the MI layer (easy axis) for option A, in which layers arestacked vertically. In option B, the relevant length scale isequal to the length of the TI layer. Likewise, the energydissipation scales inversely with the width of the MI layerfor option A and with the width of the TI layer for option B.Even though for both layouts the performance (delay andenergy) scales inversely with an appropriate dimension,option B would be preferred due to its smaller footprint.In this layout the spin torque acts nearly uniformly acrossthe cross-section area of the MI layer, promoting (or lead-ing to) a more-uniform (or more-coherent) magnetizationreversal.

IV. PERFORMANCE BENCHMARKING

To benchmark the performance of the VTOPSS againstCMOS and existing spin-based devices, we first study theimpact of device design on VTOPSS latency, energy, andEDP. Results are reported only for the vertically integrateddevice layout. For all results, τpulse = τMI + τeq. Simula-tion parameters for all benchmarks are listed in Table IIunless otherwise noted. For CMOS logic at the 2020 Inter-national Technology Roadmap for Semiconductors (ITRS)technology node, the effect of local interconnects (copperlow-κ) on the performance metrics is considered.

A. Latency and energy dissipation

In Fig. 6 the reversal delay of the MI layer and the totaldelay of the VTOPSS are plotted versus the read voltageon the MTJ. We assume a stochasticity parameter ηst = 10to guarantee a switching error rate as low as 10−7. Ourresults show that sub-500-ps reversal delay of the MI layercan be achieved with Vread � 150 mV for σSHC = 2 × 105(� m)−1 and spin-coupling efficiency of 100%. A majorreduction in delay results from the use of a TI materialwith a larger spin Hall conductivity. At a read voltageof 150 mV and σSHC = 5 × 105 (� m)−1, the MI reversal

TABLE I. Performance scaling for the device layouts depicted in Fig. 13. In option A, layers are vertically stacked, while in optionB, layers are placed laterally. The energy dissipation due to the MTJ leakage scales as EMTJ ∝ AMTJ/ min(LMI, LTI).Layout Interface area Delay (Eb fixed) Energy (TI leakage)

Option A Aint = WMILMI τMI ∼ 1LMI(

WTIWMI

)ETI ∼ 1WMI

(LTILMI

)

τMI ∼ 1LMI if WTI and WMI are scaledproportionately

ETI ∼ 1WMI if LTI and LMI are scaledproportionately

Option B Aint = WTILTI τMI ∼ 1LTI ETI ∼1

WTI

054009-8


TABLE II. Material parameters used for conducting simulations and performancebenchmarking considering a vertically integrated device layout.

Parameter Value

Magnetic insulatorEnergy barrier, Eb 30kBTUniaxial magnetic anisotropy field, HK 0.1 TGilbert damping coefficient, α 3 × 10−3Stochasticity parameter, ηst 10 (300 K); 2.6 (0 K)Width of the MI layer, WMI 50 nmLength of the MI layer, LMI 100 nm

Topological insulatorSpin Hall conductivity, σSHC 5 × 105�/2e (� m)−1Sheet resistance of the TI, Rsheet 100 k�/�Relative dielectric permittivity of the TI, �r 110Efficiency of spin coupling at the TI-MI interface, ε 1.0Width of the TI layer, WTI 100 nmLength of the TI layer, LTI 100 nm

Interconnect and magnetic tunnel junctionEffective resistivity of the interconnect, ρeff 2.5 × 10−6 � mCapacitance per unit length of the interconnect, cic 1.6 pF/cmInterconnect length, Lic 100 nmInterconnect width, Wic 50 nmInterconnect thickness, tic = 2Wic (aspect ratio 2) 100 nmResistance-area product of the MTJ 2.2 × 10−9 � m2Tunneling magnetoresistance of the MTJ 350%Area of the MTJ, AMTJ 50 × 50 nm2

delay is approximately 273 ps for 100% spin-coupling effi-ciency. The effect of spin-coupling efficiency on the delayis examined in the inset in Fig. 6 at Vread = 150 mV. Fora practical spin-coupling efficiency of 50%, the delay ofthe VTOPSS is approximately 445 ps. Further reduction

0.05 0.1 0.15 0.2Vread (V)

0

0.5

1

1.5

2

2.5

3

3.5

puls

e (s

olid

line

) an

d M

I (da

shed

line

) (n

s)

0.2 0.4 0.6 0.80

2

4

6

puls

e (n

s)

σSHC = 5 × 105 (Ω m)−1

σSHC = 2 × 105 (Ωm)−1ε

σSHC = 5 × 105 (Ωm)−1

σSHC = 2 × 105 (Ωm)−1

Vread = 150 mV

delay 0.5 ns

FIG. 6. Switching delay of the VTOPSS read voltage for var-ious values of the spin Hall conductivity, σSHC, of the TI layer.We choose spin-coupling efficiency ε = 100%. Other simulationparameters are given in Table II. The inset shows the impact of εon the total delay of the device.

in delay can be achieved if the leakage through the MTJstack is eliminated by fabrication of MTJs with a higherTMR. Finally, as shown in Table I, increasing the lengthof the MI layer can help reduce the delay further; however,this reduction comes at the cost of lower device integrationdensity.

The effect of read voltage on the energy and EDP of thedevice is shown in Figs. 7(a) and 7(b). The total energydissipation scales nearly quadratically with the read volt-age. While Eread,3 scales as V2read, the product of τpulse andζ is nearly independent of Vread, which also makes thedominant components of energy dissipation (i.e., due tothe TI and MTJ leakage) scale as V2read [see Fig. 7(c)].Unlike CMOS technology, where the relationship betweenenergy dissipation and supply voltage is exactly quadratic,in the case of the VTOPSS, the relationship depends onthe values of various material and geometrical parametersof the device. For τeq ∼ τpulse, Eread scales as V2read; how-ever, the relationship changes to linear (i.e., Eread ∼ Vread)for τeq � τpulse. At a read voltage of 150 mV, the energydissipation of the VTOPSS for infinite sheet resistance(gapped surface states and negligible bulk conductivity) isas low as 3.5 aJ if the spin-coupling efficiency at the TI-MIinterface is 100%. This energy dissipation increases by2–3 orders of magnitude for Bi2Se3 thin films with a sheetresistance of 1–10 k�/� measured at room temperature asreported in Ref. [59]. The EDP of the VTOPSS increaseswith increase of the MTJ read voltage. At 150 mV, the

054009-9


0.05 0.1 0.15 0.210-210-1100101102103104

Solid ⇒ Rsheet = 1 kΩ/sqDashed ⇒ Rsheet = 10 kΩ/sq

Dashed-dotted ⇒ Rsheet → ∞0.05 0.1 0.15 0.2

0

0.5

1

Rsheet = 10 kΩ/sqSolid ⇒ ζ

Dashed ⇒ τeq/τpulse

P ED

(Js)

Edis

s(a

J)Ediss ∼ V 2read

Vread (V) Vread (V) Vread (V)0.05 0.1 0.15 0.2

Solid ⇒ Rsheet = 1 kΩ/sqDashed ⇒ Rsheet = 10 kΩ/sq

Dashed-dotted ⇒ Rsheet → ∞

PED ∼ Vread

10−29

10−27

10−25

10−23(c)(b)(a)

FIG. 7. Effect of read voltage on (a) energy dissipation, (b) EDP, and (c) τeq and ζ .

EDP decreases from 9.5 × 10−26 J s at Rsheet = 10 k�/�to 9.5 × 10−28 J s when there is no leakage through the TI.

Figure 8 shows the contribution of various terms inEq. (19) to the overall VTOPSS energy dissipation. Forlarge TI conductance, corresponding to a large value ofthe sheet conductance of the TI, the net energy dissipationis limited by the TI leakage [Eread,2 in Eq. (19)]. Assum-ing that the TI conductance can be suppressed such thatGsheet → 0, we see that the energy dissipation is limitedby the MTJ leakage [Eread,1 in Eq. (19)] for low values of

(a)

(b)

10–7 10–6 10–5 10–4 10–310–2

100

102

104

10–7 10–6 10–5 10–4 10–310–2

100

102

104

Eread

Eread

Eread,1

Eread,1

Eread,2

Eread,2Eread,3

Eread,3

Edis

s(a

J)E

dis

s(a

J)

R 2.2 × 10−9 Ω m2T 350%

T 220%R 4.6 × 10−11 Ω m2

Gsheet (Ω−1)

Gsheet (Ω−1)

FIG. 8. Energy dissipation versus sheet conductance of the TIfor (a) large and (b) small RA and TMR at Vread = 150 mV.

the TMR and RA, while for large values of the TMR andRA, both MTJ leakage and charging of the output capac-itance will limit the total energy of the VTOPSS. Theenergy associated with charging or discharging output-node capacitances remains well under 2 aJ for all casesconsidered here (Cout = 113 aF), and is significant onlywhen both GTI and GAP are low [Fig. 8(b)].

B. Effect of MTJ design on EDP

One can reduce the EDP of the VTOPSS by designingjunctions that exhibit a large TMR—an increase in TMRat a fixed RA reduces both the switching delay and theenergy dissipation. As shown in Fig. 9(a), the scaling ofthe EDP with TMR in the VTOPSS can be expressed asPED ∝ 1/T b, where the value of the exponent b, typicallyin the range from −0.5 to −1, depends on the material andgeometrical parameters of the device.

As shown in Fig. 9(b), the EDP initially decreases withan increase in the RA. With further increase in the RA, theEDP exhibits the reverse trend and begins to increase. ForRA less than the optimal value, the EDP is inversely pro-portional to the RA. Beyond the optimal RA, unfortunatelythe delay associated with charging/discharging capacitivenodes becomes much larger than the MI reversal delay.The optimal RA depends on the material and geometry ofthe device. For the results shown in Fig. 9, the optimal RAdecreases with a reduction in Rsheet. Moreover, the EDP-RA contour becomes flatter around the optimal point asRsheet reduces. The results show that at a TMR of 600%and without any leakage through the TI, the optimal EDPof the VTOPSS is around 4 × 10−28 J s at Vread = 50 mVand 8 × 10−28 J s at Vread = 150 mV. For the same param-eters, the energy dissipation and the delay of the VTOPSSare 0.9 aJ (5 aJ) and 486 ps (192 ps), respectively, atVread = 50 mV (150 mV). In typical MTJs, TMR increaseswith increasing RA, which can be harnessed to reduce theEDP of the VTOPSS. In Ref. [61], it was shown that aTMR of 600% can be obtained with a RA of 104 � μm2

in (Co,Fe)B/MgO/(Co,Fe)B-type MTJs by annealing thestructure above 500 ◦C. For applications involving STT

054009-10


(a)

(b)

1 2 3 4 5 6 70

5

10

15

10–12 10–11 10–10 10–9 10–810–1

100

101

102

103

ηst = 10 (300 K)

Solid ⇒ Rsheet = 100 kΩ/sqDashed ⇒ Rsheet → ∞

ηst = 2.6 (0 K)

Solid ⇒ Rsheet = 100 kΩ/sqDashed ⇒ Rsheet → ∞

×10−27

×10−27

P ED

(Js)

P ED

(Js)

ηst = 10

R = 10−9 Ω m2

(Ω m2)

PED ∼ T −0.5

PED ∼ T −1

(×100) (%)

FIG. 9. Effect of (a) TMR and (b) RA on the EDP of theVTOPSS at Vread = 150 mV. For (b), TMR is 600%.

magnetic RAM, a large RA is undesirable as it increasesthe voltage required to switch the magnetization state viacurrent-induced spin torques [62]. In the case of VTOPSStechnology, the MTJ cell is used only to generate a ratherlow output voltage that must be sufficient to switch the sub-sequent logic stage. As such, a large RA of the read uniton the MTJ stack may be beneficial for the design of aVTOPSS.

C. Interconnect considerations

To transmit information between VTOPSS logic, con-ventional CMOS-compatible metallic interconnects, suchas copper low-κ or aluminum, can be used. From exami-nation of Eq. (16), the effect of interconnect resistance onthe device performance appears in the time constant τeq forcharging and discharging the output-node capacitance. InFig. 10(a), we study the effect of interconnect length onlimiting the net delay of the VTOPSS. For very low readvoltages, the MI time constant dominates, allowing us toignore the interconnect impact for interconnects as longas a few micrometers [solid line in Fig. 10(a)]. However,as we increase the read voltage, allowing faster reversal

of the MI layer, interconnects as short as a few hundrednanometers become important in quantifying the perfor-mance metrics of the device. The maximum interconnectlength that can be tolerated for τeq � τMI is given as

Lmaxic =(

GTIτMI2cic

− 12ricGt

)

+√(

cic − ricGtGTIτMI2riccicGt

)2+ τMI

riccic. (20)

For Lic > Lmaxic , τeq exceeds τMI. As shown in Fig. 10(b),as ρeff → 0, the time-constant τeq → G−1t Cout. For finiteleakage through the TI, the maximum interconnect lengthis limited to approximately 1 μm for ρeff up to 10−5 � m.For negligible TI leakage (Rsheet → ∞), the effect of theinterconnect is largely suppressed, implying that highlyresistive and long interconnects up to several hundreds ofmicrometers can be used in VTOPSS technology withoutnegatively impacting the overall performance. As a result,

10–7 10–6 10–5

eff ( m)

10–6

10–5

10–4

10–3Solid line⇒ Rsheet = 1 kΩ/

Dashed line ⇒ Rsheet → 100 kΩ/Dashed-dotted line ⇒ Rsheet → ∞

Vread = 150 mV; τMI = 172 ps

10–7 10–6 10–5

Lwire

(m)

0

2

4

6

8

10

eq/

MI

Solid line ⇒ Vread = 50 mV; τMI = 517 psDashed line ⇒ Vread = 100 mV; τMI = 257 ps

Dashed-dotted line ⇒ Vread = 150 mV; τMI = 172 ps

Lm

axic

(m)

(a)

(b)

FIG. 10. (a) Impact of interconnect length on the time con-stant τeq, which quantifies the charging or discharging rate of theoutput-node capacitance. (b) Maximum interconnect length thatyields τeq = τMI. For interconnects longer than Lmaxic , the charg-ing/discharging time of the output node exceeds the MI reversaldelay.

054009-11


there exists a wide range of interconnect options, such ascopper, ultrascaled wires (wire width much less than theelectron mean free path), and doped semiconducting wires,to design VTOPSS logic.

D. Comparison against existing logic devices

1. CMOS metrics

The model used for computing the performance metricsof CMOS technology comprises a minimum-sized CMOSinverter driving a similarly sized load through a copper,low-κ interconnect. With the Elmore delay model, thedelay of the CMOS circuit is given as [63]

τCMOS = 0.69RS (CS + CL)+ 0.69 (RScic + ricCL) Lic + 0.38riccicL2ic, (21)

where RS and CS are the source resistance and capacitance,respectively, and CL is the load resistance (assumed to beequal to CS). The energy dissipation of the CMOS circuitis given as

ECMOS = (CS + CL + cicLic) V2DD, (22)

where VDD is the supply voltage.The CMOS-device metrics are taken from the ITRS for

the 2020 technology node (half pitch of metal 1 of 18 nm).For a minimum-sized inverter, RS ≈ 78 k�, CS =0.68 fF/μm, CL = 0.38 fF/μm, ρeff = 25 μ� cm, cic =1.6 pF/cm, and the interconnect aspect ratio is 2 [64]. Thedelay of the CMOS circuit resulting from omission of theinterconnect-related delay is approximately 1.1 ps at anenergy dissipation of 10 aJ per bit. This yields an EDP of1.1 × 10−29 J s. For an interconnect length of 100 nm, thedelay of the CMOS circuit is 2.1 ps at an energy dissipationof 20 aJ per bit and an EDP of 4.2 × 10−29 J s.

2. CMOS scaling

To study CMOS scaling over process nodes, we consideronly the intrinsic delay of a CMOS transistor: τCMOS =CparVDD/IDSAT (drain saturation), where VDD is the supplyvoltage and Cpar and IDSAT are the parasitic capacitance andthe maximum on current, respectively, of the transistor. Atthe same technology node, increasing the transistor widthdoes not change its intrinsic delay as both Cpar and IDSATare proportional to the device width. If we consider differ-ent technology nodes from ITRS, we see that the switchingdelay of CMOS transistors is roughly the same as the min-imum feature size scales from 17.9 nm (year 2020) to 8.9nm (year 2026), as shown in Fig. 11. This scaling is con-sistent with the fact that the on-chip clock frequencies havenot increased over the last several years with scaling.

The intrinsic energy dissipation of CMOS transistors isgiven as ECMOS = CparV2DD. At the same technology node,

2020 2021 2022 2023 2024 2025 2026ITRS technology year

0.5

1

1.5

2

Perf

orm

ance

Delay (ps)

Energy (normalized)

FIG. 11. Scaling of the delay and energy dissipation of a silicontransistor with technology year. The data are taken from the 2013ITRS update.

increasing the transistor width will increase its energy dis-sipation due to the increase of the parasitic capacitance.This is contrary to the scaling of energy with dimensions inthe VTOPSS technology (see Table I). To interpret ECMOSacross technology nodes, we use ITRS projections for theyears 2020–2026. ITRS data indicate that Cpar ∼ W1.37 andVDD ∼ W0.2 (W is the transistor width.) Therefore, as theCMOS technology scales, its intrinsic energy dissipationdecreases. The results in Fig. 11 show this scaling behav-ior. However, the rate of decrease of energy dissipationtends to slow down towards the ITRS year 2024 with aminimum feature size of 11.3 nm.

3. Spin-based devices

Existing spin-based devices that are considered forcomparison include ASL [65], CSL [66], and MESOlogic [51] devices. ASL uses filtering of electric cur-rent through a nanomagnet to generate spin-polarizedcurrent, which communicates spin information betweeninput-output nanomagnets via a nonmagnetic conductor(e.g., copper, aluminum) that serves as the interconnect.Unlike charge current, spin current is not conserved; there-fore, the design of interconnects in ASL requires carefulconsideration [67]. On the other hand, CSL uses the spinHall effect to convert electric current carrying informationinto spin-polarized current, which is used to switch thestate of an input nanomagnet. The orientation of the inputnanomagnet is communicated to an output nanomagnet viatheir mutual magnetic dipolar coupling. The magnetizationstate of the output nanomagnet is read through a MTJ,which generates an output electric current with the polar-ity and amplitude dependent on the orientation of theoutput nanomagnet and the voltage applied on the MTJ.Since information is communicated via electric current,there is no loss of information in the interconnect. How-ever, because of the flow of electric current through a

054009-12


heavy-metal layer with a high effective resistivity, CSLhas high Joule heating. The MESO logic device, recentlyproposed in Ref. [51], uses magnetoelectric transductionto convert electric current into spin current at the inputside, while spin-orbit coupling is used at the output end forspin-to-charge transduction. That is, the input and outputstate variables are encoded in electric current. Benchmark-ing activities have shown that magnetoelectric mediatedspin devices have energy dissipation comparable to that ofCMOS devices [8].

Table III shows the performance metrics of the VTOPSSin comparison with spin-based devices. The performanceof the VTOPSS exceeds that of existing spin-baseddevices. The performance metrics of the ASL and MESOlogic devices in Table III do not include switching andwrite errors and can be considered to be representativeof operation at 0 K. The performance metrics of the CSLdevice reported in Ref. [31] assume ideal dipolar couplingbetween the read and write magnets and ignore switchingerrors. The physics of magnetic dipolar coupling and itsimpact on the reliability of CSL device is reported in Refs.[68,69]. In Ref. [70] and noted in Table III, performanceestimates of the CSL device are obtained in the presenceof practical dipolar coupling with eb0 = 5 and Perr = 0.05.The energy dissipation of the VTOPSS is 100 times lower

than that of ASL and CSL devices, while the delay of theVTOPSS is 2–10 times lower than that of ASL and CSLdevices, respectively. The delay of the VTOPSS is compa-rable to that of the MESO logic device and can be reducedfurther by use of MI layers with lower damping and/or MIswitching via precessional dynamics. In terms of energydissipation, the VTOPSS performs slightly better than theMESO logic device. The energy dissipation can be furtherreduced through material optimization, particularly with ahigher TMR and RA of the MTJ used for sensing the stateof the MI layer in the VTOPSS.

V. UNIVERSAL BOOLEAN LOGICIMPLEMENTATION

A complete set of two-input Boolean functions can beimplemented with use of the schematic shown in Fig. 12,where VA and VB refer to primary signal inputs and VXdenotes the tie-breaking input signal. To change the func-tionality between true and complementary outputs, thepolarity of the supply voltage signals on the MTJ isswapped. To implement a NAND gate, VX is set to its neg-ative value, while for a NOR gate, VX is set to its positivevoltage. For XOR and XNOR functionality, one of the pri-mary inputs is applied as a voltage signal on the TI, while

TABLE III. Overview of performance metrics of various spin-based devices. The performance metrics of the VTOPSS exceed thoseof existing spin-based technologies. The EDP of low-power CMOS technology at the 2020 ITRS technology node is approximately4 × 10−29 J s (see the text for calculations). For ASL and MESO logic devices, the energy barrier of the magnet is 40kBT and thevariation in their performance due to thermal noise is ignored; therefore, their performance is representative of results at 0 K. For theCSL device, the performance is reported at 95% accuracy of computation using magnets with an energy barrier of 5kBT. The physicsof dipolar coupling is included according to Refs. [68,69]. For the VTOPSS, the write-error probability is 10−7 at 300 K, while thethermal stability is 3.4 × 104 s. The energy dissipation and EDP of the VTOPSS can be reduce by an order of magnitude by suppressionof leakage through the TI.

VTOPSS (this work)

Metric ASL [50] CSL [70] MESO logic [51] Vread = 0.15 V Vread = 0.05 V(300 K/0 K)

Input-output Voltage Electric current Electric current VoltageTransduction V → m → Ispin → m → V Ielec → m → Ielec Ielec → m → Ielec V → m → VEnergy perbit

0.34 fJa 1.31 fJ 27 aJ 38 aJ/16 aJ 10 aJ/3.5 aJ

Switchingdelay

0.5 ns 3 ns 250 psb 272 ps/145 ps 617 ps/235 ps

Energy-delayproduct (J s)

17 × 10−26 3.9 × 10−24 6.75 × 10−27 10−26/2.3 × 10−27 6.3 × 10−278.3 × 10−28

Area 3.8 × 10−3 μm2 1.6 × 10−3 μm2 1.4 × 10−2 μm2 (1 − 2) × 10−3 μm2c(1 − 2) × 10−2 μm2d

Fan-out No Yes Yes Yes

aResults for perpendicular-magnetic-anisotropy magnets.bTotal pulse width reported in Ref. [51].cConservative estimate for a vertically integrated device.dEstimate reported for a laterally integrated device assuming the areas of the TI layer and the MTJ are 100 × 100 nm2 and the spacingbetween the TI and the MTJ is 50 nm.

054009-13


V–

Vout

y

z

x

V+V XGND

Topological insulatorMagnetic insulator

Fixed magnetFree magnet

Exchange coupling

Write unitRead unit

V BGND

V A GND

FIG. 12. All two-input Boolean logic functions can be imple-mented with the same device layout. The primary inputs aredenoted as VA and VB, while the signal VX denotes the tie-breaking signal to change the Boolean functionality. To switchbetween inverting and noninverting logic (different polarities ofVout), the polarity of the signals V+ and V− at the MTJ can beinterchanged. GND labels show the ground contacts.

the other primary input serves as the supply voltage onthe MTJ in the read unit. In the case of copy-invert func-tions, the tie-breaking signal VX is set to 0 V. Alternately,the schematic shown in Fig. 1 can be used for copy andinvert Boolean operations. However, by use of a genericlayout as in Fig. 12, all 16 Boolean operations possi-ble for two input signals can be implemented directly bypermutation of the polarities of the MTJ supply and thecontrol voltage. Another major advantage of the VTOPSSis its ability to support logic locking [71] and encryptionat the device level by preventing optical-based reverse-engineering attacks [72]. The innate polymorphism of theVTOPSS will enable runtime reconfigurability where theactual function to be implemented is determined on the flywith a key or control input. Exploration of the resilienceof the VTOPSS against existing hardware attacks, promi-nently those based on the Boolean satisfiability test, willbe investigated in future work.

The device layout corresponding to the universal logicgate is shown in Fig. 13, where the device area for auniversal gate is approximately 0.06 μm2, assuming rel-atively large values of the cross-section areas of the TI-MIinterface, MTJ, and the interconnect. The area can bereduced significantly by the patterning of narrower TI

Magnetic insulatorTopological insulator

Free layerBarrier Fixed layer

FIG. 13. Device layout for the schematic shown in Fig. 12.Here it is assumed that the cross-section area of the TI layer is100 × 100 nm2 and the spacing between adjacent TI layers is 50nm. The MTJ cross-section area is the same as that of the TI-MIinterface. The total area is approximately 0.06 μm2. GND labelsshow the ground contacts.

and MI layers and reduction of the cross-section dimen-sions of the MTJ. The latter approach, in particular, isadvantageous for reducing the device footprint without anegative impact on the device performance metrics.

VI. CONCLUSIONS

Computational electronics can, in principle, be realizedwith any state variable that is stable over device-relevanttimescales, and with any low-loss communication mecha-nism between devices that allows fan-out. In this regard,storing and manipulating information in magnetic materi-als is promising. Magnetic materials have a large numberof electron spins that are locked together by their exchangeinteraction such that the reorientation energy per spin tomove the magnetization collectively can be on the order ofmillielectronvolts. Magnetization reversal solely throughelectric fields is critical toward paving the path for anultralow-energy computing substrate. The efficiency ofvoltage-spin conversion must be significantly higher toallow ultralow-voltage operation to be competitive withCMOS technology.

In this paper, a VTOPSS based on a hybrid TI-MI mag-netoelectric structure is presented. The device has the fol-lowing important features: (i) innate polymorphism (i.e., itcan implement all 16 two-input Boolean operations usingthe same layout), (ii) CMOS compatibility (input and out-put variables are in voltage domain), (iii) extremely largeintrinsic gain for charge-to-spin conversion owing to theultrahigh spin Hall conductivity of the TI material, (iv)ability to support fan-out, (v) sub-10-mV operation withenergy of less than 10 aJ per bit, (vi) ability to lower theEDP to on the order of 10−29 J s (competitive with CMOStechnology), (vii) elimination of electric-current-carryingwires as the operation is fully based on voltage-to-voltageconversion with transmission of information via capaci-tive charging and discharging of wires, amd (viii) ultralowdamping of the MI layer allowing ultrafast operation on theorder of a few hundred picoseconds via antidamping spintorque.

We develop analytic models to quantify the perfor-mance of the VTOPSS and benchmark the results againstexisting CMOS and spin-based devices. Our results con-clusively show that for the current state-of-the-art mate-rial parameters, the VTOPSS exceeds the performanceof all-spin logic, charge-spin logic, and magnetoelectricspin-orbit logic devices. Improvements in material param-eters and device design can readily facilitate sub-attojoule-energy-per-bit operation with an energy-delay product ofapproximately 10−29 J s for the VTOPSS to be competi-tive against CMOS devices at the 2020 ITRS technologynode. Future work will address important issues perti-nent to multidomain effects in both uniaxial and biaxialmagnetic insulators and the effects of thermal stochastic-ity for subcritical excitation. Unlike CMOS devices, the

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VTOPSS can also provide logic locking due to the uniformdevice-level layout that makes it virtually impossible toprobe the functionality with reverse-engineering hardwareattacks. The ability of the VTOPSS to thwart state-of-the-art Boolean satisfiability attacks is yet to be examined andwill be considered in future work.

ACKNOWLEDGMENTS

This work was supported partially by the MRSEC Pro-gram of the National Science Foundation under AwardNo. DMR-1420073. A.D.K. acknowledges support fromGrant No. NSF-DMR-1610416. The authors thank Profes-sor Nitin Samarth at Pennsylvania State University for use-ful discussions during the preparation of the manuscript.S.R. thanks Nikhil Rangarajan at New York Universityfor his help in generating some of the graphics in thepaper.

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I. INTRODUCTIONII. PHYSICS OF OPERATIONIII. PERFORMANCE MODELINGA. Device latencyB. Thermal stabilityC. Minimum input voltageD. Minimum read voltageE. Energy dissipationF. Dimensional scaling

IV. PERFORMANCE BENCHMARKINGA. Latency and energy dissipationB. Effect of MTJ design on EDPC. Interconnect considerationsD. Comparison against existing logic devices1. CMOS metrics2. CMOS scaling3. Spin-based devices

V. UNIVERSAL BOOLEAN LOGIC IMPLEMENTATIONVI. CONCLUSIONSACKNOWLEDGMENTS. References

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