Phd 3rd year Research Activity

Class-G Headphones Amplifier

Università di Pavia - Dipartimento di Elettronica Dottorato di Ricerca in Microelettronica - XXIII Ciclo

Ph.D. Candidate: Alex Lollio

TUTORE: CHIAR.MO PROF. RINALDO CASTELLO COORDINATORE: CHIAR.MO PROF. FRANCO MALOBERTI

Headphone audio amplifiers Target application

Typical operating conditions

VIN

VHV

-VHV

Key objectives:

•  Low distortion

•  Low noise

•  High efficiency

•  Single ended •  RL = 32/16 Ω •  BW = 20Hz–20kHz •  PO,MAX > 40mW (on 16 Ω)

Modern cellular phones incorporates music playback and users may wish to use this feature for many hours

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Outline

•  Headphone amplifier (Class-AB, Class-D, Class-G PROs and CONs)

•  Class-G headphone driver (architecture, switching principle, distortion analysis)

•  Prototype in 65nm CMOS technology (implementation, results, comparison)

•  Class G improved version (new SNR Spec, proposed solution, results and comparison)

•  Conclusions

  Class AB (Linear amplifier) PROs: Best linearity

No EMI problems

CONs: Low efficiency

Typically the preferred solution in headphone application

  Class D (Switching amplifier) PROs: Best efficiency

CONs: Less linearity than class AB

EMI problems

Emerging solution in headphone application

Headphone audio amplifiers Alternative topologies

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  Class G: It is a linear amplifier which uses two voltage supply rails which switches to the appropriate voltage as required by the instantaneous output voltage

PROs: High efficiency but less than class D

High linearity but less than class AB

No EMI problems

CONs: It needs two voltage supply rails

Headphone audio amplifiers Alternative topologies

VIN

VLV

VHV

-VLV -VHV

VHV

-VHV

VLV

-VLV

VOUT VOUT

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Class G alternative topologies

  Series topology (classical)

  Parallel topology

•  Only one output stage

•  Switches are in series with the power transistors

•  Two output stages work in parallel

•  No switches in series with the power transistors

•  It needs a careful switching circuit design

VHV

-VHV

VLV

-VLV

VHV

VLV

-VHV

-VLV

RL

RL

This is the adopted solution

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Class G: working principle

For Vout below the switching point the low voltage stage is active. For Vout above the switching point both the low voltage and high voltage stages drive the load (in different moments).

VHV

VLV

-VHV

-VLV

LV stage

HV stage

iHV

iLV

iLV

iHV

iLV

iHV Iout[A]

Iout[A] iLV t t

Switching point

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9

Class G: switching distortion

Distortion zoom in

Distortion caused by the switching

Up to the switching point the class G linearity is the same as a class AB

Compared to class AB, class G has an additional source of distortion.

Switching point

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The implemented current based switching enables low distortion and high efficiency

Class G: critical design choices •  Switching point level: To achieve high efficiency, it must be as close as possible to the low voltage supply

Switching point equal to VLV (efficiency=78%)

Switching point far from the low voltage supply

•  Switching strategy: to minimize the distortion, switching must be as smooth as possible

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Outline





•  Conclusions

Overall amplifier architecture

•  Three stage opamp with differential input and single ended output.

•  The two identical second stages, gm2, and the third stages, gm3L and gm3H, work in parallel.

•  Only the low voltage stage gm3L is supplied by the low voltage rail ±VLV. The rest of the circuit is supplied by the high voltage rail ±VHV

gm2

gm2

gm1

-gm3L

-gm3H

Switching stage

R2

R1

R1 R2 RL

CM2

CM2 CM1

VOUT

Main path

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Amplifier architecture: main path

First stage

Input pairs gm1

VO

VLV

-VLV

VHV -VHV

Floating battery

VHV

VHV

-VHV

RL

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14

Second stage


gm2

Floating battery ref: Renirie, Langen, Huijsing, 1995

VO

VLV

-VLV

VHV -VHV

Floating battery

VHV

VHV

-VHV

RL

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15


Third stage

LV stage gm3L

HV stage gm3H

RL VO

VLV

-VLV

VHV

-VHV

-VHV

Floating battery

VHV

VHV

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-VLV + VTH

Amplifier architecture: switching stage conceptual schematic

PMOS switching

stage

NMOS switching

stage

RL VO

VO VLV - VTH

VO

VLV

-VLV

VHV

-VHV

-VHV

Floating battery

VHV

VHV

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-VLV + VTH

Amplifier architecture: switching stage conceptual schematic

PMOS switching

stage

RL VO

VO VLV - VTH

VO

VLV

-VLV

VHV

-VHV

-VHV

Floating battery

VHV

VHV

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•  Switching point sensing is in voltage domain. A differential pair compares the output voltage to the switching point voltage VLV-VTH

•  The switching between the high voltage and low voltage output stage is current based. The switching circuit injects all its bias current into the gate of the MOS to be switched off.

Switching principle details

VOUT

LV stage

HV stage

iJH

iJL

VOUT VLV - VTH

VHV

-VHV

-VLV

VLV

VHV

VHV

IBIAS

PMOS switching stage

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Output currents during switching

t

Iout[A]

Out

put c

urre

nts

iLV

iHV

t

VLV -VTH

VLV

Vout[V]

•  When VOUT is lower than the switching point (VLV-VTH) the switching circuit enables the LV stage and disables the HV stage

•  When VOUT is higher than the low voltage supply VLV only the HV stage drives the load

•  When VOUT is between VLV-VTH and VLV both stages drive the load

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Switching distortion: Amplifier model during the switching

•  We use a simplified linear model of the amplifier during the switching.

This current is used to represent the disturbance generated by the switching stage.

gm1 gm2 -gm3 RL

VOUT R1

R1

R2 CM1

CM2

iJ

Where

R2

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Outline





•  Conclusions

Chip micrograph

•  65nm CMOS process (1.8V analog transistors)

•  0.14mm2 active area per channel

•  Voltage supplies:

High voltage rail ±1.4V

Low voltage rail ±0.35V

•  Switching point 50mV under the low voltage supply

•  Max load capacitance 1nF

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23

Measurement results: Power dissipation versus output power

Fin=1kHz RL=32Ω

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Measurement results: THD+N and efficiency versus output power

•  Sinusoidal input signal (fin=1kHz) •  About 6dB extra distortion due to switching

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Performance summary and comparison with literature

Parameter This work (Class G)

JSSC 09 (Class AB)

[1]

ESSCIRC 06 (Class AB)

[2]

ISCAS 09 (Class D)

[3]

Technology 65nm 130nm 65nm 0.13um

Supply voltage ±1.4V ±0.35V

±1V ±0.6V 2.5V 3.6V

Quiescent power (per channel) 0.41mW 1.2mW 12.5mW 1.8mW

Peak load power (16Ω) 90mW 40mW 53.5mW 50mW

THD+N @ PRMS (32Ω) -80dB @ 16mW

-84dB @ 10mW

-68dB @ 27mW (16Ω)

-80dB @ 10mW

SNR A-weighted 101dB 92dB (un-weighted) - 96dB

[1] Vijay Dhanasekaran, JSCC ‘09 [2] P. Bogner, ESSCIRC ’06 [3] Pillonet, ISCAS ‘09

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Performance comparison with products

Parameter This work (Class G)

MAX9725 (Class AB)

TPA6141 (Class G)

LM48824 (Class G)

Supply voltage 1.4V with two

charge pumps + 1 buck

1.5V with one charge pump

3.6V with 1 charge pump +

1 buck

3.6V with 1 charge pump +

1 buck Quiescent power (per

channel) 0.41mW + 0.3mW (2 CPs + 1 buck) 1.57mW 2.16mW 1.62mW

PSUP @ PL=0.1mW 0.87mW + 0.4mW - 4.5mW 3.24mW

PSUP @ PL=0.5mW 1.63mW + 0.6mW - 7.2mW 5.58mW

Peak load power (16Ω)

90mW 70mW (CPs RON=2.5Ω) 50mW 50mW 74mW

THD+N @ PRMS (32Ω) -80dB @ 16mW -84dB @12mW -80dB @20mW -69dB@20mW

SNR A-weighted 101dB 92dB 105dB 102dB

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Outline





•  Conclusions

New Spec: increase the SNR of 10dB 3-stages improved performance

Aim:

increase the SNR

Classical approach:

increase gM1 and consequently CM1

ISCC ‘10 3-stages improved SNR @ 1VRMS 100dB 110dB

CM1 15pF 260pF CM2 4x18pF 4x18pF PQ 0.41mW 0.55mW

Big area

where

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4-stages Feed Forward (FF) solution

•  The additional stages increase the open loop gain of the amplifier at low frequencies

•  The stage gM11 dominates the noise performance

Additional stages

Ref: A. Bosi et all. VDSL2 Analog Front End, ISSCC, 2009

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4-stages Feed Forward (FF) solution

•  The amplifier cuf off frequency is gM1/CM1

•  The GLOOP shows a zero at

Low freq path

High freq path

High freq path gM1 Low freq path gM11/sC · gM12

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4-stages FF: GLOOP plot

4-stages FF solution:

1. gM11 determines the noise performances

2. More open-loop gain in the audio BW

Audio BW (20Hz-20kHz)

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4-stages FF: Less capacitors sizes

3-stages improved performance:

4-stages FF: gM11 determines the noise performance

Big area

Audio BW (20Hz-20kHz)

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4-stages FF: Less switching distortion

4-stages FF shows higher switching distortion compression

We can reduce gM2 saving power consumption

We can reduce CM2 saving area

3-stages: 4-stages FF:

3-stages 4-stages FF gM2 200uA/V 55uA/V CM2 4x18pF 4x5pF

THD@1kHz -82dB -85dB

We saved additional 52pF

Switching distortion

Switching distortion

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Performance summary

ISCC ‘10 3-stages improved 4-stages FF

SNR@1VRMS 100dB 110dB 110dB

CTOT 87pF 332pF 101pF

PQ 0.41mW 0.55mW 0.6mW

THD@1kHz -82dB -82dB -85dB

Conclusion:

The adopted solution shows the same performance as the 3-stages one using 1/3 of total capacitors area paying only 10% of additional power consumption.

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Outline




•  Conclusions

Conclusions

•  A class-G headphone driver has been presented. It shows 50% less power consumption than the best competitor.

•  The class-G improved version satisfies the most aggressive market requirements (110dB of SNR and better than 80dB of THD)

•  The class-G improved version will be integrated in Dec 2010 into a novel Marvell audio codec

Publications

•  Marvell Patent Ref No. MP3391: A. Lollio, G. Bollati, R. Castello, “CIRCUITS AND METHODS FOR AMPLIFYING SIGNALS”

•  A. Lollio, G. Bollati, R. Castello, “Class-G Headphone Driver in 65nm CMOS Technology”, Proc. ISSCC 2010, San Francisco, 7-11 Feb. 2010, pp.84-85

•  A. Lollio, G. Bollati, R. Castello, “A Class-G Headphone Amplifier in 65nm CMOS Technology” IEEE J. Solid-State Circuits, vol. 45, no. 12, Dec. 2010.

Activities Summary

Seminari organizzati dal dottorato (3.8 CFU)

Scuole di Dottorato (12 CFU)

Corso Elementi di Elettronica di Potenza (5 CFU)

Corso di Misure Elettriche (5 CFU)

Tutorato di Elettronica (2 CFU)

Presentazione a Congresso Internazionale: ISSCC2010 (3 CFU)

Pubblicazione su rivista internazionale: JSSC2010 (4 CFU)

Presentazioni annuale sull’attività di ricerca svolta (1.5 CFU)

Totale CFU: 36.3

Buck and CPs: Power consumption estimation (per channel) 2 Charge pumps PQ -> 0.2mW 1 Buck (80% efficiency), PL=0 Pdiss -> 0.1mW 1 Buck (80% efficiency), PL=0.1mW Pdiss -> 0.2mW 1 Buck (80% efficiency), PL=0.5mW Pdiss -> 0.4mW Total power consumption

PQ -> 0.2mW+0.1mW = 0.3mW PL=0.1mW -> 0.2mW+0.2mW = 0.4mW PL=0.5mW -> 0.2mW+0.4mW = 0.6mW

Measurement results: THD+N versus frequency

RL=32Ω BW= 20Hz – 20 kHz

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Measurement results: Spectrum at different output power

PO=20mW Fin=1kHz

PO=1mW Fin=1kHz

[1] Vijay Dhanasekaran; Jose Silva-Martinez; Edgar Sanchez-Sinencio, "Design of Three-Stage Class-AB 16Ohm Headphone Driver Capable of Handling Wide Range of Load Capacitance," Solid-State Circuits, IEEE Journal of , vol.44, no.6, pp.1734-1744, Jun 2009.

[2] P. Bogner, H. Habibovic and T. Hartig, ‘‘A High Signal Swing Class AB Earpiece Amplifier in 65nm CMOS Technology,’’ Proc. ESSCIRC, pp.372-375, 2006.

[3] Pillonet, G., et al,”A 0.01% THD, 70dB PSRR Single Ended Class D using variable hysteresis control for Headphone Amplifiers”, ISCAS 2009 pp.1181-1184.

[4] Maxim, ‘‘1V, Low-Power, DirectDrive, Stereo Headphone Amplifier with Shutdown,’’ Rev. 3; 8/08, accessed on Jul. 7, 2009 < http://datasheets.maximic.

com/en/ds/MAX9725.pdf>

[5] Texas Instrument, ‘‘Class-G Directpath Stereo Headphone Amplifier,’’ 3/09, accessed on Jul. 7, 2009 < http://focus.ti.com/lit/ds/symlink/tpa6141a2.pdf>

[6] National Semiconductor ”Class G Headphone Amplifier with I2C Volume Control,” August 31,2009, accessed on Jan. 25, 2010

< http://www.national.com/ds/LM/LM48824.pdf >

References

Phd 3rd year Research Activity

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